JPH07109966B2 - Amplifier circuit - Google Patents

Description

The present invention relates to an amplifier circuit to which an offset voltage cancel circuit is added. More specifically, it relates to improvement of the output characteristics of such an amplifier circuit.

[Conventional technology]

A high-speed amplifier that has the function of amplifying up to high frequencies
Since an amplifier that amplifies up to 10 MHz or more generally has a relatively large DC offset voltage V _OF , a circuit that automatically cancels this offset voltage V _OF is added to the amplifier. The offset voltage canceling circuit cancels the drift caused by the change in the offset voltage.

FIG. 3 is a diagram showing an amplifier to which a conventional offset voltage cancel circuit is added.

In the figure, U1 is a high-speed amplifier having an amplifying function up to a high frequency region, and has a DC offset voltage V _OF (a voltage appearing between two input terminals of the amplifier even when the input voltage Vin = 0v) between inputs.

On the other hand, the integrating circuit composed of the operational amplifier U2, the resistor R3 and the integrating capacitor C constitutes an offset voltage canceling circuit. As the amplifier U2, an amplifier having a low speed but a small offset is used.

The integrator circuit (offset voltage cancel circuit) inverts and integrates the DC offset voltage V _OF of the high-speed amplifier U1 (voltage of the inverting input terminal of the amplifier U1), and this voltage is non-inverting input terminal (+ input terminal) of the amplifier U1. In addition to. Therefore, the offset voltage cancel circuit outputs a voltage signal (−V _OF ) having the same magnitude as the offset voltage V _OF and the opposite polarity to the amplifier U.
Since the operation is stable when applied to the non-inverting input terminal of 1, the voltage between the two input terminals of the high speed amplifier U1 is V _OF +
(−V _OF ) = 0v, and the offset voltage V _OF is canceled.

The input / output relationship of such a circuit of FIG. 3 is shown in FIG. When the offset voltage V _OF is canceled (non-inverting input terminal potential = 0v), there is no new current flowing into the integrating circuit side (because the voltage between the input and output of the integrating circuit is the same). All the current i in flowing through the resistor R1 is the resistance R2
Also flows. Therefore, the equation (1) is established.

Vout / Vin = -R2 / R1 (1) The circuit in FIG. 3 operates with the zero point P1 shown in FIG. 6 as if it were a fulcrum. That is, when the input voltage Vin changes, this zero point P
With 1 as the fulcrum, the slope of the diagonal line consisting of the resistors R1 and R2 changes, and the output voltage Vout is output.

The advantage of the circuit shown in FIG. 3 as described above is that if the time constant of the integrating circuit is sufficiently large, the offset error is eliminated with respect to a reciprocal signal such as a sine wave.

However, when a step input such as that shown in FIG. 8 (1) is applied to the circuit of FIG. 3 as Vin, the output of the amplifier U1 does not change stepwise according to Vin, but is shown in FIG. 8 (2). As shown in, the waveform has a waveform that once rises and then changes with the time constant of the integrating circuit. The reason for this will be described with reference to FIG.

When a stepped signal as shown in FIG. 8 (1) is applied as the input voltage Vin, the integrator circuit responds with an integral time constant, so that the output of the integrator circuit becomes the step input at the time of the fall (rise) of the step. I can't follow.

On the other hand, in general, the high speed amplifier U1 has an open loop gain A.
There relatively low (e.g., gain A = 10 to 10 ² about)
When the input voltage Vin is applied to the input section B of FIG. 3, a voltage e proportional to the magnitude thereof appears at the inverting input terminal (-input terminal) of the high speed amplifier U1. Note that V _OF is the input voltage Vin =
This is the offset voltage generated at 0v.

The high speed amplifier U1 outputs a voltage of -Ae obtained by multiplying the voltage e by a gain A. Therefore, the moment the step input is added, P2
The point is a zero potential point, and the input / output relationship shown in FIG. 7 is obtained. If the open loop gain A of the high speed amplifier U1 is an infinite value (ideal value), it will be e0v, as explained in many reference books, and the fulcrum will be the point P1 in FIG. However, since the gain A is a finite value here, the point P2 in FIG. 7 becomes the fulcrum at the moment when the step input is applied. Therefore, the input / output gain G1 in FIG. 3 is expressed by the equation (2).

However, as time elapses, the voltage e = 0v shown in FIG. 7 becomes (inverted input terminal voltage = 0v) due to the action of the integrating circuit (offset voltage canceling circuit). Therefore, the 7th
Since P1 point shown in the figure is 0v, after the integration time constant,
The state of the figure becomes FIG. Therefore, the final gain G2 of the circuit shown in FIG. 3 is expressed by the equation (1).

G2 = -R2 / R1 (1) That is, the circuit of FIG. 3 has different DC gain G2 and AC gain G1.

Therefore, when a step input is applied to the circuit of FIG. 3, its output Vout becomes as shown in FIG. 8 (2).

However, if the waveform obtained by amplifying the waveform of FIG. 8 (1) by the high-speed amplifier U1 is the waveform of FIG. 8 (2), it is inconvenient.

To summarize the reason why the waveform in Fig. 8 (2) is obtained, at the moment when there is a step input, the potential at the inverting input terminal of the high-speed amplifier U1 is not 0v, but a certain voltage e is generated. e is applied. This is because the integrator circuit operates so that the voltage e is equivalently 0v.

Therefore, conventionally, the characteristics of step input have been improved by the configuration of FIG. The circuit of FIG. 4 is that the voltage between the input voltage Vin and the output voltage Vout is divided by the resistors R3 and RN, and the divided voltage is applied to the integrating circuit (amplifier U2).
Other configurations are the same as those in FIG. High-speed amplifier
U1 is represented by an equivalent circuit, UR described inside is an ideal amplifier having an output impedance of 0Ω, and r01 is an actual output impedance of the high-speed amplifier U1.

Then, the voltage V2 (see FIG. 4) divided by the resistors R3 and RN becomes the potential (0v) at the point P2 in FIG. α is an arbitrary constant.

The operation will be explained. The circuit of FIG. 4 shows the point P2 of FIG. 9 (the same as the point P2 of FIG. 7) at the moment when the step input is applied.
Is 0v. Therefore, the output voltage Vout is -Ae as shown in FIG. 9 (same as -Ae in FIG. 7). The operation up to this point is the same as in FIG.

However, the operation after that is different. In the circuit of FIG. 4, the voltage V2 applied to the integrating circuit is divided by the resistors R3 and RN, and the resistors R3 and RN are preset as shown in equations (3) and (4). The voltage applied to the integrating circuit is the voltage at point P2 in FIG. That is, the voltage e at the point P1 in FIG. 9 is not applied to the integrating circuit, and the voltage at the point P2 when the step input is applied is applied as it is.
A step response output voltage waveform as shown in FIG. 8 (3) is obtained from the high speed amplifier U1.

[Problems to be Solved by the Invention]

 The conventional FIG. 4 circuit as described above has the following problems.

The above description is based on the assumption that the high speed amplifier U1 shown in FIG. 4 is operated in an ideal state, that is, no load, and the output impedance is 0Ω. However, in a practical circuit, as shown by U1 in FIG. 4, the load RL is usually connected to the high-speed amplifier U1, and the output impedance r01 (for example, about 10Ω) exists in the actual high-speed amplifier U1. i _L voltage drop (r01 · i _L) is generated, the output voltage Vout is reduced.

This is equivalent to the apparent decrease in the gain A of the high speed amplifier U1. Therefore, when the circuit of FIG. 4 is put to practical use, the resistance values R3 and RN that determine the voltage V2 applied to the integrating circuit are
Although the value is determined in advance by anticipating the voltage drop due to the load current i _L , if the load RL changes or the value of the load RL is not fixed at the design stage of the circuit in FIG. 4, the correction cannot be performed. is there. That is, the input voltage V2 of the integrating circuit of FIG.
Could not be adjusted to the point P2 in FIG. 9, and as a result, the output waveform as shown in FIG. As described above, in the circuit of FIG. 4, when the high-speed amplifier U1 is in an ideal state, the DC gain and the AC gain can be made equal, but at the stage of practical application, the DC gain and the AC gain are equal due to the influence of the load. I couldn't.

Although it has been stated on page 3 that the amplifier U2 used in the offset cancel circuit has a particularly small offset, the amplifier with a small offset generally has a narrow frequency band. That is, the characteristic is that the gain is maintained only in the region extremely close to the direct current. The high speed amplifier U1 is the fifth
The open loop gain A is small as described on the page.
Therefore, although the amplifier circuit of FIG. 4 has a certain level of gain up to the high frequency region, there is a problem that the open loop gain in the low frequency region is low.

A first object of the present invention is to provide an amplifier circuit capable of accurately amplifying a step input (outputting the waveform of FIG. 8 (3)) even if the load RL fluctuates or its value is undetermined. That is.

A second object of the present invention is to provide an amplifier circuit having a high open loop gain in the low frequency region while achieving the above object.

[Means for Solving the Problems]

In order to solve the above problems, the present invention provides an input resistance (R1) connected between an input section (B) and an inverting input terminal, a feedback resistance (R2) connected between input and output, and one end of the input resistance. The output impedance (r01) and the offset voltage V are provided with an integrating circuit which is composed of a resistor (R3) connected to the section (B), an integrating capacitor and an amplifier (U2) and adds the integrated output to the non-inverting input terminal. _The amplifier (U1) having _OF , the small resistance (r02) connected between the output terminal of this amplifier (U1) and the load (RL), and the voltage across the small resistance (r02) are introduced, The output of the integrator circuit is provided with an arithmetic circuit that adds a signal having a value that maintains the negative offset voltage −V _OF to the integrator circuit.

[Action]

In the present invention, the magnitude of the load current i _L is observed by the minute resistance provided at the output terminal of the high speed amplifier. Then, the voltage across the minute resistor is introduced, and the output of the integrating circuit (see FIG. 8 (4)) calculates a signal having a value that maintains the negative offset voltage −V _OF, and the signal is added to the integrating circuit. Therefore, even if the load fluctuates, the offset voltage V _OF
It cancels only, and does not cancel the voltage e generated at the input of the high speed amplifier according to the input voltage.

Therefore, the waveform as shown in FIG. 8 (3) can be output.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of an amplifier circuit according to the present invention, FIG. 2 is a diagram showing another configuration example of the present invention, and FIG. 5 is a diagram showing an operating principle of the present invention.

1 and 2 is different from FIG. 4 in that a high speed amplifier is used.
A small resistor r02 is provided between the output terminal of U1 and the load RL, and the voltage SA across the small resistor r02 is introduced so that the output of the integrating circuit maintains a negative offset voltage −V _OF. That is, the arithmetic circuit 1 for outputting is output. Since other configurations are similar to those in FIG. 4, only configurations different from those in FIG. 4 will be described in detail.

The arithmetic circuit 1 introduces the voltage across the micro resistor r02 and outputs the following signal SA to the inverting input terminal of the amplifier U2 that constitutes the integrating circuit.

This signal SA will be described. Integrator circuit (amplifier U2) is a resistor
The current i in applied via R3 and the current of the algebraic sum of the signal SA (current i _f here) applied from the arithmetic circuit 1 are integrated. Here, the current i in is the current flowing through the resistor R3 when the input voltage Vin is applied to the input section B.
_f is a small resistance r02 due to the input voltage Vin being applied.
Is a current output from the arithmetic circuit 1 based on the voltage generated at both ends of the.

The arithmetic circuits 1 and 2 which are the constituent elements of the present invention have an _if ==-i in
The current is output in the relationship of. When the input voltage Vin = 0v, the output of the integrating circuit is the voltage (−V
_OF ) to cancel the offset voltage V _OF of the high speed amplifier U1. Even if the input voltage Vin is applied in this state, the current i in
Since the algebraic sum of i _f is 0, the output of the integrating circuit is (−V
_OF ) is maintained (see (4) in FIG. 8).

Any configuration may be used as long as it is an arithmetic circuit capable of outputting a signal (i _f ) having such a relation of _if == − i in. However, in the present application, a specific example thereof is shown in FIGS. 1 and 2. An example was given.

The arithmetic circuit 1 shown in FIG. 1 includes an amplifier U3 in which the potential across the minute resistor r02 is introduced to the inverting / non-inverting input terminals via resistors R6 and R7. Further, this amplifier U3 is provided with a feedback resistor R5 between its input and output, and its output signal is applied to the inverting input terminal of the amplifier U2 of the integrating circuit via the resistor R4.

In the arithmetic circuit 2 of FIG. 2, the potential of the small resistor r02 on the high speed amplifier U1 side is taken out by the resistor R14 and this is taken out by the amplifier U2 of the integrating circuit.
In addition to the inverting input terminal of
The L side potential is led to the inverting input terminal of the amplifier U3 by the resistor R17, amplified by the amplifier U3 having the feedback resistor R16, and the output resistor R15.
The output is added to the inverting input terminal of the amplifier U2 of the integrating circuit via.

Although the signal SA output from the arithmetic circuits 1 and 2 has been described as a current in the above description, FIG. 5 illustrates it as a voltage. The operation of the amplifier circuit of FIG. 1 will be described with reference to FIG.

As described above, the actual high-speed amplifier U1 can be drawn by dividing it into the ideal amplifier UR having an output impedance of 0Ω and the output impedance r01 connected to its output end.

Amplifier U3 and resistors R5 and R6 that form the arithmetic circuit 1 of FIG.
Has a function of generating the output voltage VR of the ideal amplifier UR (that is, the output V3 of the amplifier U3 = VR). The reason will be explained. The resistors R3, R4, R5, R6 are preset as follows.

R3 = α {R1 + R2 / (A + 1)} R4 = α ・ R2 ・ A / (A + 1) R5 = β ・ r01 (5) R6 = β ・ r02 (6) β: arbitrary constant The output voltage VR of the ideal amplifier UR is It can be expressed by equation (7).

VR = Vout + {(V4-Vout) / r02} (r01 + r02) ...
(7) Vout and V4 are the voltages at the points shown in FIG.

The current i _D flowing through the resistor R2 shown in FIG.
Since the current i _L output from U1 is (r01 + r02 + RL) << R2, there is a relationship of i _D << i _L. Therefore, the current flowing through the resistor r02 will be described as i _L.

The values of the resistors R6 and R5 can be set so that only i _L / β of the current i _L flowing through the resistor r02 flows into the resistor R6 side.
Therefore, the output voltage V3 of the amplifier U3 can be expressed by equation (8).

V3 = Vout + (R5 + R6) ・ (i _L / β) (8) Equations (5) and (6), and i _L = (V4-Vout) / r02 are substituted into equation (8), V3 = VR Become.

Since the voltage Vout from the high-speed amplifier U1 applied to the resistor RN in FIG. 4 (conventional example) is affected by r01.i _L , the potential at the point P2 in FIG. 9 is maintained and the inverting input terminal of the amplifier U2 is maintained. Could not be added to.

On the other hand, according to the circuit of FIG. 1 according to the present invention, the voltage V3 applied to the resistor R4 is the output impedance r01 of the high speed amplifier U1.
Is automatically calculated to a voltage equal to the voltage VR (output voltage of the ideal amplifier UR) that is not affected by. Therefore, according to the present invention, no matter how the load changes, the inverting input terminal of the amplifier U2 of the integrating circuit is automatically connected to point P2 of FIG. 5 (P2 of FIG. 9).
Can be kept at the same voltage). As a result, the 8th
It is possible to output a waveform as shown in FIG.

The arithmetic circuit 2 of FIG. 2 can also achieve the same effect as the circuit of FIG.

In the circuit of FIG. 1 described above, since VR = V3, the equation (9) is established from the equation (7).

V3 = Vout + {(V4-Vout) / r02} (r01 + r02) = V4
(R01 + r02) /r02-Vout.r01/r02 (9) Then, in the circuit of FIG. 1, the current of _if = V3 / R4 was applied to the amplifier U2 of the integrating circuit.

Also in the arithmetic circuit 2 of FIG. 2, the same current _if as in the arithmetic circuit 1 of FIG. 1 can be applied to the amplifier U2 of the integrating circuit.

That is, in FIG. 2, each resistance is set as follows.

Therefore, the output voltage VA of the amplifier U3 is expressed by equation (11).

VA = −Vout · r01 / r02 (11) This is the value of the second term on the right side of the equation (9). This voltage
VA is applied to amplifier U2 through resistor R15, which has the same value as resistor R4 in the circuit of FIG.

In the circuit of FIG. 1, the current i ₁ applied to the amplifier U2 based on the voltage of the first term on the right side of the equation (9) is i ₁ = {V4 (r01 + r02) / r02} / R4 (12). Therefore, in the arithmetic circuit 2 of FIG.
If 4 is set to the value of equation (10), the current value flowing through this R14 is the current value of equation (12).

Thus, the circuit shown in FIG. 2 can perform the same operation as that shown in FIG.

FIG. 10 is a diagram showing an amplifier circuit that achieves the second object of the present invention. The difference between FIG. 10 and FIG. 4 is that the structure surrounded by a dotted line is newly added. The operation of the part indicated by the dotted line is the same as the operation of the integrating amplifier U2 for canceling the offset voltage with respect to the high speed amplifier U1. That is, the offset voltage VO of the offset voltage canceling amplifier U2 itself
F2 is further canceled by the circuit in the newly provided dotted line.

The configuration of a portion surrounded by a dotted line newly added to FIG. 4 will be described. An integrating capacitor C2 is provided between the output terminal and the inverting input terminal, and an amplifier U4 having a non-inverting input terminal connected to a common potential is provided. The potential at the connection point between the resistors R3 and RN is introduced into the inverting input terminal via the resistor R21, and the output voltage of the amplifier U4 is applied to the non-inverting input terminal of the amplifier U2 via the resistor R22. The basic operation of the part surrounded by the dotted line is the same as in FIG. 3, and the DC offset voltage VOF2 of the amplifier U2 is inverted and integrated, and this voltage is applied to the non-inverting input terminal of the amplifier U2. Therefore, the offset voltage VOF2 is canceled.

The operation of FIG. 10 will be described with reference to FIG. High speed amplifier
U1 has a small open-loop gain, but the frequency as shown in FIG.
Has gain characteristics.

On the other hand, the characteristic of FIG. 11 (B) is the frequency characteristic of the low offset amplifier designed to have a small offset voltage.
The characteristic shown in FIG. 11C is the frequency characteristic of a general-purpose amplifier.

Compare general-purpose amplifiers, low-offset amplifiers, and high-speed amplifiers.

Comparing the frequency-gain characteristics, the high-speed amplifier holds the gain up to the highest frequency region, the general-purpose amplifier is next, and the low-offset amplifier is the last. However, the high-speed amplifier has a problem that its gain is small even in a low frequency region.

Comparing the offset voltages, the smallest is the low-offset amplifier, the second is the general-purpose amplifier, and the largest is the high-speed amplifier.

In a composite amplifier circuit in which two amplifiers are combined like the circuit of FIG. 4, the combined frequency-gain characteristic of the two amplifiers is obtained. Therefore, when a low offset amplifier is used for the amplifier U2 in FIG. 4, it has the frequency-gain characteristic of (B) in the region near DC, and exceeds the frequency f1 (A).
The frequency-gain characteristics of This combination has a small gain in the low frequency region and is problematic as an amplifier circuit.

Therefore, in the present invention, a general-purpose amplifier is used as the amplifier U2.
Therefore, the combination of the general-purpose amplifier U2 and the high-speed amplifier U1 has the frequency-gain characteristic of FIG. 11C in the low frequency region,
When the frequency f2 is exceeded, the frequency-gain characteristic of (A) is obtained. According to this combination, a high gain can be secured by the action of the general-purpose amplifier U2 in the low frequency region.

However, as it is, the purpose of canceling the offset of the high speed amplifier U1 by the offset voltage VOF2 held by the general purpose amplifier U2 cannot be achieved.

Therefore, in the present invention, an amplifier U4 for canceling the offset voltage VOF2 of the general-purpose amplifier U2 is newly provided as shown in FIG. 10, and a low offset amplifier is used for this amplifier U4. As a result, according to the amplifier circuit of FIG. 10, the offset voltage is canceled by the action of the amplifier U4, and the frequency-gain characteristic is as shown in (D) of FIG.

In addition, the minute resistor r02 shown in FIGS. 1 and 2 is provided at the output terminal of the high speed amplifier U1 shown in FIG. 10, and the portion of the resistor RN shown in FIG. 10 is configured as shown in FIGS. It is obvious that

[Effect of the present invention]

As described above, according to the present invention, the DC gain and the AC gain can be equalized without being influenced by the load RL. That is,
Even if the load RL fluctuates or its value is undecided, the step input can be accurately amplified (the waveform of FIG. 8 (3) can be output).

[Brief description of drawings]

1 and 2 are diagrams showing a configuration example of an amplifier circuit according to the present invention, FIGS. 3 and 4 are diagrams showing a conventional example, FIG. 5 is a diagram showing a potential relationship of the present invention, and FIG. FIG. 7, FIG. 7 and FIG. 9 are diagrams showing the potential relationship of the conventional example, FIG. 8 is a time chart of each part,
FIG. 10 is a diagram showing another configuration example of the present invention, and FIG. 11 is a diagram showing frequency-gain characteristics. 1,2 ... Arithmetic circuit, U1, U2, U3, U4 ... Amplifier, r01 ... Output impedance, r02 ... Small resistance, R1 to R17 ... Resistance, RL ... Load, C ... Integration capacitor.

Claims (1)

[Claims] 1. An input resistance (R1) connected between an input section (B) and an inverting input terminal, a feedback resistance (R2) connected between input and output, and one end connected to the input section (B). A resistor (R3), an integrating capacitor, and an amplifier (U2) that add the integrated output to the non-inverting input terminal. The output impedance (r01) and the offset voltage V _OF
(U1) with a small resistance (r02) connected between the output terminal of this amplifier (U1) and the load (RL), and the voltage across both ends of this small resistance (r02) is introduced, and the integration An amplifier circuit comprising: an arithmetic circuit that adds a signal whose output maintains a negative offset voltage −V _OF to an integrator circuit.