JPH07109983B2 - Pulse delay circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse delay circuit applied to a digital signal processing circuit.

(Prior Art) FIG. 3 shows a conventional pulse delay circuit. In the figure,
31,32,33,34 are delay type flip-flops (hereinafter referred to as DFF
Is abbreviated), indicating that there are n DFFs. Reference numeral 35 is an input terminal of the pulse delay circuit, 36 is a clock input terminal, and 37 is an output terminal of the pulse delay circuit.

FIG. 4 is a diagram for explaining the operation of the DFF used in the conventional pulse delay circuit. In the figure, φ ₁ , D ₁ , Q
₁ is an example of the DFF in FIG. In FIG. 4, φ ₁ is the clock, D ₁ is the DFF input, and Q ₁ is the DFF output. The DFF inputs the state of D ₁ inside at the timing of the clock φ ₁ at a high potential (hereinafter abbreviated as “H”), and when the clock φ ₁ changes to a low potential (hereinafter abbreviated as “L”). ,
Outputs information inside DFF to output Q ₁ . Therefore, in FIG. 4, when D ₁ changes from “L” → “H” → “L”, the output Q ₁ is synchronized with clock φ ₁ as shown in FIG.
It changes from "H" to "L".

FIG. 5 shows operation waveforms of the conventional pulse delay circuit, which are φ ₁ ~
φ _n , D ₁ , Q ₁ , Q ₂ , Q _n-1 , Q _n are φ ₁ to φ _n , D ₁ , Q ₁ , Q ₂ , Q in FIG.
_It corresponds to _n-1 and Q _n , respectively.

(1), (2), shown in the clocks φ _{1 to} φ _n in FIG.
(N-1) and (n) are clock pulse numbers, and (1)
Is the timing when the DFF output Q ₁ changes from “L” to “H”, (2) is the timing when the DFF output Q ₂ changes from “L” to “H”, and (n-1) is the DFF The output Q _n-1 of the DFF changes from “L” to “H”, and (n) shows the output Q _n of the DFF changes from “L” to “H”.

In FIG. 5, the DFF inputs the state of D ₁ to the DFF at the timing of the clock φ ₁ in the “H” state, and outputs the information inside the DFF to Q ₁ at the timing of the clock φ ₁ in the “L” state.

In the conventional pulse delay circuit shown in FIG. 3, Q ₁ and D ₂
Since Q _n-1 and D _n are connected in the same manner, as shown in FIG. 5, the DFF output Q _n changes after the Q output changes from “L” to “H”. , Clock pulse n-1
It will change from “L” to “H” after the pulse. That is, in the conventional pulse delay circuit shown in FIG. 3, when n = 10, for example, n = 10 in FIG. 5 as well, so after Q ₁ changes from “L” to “H”, the clock Pulse in n
The output of Q _n (Q ₁₀ ) changes from “L” to “H” after −1 = 9 pulses.

As described above, the conventional pulse delay circuit shown in FIG. 3 can delay the input signal by approximately d = n × T, where n is the number of stages of the delay circuit and T is the period of the clock pulse. it can. Here, d represents a delay time.

Next, the pulse width accuracy after delay of the conventional pulse delay circuit shown in FIG. 3 will be described.

FIG. 6 shows operating waveforms for explaining the problems of the conventional pulse delay circuit. Φ ₁ shows the clock of the conventional pulse delay circuit shown in FIG. 3, and D ₁ shows the DFF. On input, Q ₁ shows the output of the DFF corresponding to the input of D ₁ . In the sixth view, D _'1 represents a DFF input of a conventional pulse delay circuit shown in FIG. 3, Q' ₁ are corresponding to the input of D _'1 DFF
Shows the output of. In FIG. 6, DFF inputs D ₁ and D ′ ₁
Have the same pulse length t. It can be seen that even if the input signal of the DFF has the same pulse width, the output signal width of the DFF changes due to the change in the phase relationship with the clock pulse φ ₁ . That is, in the conventional pulse delay circuit shown in FIG. 3, in order to improve the accuracy of the pulse width after delay,
It is necessary to make the width of the clock pulse sufficiently short with respect to the pulse width. That is, as shown in FIG. 6, the output Q of the DFF
₁ and Q ′ ₁ are t−φ ≦ t ₁ ≦ t + φ, where t is the input pulse width, φ is the clock period, and t ₁ is the pulse width after delay when an error occurs during one period of the clock pulse. It becomes a relationship. For example, if the pulse width error after delay is 1% or less of the input pulse width, the clock pulse period must be 1/100 or less of the delayed pulse width.

That is, in order to eliminate the error in the conventional pulse delay circuit, the clock pulse period must be sufficiently short with respect to the delayed pulse width.

Next, problems of the conventional pulse delay circuit shown in FIG. 3 will be described. In the conventional pulse delay circuit, consider a case where the delay time is longer than the pulse width, for example, the pulse width is t, the delay time is d, and d = 2t. As described above, for example, in order to make the accuracy of the pulse width after the delay 1% or less, the frequency of the clock pulse needs to be 100 times or more the pulse width, and the delay time d is twice the pulse width. DFF requires 200 steps or more. That is, even when the delay time is twice the pulse width, n = 200 in FIG. 3, and the number of DFFs is very large.

(Problems to be Solved by the Invention) As described above, in the conventional pulse delay circuit, in order to improve the pulse width accuracy after the delay, the period of the clock pulse is made sufficiently shorter than the pulse width of the delayed pulse. There is a need. However, in the conventional pulse delay circuit, when the delay time is longer than the delayed pulse width, it is necessary to make the number of DFF stages extremely large, and there is a drawback that the circuit scale becomes large.

An object of the present invention is to solve the conventional drawbacks, improve the accuracy of the pulse width after delay and the scale of the delay circuit, and provide a small-scale pulse delay circuit with good accuracy of the delay time.

(Means for Solving the Problems) The present invention has a first counter and a second counter,
The output of the first counter and the output of the second counter are connected to the input of the output flip-flop circuit, the output of the first counter is connected to the input of the first flip-flop circuit, and the second counter The output of the counter is connected to the input of the second flip-flop circuit, the pulse input terminal is connected to the input of the rising detection logic circuit and the input of the falling detection logic circuit, and the output of the rising detection logic circuit is passed through the inverter to 1st with output of 1 counter
The input of the first flip-flop circuit, the output of the first flip-flop circuit is combined with the output of the rising detection logic circuit, and the output of the falling detection logic circuit is connected to the reset input of the first counter. After that, it becomes the input of the second flip-flop circuit together with the output of the second counter, and the output of the second flip-flop circuit is combined with the output of the fall detection logic circuit.
Connected to the reset input of the second counter, and
The clock input terminals of the counter and the second counter are commonly connected.

(Operation) Unlike the conventional pulse delay circuit, the pulse delay circuit of the present invention uses two counters, and the first counter uses the rising edge of the delay pulse as the count start timing.
In the second counter, the falling edge of the delay pulse is used as the count start timing, and the rising edge and the falling edge of the delay pulse are transmitted separately by the two counters and by using the same clock, and the outputs of the two counters are output. Is subjected to logic processing by a flip-flop circuit, and further, a change in the output state of the two counters is subjected to logic processing by the flip-flop circuit, and is synthesized with the reset signal of each counter.

(Embodiment) An embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 shows a pulse delay circuit of the present invention. In the figure, 1 is a first counter, R _A is a reset input, φ _A is a clock input, Q _A is an output, 2 is a second counter, R _B is a reset input, φ _B is a clock input, Q _B Is the output. 3,
4,5,6,7,8 are NOR gates, and NOR gates 3 and 4, NOR gates 5 and 6, and NOR gates 7 and 8 each constitute a flip-flop circuit. 9 and 10 are OR gates,
Outputs the logical sum of two inputs. 11 and 12 are AND gates,
Outputs the logical product of two inputs. 13,14,15,16,17,18,19
Is an inverter that outputs the inverted logic of the input. 20 is a pulse input terminal to which a pulse before delay is input. Reference numeral 21 is an output terminal of the pulse delay circuit of the present invention, and the pulse input to the input terminal 20 is delayed and output. A clock input terminal 22 is connected to the clock input φ _A of the first counter and the clock input φ _B of the second counter.

FIG. 2 shows operation waveforms of the pulse delay circuit of the present invention.
In the figure, φ _A and φ _B are clock pulses of the first counter and the second counter in FIG. 1, and the first counter and the second counter count the number of clock pulses φ _A and φ _B , When the count value of the counter reaches the specified value, Q _A and Q _B change from the “L” state to the “H” state.

In FIG. 2, a is an input pulse, which is input to the input terminal 20 in FIG. In FIG. 2, b is the output waveform of the inverter 13 in FIG. 1, which is the inverted waveform of the input terminal 20 and is slightly delayed because of the delay of the transmission time. In FIG. 2, c is the output waveform of the AND gate 11 in FIG. 1, and the output of the AND gate 11 is the logical product of the output of the inverter 13 and the input terminal 20.

In FIG. 2, d is the output waveform of the inverter 15 in FIG. d has the same polarity as the input terminal 20 in FIG. 1 and has a waveform with a transmission time delay due to the inverters 14 and 15.

In FIG. 2, e is the output waveform of the AND gate 12 in FIG. It is also the logical product of e, b, and d.

In FIG. 2, f, g, h and i are the first counter output Q _A , the second counter output Q _B , the output of the NOR gate 6 and NOR in FIG.
The output waveforms of the gate 8 are shown.

Next, the operation of the pulse delay circuit of the present invention shown in FIG. 1 will be described. In the figure, the pulse input to the input terminal 20 is brought into the "H" state at the rising timing of the input pulse by the AND gate 11 and the inverter 13 as shown in c of FIG. "Is the first
Since it corresponds to the signal transmission time of the inverter 13 in the figure, it is sufficiently shorter than the cycle of the clock inputs φ _A and φ _B in FIG. Similarly, the AND gate 12 in FIG.
As shown by e in FIG. 2, the output of becomes the "H" state at the timing of the falling edge of the input pulse, and the period when e is "H" is compared with the cycle of the clocks φ _A and φ _B. Short enough.

In FIG. 1, when the output of the AND gate 11 becomes "H", O
The output of the R gate 9 also becomes "H", the first counter is reset, the count becomes zero, and the output Q _A becomes "L". The output of the AND gate 11 is "L" → "H" → "L" at the timing near the falling edge of the pulse input to the input terminal 20.
Therefore, the output of the inverter 17 also changes to the AND gate 11
The output changes from "L" to "H" to "L" after a delay of the transmission time of the inverter 16 and the inverter 17. Here, the operation of the flip-flop circuit formed by the NOR gates 5 and 6 will be described. The input of the NOR gate 5 is the output of the NOR gate 6 and the output Q _A of the first counter, and the input of the NOR gate 6 is the output of the NOR gate 5 and the output of the inverter 17, so the output Q _{A of} the first counter Changes to "L", and then the output of the inverter 17 changes from "L" to "H" to "L".
The output of the gate 6 becomes "L". When the first counter output Q _A is “L” and the output of the inverter 17 is “L”, the outputs of the NOR gates 5 and 6 do not change and the output of the inverter 17 is “L”.
Then, when the output Q _A of the first counter becomes “H”, the NOR gate 6
Output becomes "H". At the rising edge of the pulse input to the input terminal 20, the output of the AND gate 11 changes to "L" →
The output of the OR gate 9 is also "L" because it changes from "H" to "L"
→ “H” → “L”, the reset terminal _RA of the first counter is once reset, and then input to the clock input φ _A , the first counter starts counting by the clock. When the first counter finishes counting, the output Q _A becomes “H”, so that the output of the NOR gate 6 becomes “H”. At this time, the output of the inverter 17 is "L". That is, the first counter is reset because the output of the NOR gate 6 becomes "H" after the count is completed and the reset input _RA becomes "H", and the output Q _A becomes "L" → "H" → "L". "It becomes. NOR
Since the gates 3 and 4 form a flip-flop circuit like the NOR gates 5 and 6, the output of the NOR gate 4 is the first
As soon as the counter finishes counting, it goes to "H" and the second
This state is maintained until the signal from the counter output Q _B comes. In FIG. 2C, there are three "H" periods, and the central "H" signal shows the change at the end of counting by the first counter in FIG.

Next, the output of the AND gate 12 in FIG.
With the timing of the falling edge of the input pulse input to 0,
Since it changes from "L" to "H" to "L", the second counter is reset once at the falling edge of the input pulse and starts counting after the count reaches zero. When the second counter is reset before starting counting, the output Q _B becomes “L”, and then the output of the inverter 19 changes from “L” → “H” → “L”, so that the NOR gate The output of 8 becomes "L". When the second counter finishes counting and the output Q _B becomes “H”, the output of the NOR gate 4 becomes “L” (at this time, the output Q _A of the first counter is “L”), and the inverter Since the output of 19 is "L", the output of NOR gate 8 becomes "H", the output of OR gate 10 becomes "H", and the second
The counter is reset. Therefore, when the second counter has finished counting, the output Q _B changes the "L" → "H" → "L".

In FIG. 2, there are three periods where c is “H”, and the central “H” signal shows the change at the end of counting of the counter in FIG. Therefore, at the output terminal 21 in FIG. 1, as shown by j in FIG. 2, a delayed pulse waveform having a pulse width t equal to the input pulse input to the input terminal 20 is obtained. That is, in the pulse delay circuit of the present invention shown in FIG. 1, the first counter delays the rising timing of the input pulse, the second counter delays the falling timing of the input pulse, and the NOR gates 3, 4 Regenerates the input pulse from two counter outputs.

In the pulse width accuracy after delay of the pulse delay circuit of the present invention shown in FIG. 1, one cycle of the clock input to the clock terminals φ _A and φ _B becomes an error factor. Therefore, the output terminal
When the pulse width output to 21 is t ₀ , the input pulse width is t, and the clock cycle is t _φ , t−t _φ ≦ t ₀ ≦ t + t _φ .

Next, consider the case where the delay time of the pulse delay circuit of the present invention is long. Since the pulse delay circuit of the present invention uses a counter, a large count can be obtained even when the number of flip-flop circuits forming the counter is small. Therefore, even when the delay time is long, there is no problem that a very large number of flip-flop circuits are required unlike the conventional pulse delay circuit, and the same delay pulse width accuracy as that of the conventional pulse delay circuit can be obtained.

(Effects of the Invention) According to the present invention, even when the delay time of the pulse delay circuit is longer than the delay pulse width, a small-scale and accurate pulse delay circuit can be obtained. Is large.

[Brief description of drawings]

FIG. 1 shows a pulse delay circuit according to an embodiment of the present invention,
FIG. 3 is an operation waveform diagram of the pulse delay circuit of the present invention, FIG. 3 is a conventional pulse delay circuit, FIG. 4 is an operation waveform diagram of a delay flip-flop circuit used in the conventional pulse delay circuit, and FIG. Operation waveform diagram of conventional pulse delay circuit, 6th
The figure is a waveform diagram for explaining the problems of the conventional pulse delay circuit. 1,2 …… Counter, 3,4,5,6,7,8 …… NOR gate, 9,10…
… OR gate, 11,12 …… AND gate, 13,14,15,16,17,18,
19 …… Inverter, 20 …… Pulse input terminal, 21 …… Output terminal, 22 …… Clock input terminal.

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Hideo Hayashi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Akira Furukawa 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Claims] 1. A first counter and a second counter, wherein an output of said first counter and an output of said second counter are connected to an input of an output flip-flop circuit, and said first counter The output of the counter is connected to the input of the first flip-flop circuit, the output of the second counter is connected to the input of the second flip-flop circuit, and the pulse input terminal is connected to the input of the rising detection logic circuit. The output of the rising edge detection logic circuit is connected to the input of the falling edge detection logic circuit, and the output of the rising edge detection logic circuit becomes the input of the first flip-flop circuit together with the output of the first counter through an inverter. The output is combined with the output of the rising edge detection logic circuit and is connected to the reset input of the first counter. The output of the clock circuit becomes an input of the second flip-flop circuit together with the output of the second counter via an inverter, and the output of the second flip-flop circuit is combined with the output of the fall detection logic circuit. Above, a pulse delay circuit connected to the reset input of the second counter, and the clock input terminals of the first counter and the second counter are commonly connected.