JPH0342814B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a hexadecimal counter circuit, and in particular, a so-called synchronous type counter circuit configured to repeat and count from 1 to 12 for use in a digital clock IC. Concerning a hexadecimal counter circuit.

[Conventional technology]

FIG. 3 shows an example of this type of hexadecimal counter circuit in the prior art, in which 6, 7, 8, 9, and 10 are D flip-flops, among which flip-flops 6, 7, and 1 are D flip-flops.
0, the clock signal φ from the clock generation circuit
has a clock input terminal φ to which the clock signal φ is supplied through inverters 61 and 62, and a clock input terminal to which the clock signal φ is inverted and supplied through inverter 61. The flip-flop 8 also has clock input terminals Q ₂ , _{2 to which the output Q 2 , 2 of} the flip-flop 7 is input as a clock signal.
The flip-flop ₉ has a clock input terminal Q _{1,1 to which the output Q 1,1 of the} flip-flop 6 is inputted as _a clock signal.

Furthermore, the D flip-flop 6 has a set terminal S, a data input terminal D ₁ , and an output terminal Q ₁ , ₁ , and the D flip-flop 7 has a reset terminal R, a data input terminal D ₂ , and an output terminal Q ₂ , _2. The D flip-flop 8 has a reset terminal R, a data input terminal D ₃ , and an output terminal Q ₃ .
The flip-flop 9 has a reset terminal, a data input terminal D ₄ , and an output terminal Q ₄ , and the D flip-flop 10 has a reset terminal, a data input terminal D ₅ , and an output terminal Q ₅ .

and the data input terminal of D flip-flop 6.
The output from _{terminal 1 is} input to D1.

Also, the data input terminal of D flip-flop 7
D ₂ includes the output a of the AND gate 71 (the logical product of Q ₁ , Q ₂ ), the output b of the AND gate 72 (the logical product of ₁ , Q ₅ ), and the output c of the AND gate 73 (the logical product of ₁ , ₂ and Q ₃ ), and the signal obtained through the NOR gate ₇₄ (i.e. +++ ₄ )
is input.

Also, the data input terminal of D flip-flop 8
A signal obtained by passing Q _{5 and} Q ₃ through the NOR gate 81 is input to D 3 , and a signal obtained by passing ₃ and ₂ through the NOR gate 91 is input to the data input terminal D ₄ of the D flip-flop 9 .

Furthermore, the data input terminal of the D flip-flop 10
D ₅ contains the output i (logical product of Q ₁ and Q ₄ ) of the AND gate 101 and the output j (the logical product of Q 1 and Q 4 ) of the AND gate 102 (
₂ , Q ₅ ) to the signal obtained through the NOR gate 103 and the inverter 104 (i.e.
+j) is input.

Under such a configuration, the outputs Q ₁ , Q ₂ , Q ₃ , Q ₄ , and Q ₅ obtained from each D flip-flop are
By combining these, each time the clock signal φ is input (in this example, each time the clock signal φ that is input sequentially falls), the count number on the output side is repeated as 1, 2, 3, ...12. It turns out. In that case, if Q ₅ is high level, the 10th digit is "1"
, and the count number of 1 digits (i.e. 0 to 9) is calculated from each output of Q ₁ , Q ₂ , Q ₃ , and Q ₄ (2
(expressed in base numbers).

Next, FIG. 4 is a diagram showing a timing chart when the circuit of FIG. The reset signal is supplied to the reset terminal, and _Q1 is initially set to high level ("1"), and in other flip-flops 7 to 10, the reset signal is supplied to the reset terminal, and _Q2 to _Q5 are set to low level ("0"). ”).

After that, each D flip-flop reads the value of the input signal input to the respective data input terminal at each falling time of the clock signal φ (however, Q ₂ and Q ₁ for D flip-flops 8 and 9, respectively). , whose value is clocked by the clock signal φ
(However, for D flip-flops 8 and 9, each
Q ₂ , Q ₁ ) is held until the next falling time.

That is, first, in the D flip-flop 6, Q ₁ is changed by the reset signal as described above.
is initialized to "1", while ₁ is initialized to "0".
Therefore, on the next falling edge of the clock signal φ, the flip-flop reads the value of D ₁ or ₁ and Q ₁ is set to ``0'' while <sub>1</sub> is set to ``1''. Furthermore, at the next falling edge, the value of ₁ at that time is read and Q ₁ becomes "1", while ₁
is set to "0" and the same cycle is repeated (see Q ₁ in Figure 4).

Next, each AND gate 71, 7 in FIG.
The outputs a, b, and c of 2 and 73 are the logical product of Q ₁ and Q ₂ , the logical product of ₁ , Q ₅ , and the logical product of ₁ , ₂ , and Q _3, respectively, and are the logical product of a, b, and c in Fig. 4. The waveform will be as shown below. Furthermore, the data input D ₂ obtained from these a, b, c and Q ₄ through the NOR gate 74 is the fourth
The waveform will be shown as _D2 in the figure.

Therefore, in the D flip-flop 7,
The reset signal sets Q ₂ to “0”, while ₂
After D2 is initially set to "1", the value of D2 at that time is " ₁ " at the next falling edge of the clock signal φ.
After reading Q ₂ becomes "1" and ₂ becomes "0". Then, at the next falling edge, the value of D ₂ at that time is read, and the value of Q ₂ (and therefore ₂ ) is maintained as it is. In this case, although not shown in the figure, in order to perform the above operation, the clock signal must fall before the value of D ₂ changes from "1" to "0".

Then, at the subsequent falling edge of the clock signal, the flip-flop 7 outputs the current D ₂
Q ₂ is set to ``0'' by reading the value of . Then, at the next falling edge, the value of D ₂ at that time is read, and the value of Q ₂ is maintained as it is. Again, to perform such an operation,
The clock signal must fall before the value of _D2 changes from "0" to "1". Do the same below
The waveform of Q ₂ becomes as shown in FIG. 2 D ₂ .

Furthermore, the outputs i, j of each AND gate, each data input D ₃ , D ₄ , D ₅ and each flip-flop output
The waveforms of Q ₃ , Q ₄ , and Q ₅ are as shown in Figure 4, and as a result, the counter output composed of Q ₁ to Q ₅ is as shown in the bottom row of Figure 4. become. Note that _the clock signal input to the D flip-flop 8 is Q _2,2 , and the clock signal input to the D flip-flop 9 is
Q ₁ , ₁ .

And the output Q ₅ sets the 10th digit of the count number to "1"
The output is ``1'' when the count is 10, 11, and 12.
The digit of 1 is represented by combining Q ₁ to Q ₄ . Therefore
Q ₁ becomes "1" when the count number is odd, and Q ₂
is "1" when the count number is 2, 3, 6, 7, and 12, and Q ₃ is "1" when the count number is 4, 5, 6, 7.
When , it becomes "1", and Q ₄ has a count of 8 and 9.
It becomes "1" when . After the count reaches 12, it returns to 1 at the next falling edge of the clock.

[Problem that the invention seeks to solve]

However, in the conventional circuit described above, the delay caused by the internal gate and wiring capacitance, etc.
It affects the data and clock signal input to each D flip-flop, disrupts the timing relationship between the data and clock signal, and incorporates spike pulses that occur in the input data into the output side, resulting in some There is a problem in that the output of the D flip-flop may be set to an incorrect value when the clock signal falls.

That is, one aspect of the malfunction is shown in FIG. As mentioned earlier, in order for the above conventional circuit to operate correctly, if the value of the data input to the D flip-flop also changes at the falling edge of the clock signal input to the D flip-flop, the data value must change. The clock falls before the change occurs, and it is necessary to read the data before the change.

However, as mentioned above, the flip-flop 9 uses the output Q ₁ , ₁ of the flip-flop 6 as a clock signal, and the delay in the clock signal Q ₁ , ₁ caused by wiring capacitance etc. is quite large. The output of the NOR circuit 91 which becomes the input data D ₄ ( ₂ + ₃ =
Since the propagation speed of Q ₂ and Q ₃ ) is faster, for example, after the data D ₄ changes from "1" to "0" at the time point t _A in FIG. 5, the clock signal Q ₁
will fall, and in such a case, as shown at point A in Figure 5, the output _Q4 will not become "1" but will be set to "0", and as a result, the next count after count number 7 will be 0. This will result in a malfunction.

Furthermore, another aspect of the malfunction is shown in FIG. This malfunction is caused by the timing between the clock signal and data of the flip-flop 8. The input data _D3 of the flip-flop 8 is ( ₅ + ₃ ), but if the input data D3 of the flip-flop 8 is (5 + 3),
At the time indicated by t _B in the figure, the fall of Q ₅ and Q ₃
If a time lag occurs between the rising edge of the data _D3 , a spike pulse as shown by P in FIG. 6 will occur in the data D3.

On the other hand, the flip-flop 8 uses the outputs Q ₂ and ₂ of the flip-flop 7 as a clock signal, and the clock signal has a considerable delay caused by wiring capacitance, etc., and the above-mentioned data D ₃
Since the clock signal _Q2 falls after the spike pulse P generated at , the flip-flop 8 reads this spike pulse as shown by B in FIG. 6, and the output _Q3 is set to "1". As a result, the count number after 12 becomes 5, which again causes a malfunction.

This was done in order to solve the problems related to the present invention, and the mutual time relationship between the clock signal and the data does not go out of order under any conditions, and each flip-flop does not cause an error at the falling edge of each clock. digital clock IC.
This is designed to eliminate malfunctions that could be fatal.

[Means for solving problems]

According to the invention, the first D flip-flop 1
to a fifth D flip-flop 5, the first D flip-flop 1 has a clock input terminal,
a set terminal, a data input terminal, and an output terminal; each of the second D flip-flop 2 to fifth D flip-flop 5 has a clock input terminal, a reset terminal, a data input terminal, and an output terminal; A clock signal (CK) from a clock generation circuit is directly supplied to the clock input terminal of each of the first D flip-flop 1 to the fifth D flip-flop 5, and the data input terminal of the first D flip-flop 1 is directly supplied with a clock signal (CK) from a clock generation circuit. The inverted output of the first D flip-flop 1 is input to the input terminal, and the output of the first D flip-flop 1 and the output of the second D flip-flop 2 are input to the data input terminal of the second D flip-flop 2. the logical product of the inverted output of the first D flip-flop 1 and the output of the fifth D flip-flop 5, the inverted output of the first D flip-flop 1, and the second D flip-flop 2. and the inverted output of the third D flip-flop 3;
A signal obtained as an inverted logical sum with the output of the fourth D flip-flop 4 is input, and a signal obtained by inverting the output of the first D flip-flop 1 and the second D flip-flop 3 is input to the data input terminal of the third D flip-flop 3. the AND of the output of the D flip-flop 2 and the inverted output of the third D flip-flop 3;
The logical product of the inverted output of the first D flip-flop 1, the output of the second D flip-flop 2, and the output of the third D flip-flop 3, the inverted output of the second D flip-flop 2, and the third A signal obtained as a logical sum of the output of the first D flip-flop 1 and the output of the second D flip-flop 3 is input to the data input terminal of the fourth D flip-flop 4. As the logical sum of the logical product of the output of the D flip-flop 2 and the output of the third D flip-flop 3, and the logical product of the inverted output of the first D flip-flop 1 and the output of the fourth D flip-flop 4. The obtained signal is input to the data input terminal of the fifth D flip-flop 5, and the logical product of the output of the first D flip-flop 1 and the output of the fourth D flip-flop 4 and the second A signal obtained as the logical sum of the inverted output of the D flip-flop 2 and the output of the fifth D flip-flop 5 is input, and each of the first D flip-flop 1 to the fifth D flip-flop 5 outputs the The first D flip-flop is configured to read an input signal value input to the data input terminal at each falling time of the clock signal and hold the input signal value until the next falling time of the clock signal. 1 to the fourth D
The binary output from each output terminal of the flip-flop 4 counts the digits 1 to 9, and the binary output from the output terminal of the fifth D flip-flop 5 counts the digits of 10, which are then combined. A hexadecimal counter circuit is provided, characterized in that it is configured to repeatedly count from 1 to 12.

[Effect]

According to the above configuration, each D flip-flop is
At each falling time of the clock signal input from the clock generation circuit to the flip-flop, the value of the input signal input to each data input terminal at that time is read, and the value is stored until the next falling time of the clock signal. Hold.

In that case, all the clock signals supplied to each flip-flop are commonly directly supplied from the clock generation circuit only via an inverter as necessary, and each D
Since the value of the data input to the flip-flop is determined, it is reliably prevented that erroneous data input is set on the output side due to a delay in the fall time of the clock.

〔Example〕

Figure 1 shows one of the hexadecimal counter circuits according to the present invention.
Examples 1, 2, 3, 4, and 5
are D flip-flops, and each flip-flop has a clock input terminal C to which the clock signal CK from the clock generation circuit is supplied through inverters 11 and 12, and a clock input terminal C to which the clock signal CK from the clock generation circuit is supplied.
Each D flip-flop has a clock input terminal to which CK is inverted and supplied through an inverter 11, and the operation of each D flip-flop is defined based on this clock signal.

Furthermore, the D flip-flop 1 has a set terminal S, a data input terminal D ₁ , and an output terminal Q ₁ , ₁ , and the D flip-flop 2 has a reset terminal R, a data input terminal D ₂ , and an output terminal Q ₂ , _2. The D flip-flop 3 has a reset terminal R, a data input terminal D ₃ , and an output terminal Q ₃ , and the D flip-flop ₄ has a reset terminal R, a data input terminal D ₄ , and an output terminal Q ₄ . have, D
Flip-flop 5 has a reset terminal, a data input terminal _D5 , and an output terminal _Q5 .

and the data input terminal of D flip-flop 1.
The output from _{terminal 1 is} input to D1.

Also, the data input terminal of D flip-flop 2
D ₂ includes the output a of the AND gate 21 (the logical product of Q ₁ and Q ₂ ), the output b of the AND gate 22 (the logical product of ₁ and Q ₅ ), and the output c of the AND gate 23 (the logical product of ₁ , ₂ , and Q ₃ ), and Q ₄ as the signal obtained through the NOR gate 24 (i.e. +++ ₄ )
is input.

Also, the data input terminal of D flip-flop 3
D ₃ is the output d of the AND gate 31 (logical product of Q ₁ , Q ₂ , and ₃ ), and the output e of the AND gate 32 (
₁ , Q ₂ , and Q ₃ ) and the output f of AND gate 33 (logical product of ₂ and Q ₃ ) through NOR gate 34 and inverter 35 (ie, d+e+f) are input.

Also, the data input terminal of D flip-flop 4
D ₄ receives the output g (logical product of Q ₁ , Q ₂ , and Q ₃ ) of AND gate 41 and the output h (logical product of ₁ , Q ₄ ) of AND gate 42 through NOR gate 43 and inverter 44 . The signal (i.e., g+h) is input.

Furthermore, the data input terminal of D flip-flop 5
D ₅ contains the output i (logical product of Q ₁ , Q ₄ ) of the AND gate 51, and the output j ( ₂ , Q ₅ ) of the AND gate 52.
(logical product) of NOR gate 53 and inverter 5
4 (ie, i+j) is input.

The hexadecimal counter circuit according to the present invention has the above-described configuration, and by combining the outputs Q ₁ , Q ₂ , Q ₃ , Q ₄ , and Q ₅ obtained from each D flip-flop, the clock signal CK is input. (in this example, the clock signal that is input sequentially)
1, 2, 3...12 will be repeated as the count number on the output side every time CK falls). In that case, if Q ₅ is at a high level, it indicates that the 10s digit is "1", and each number of 1s digits (i.e. 0
-9) are obtained by combining the outputs of Q ₁ , Q ₂ , Q ₃ , and Q ₄ (expressed in binary numbers),
In this respect, it is similar to the conventional example described above.

Next, FIG. 2 is a timing chart showing the operation of the circuit shown in FIG. _Q1 is initially set to high level (“1”), and the other D flip-flops 2 to 5
In this case, the reset signal is supplied to the reset terminal, and Q2 to _Q5 are initialized to low level ₍ "0").

Thereafter, each D flip-flop reads the value of the input signal input to each data input terminal at each falling time of the clock signal CK, and holds that value until the next falling time of the clock signal CK. do.

That is, first, in the D flip-flop 1, Q ₁ is set by the reset signal R as described above.
is initialized to "1", while ₁ is initialized to "0".
Therefore, on the next falling edge of the clock signal CK, the flip-flop reads the value of _D1 , ie, ₁ , and _Q1 is assumed to be ``0'', while <sub>1</sub> is assumed to be ``1''. Furthermore, at the next falling edge, read the value of ₁ at that time and _change Q ₁ to "1".
is set to "0", and the same cycle is repeated thereafter. (See Q ₁ in Figure 2).

Next, each AND gate 21, 2 in FIG.
The outputs a, b, and c of 2 and 23 are the logical product of Q ₁ and Q ₂ , the logical product of ₁ , Q ₅ , and the logical product of ₁ , ₂ , and Q ₃ , respectively, and are the logical product of a, b, and The waveform is shown as c. Furthermore, the data input D ₂ obtained from these a, b, c and Q ₄ through the NOR gate 24 has a waveform shown by D ₂ in FIG.

Therefore, in D flip-flop 2,
The reset signal sets Q ₂ to “0”, while ₂
is initialized to “1”, the clock signal CK
At the next falling edge of , the value of D ₂ at that time is "1"
After reading Q ₂ becomes "1" and ₂ becomes "0". Then, at the next falling edge, the value of D ₂ at that time is read, and the value of Q ₂ (and therefore ₂ ) is maintained as it is. In this case the second
In the figure, the fall of the clock signal CK and the change of the value of _D2 from "1" to "0" are shown to be simultaneous, but in reality, the clock signal CK changes from "1" to "0" at the same time. Since each data value is determined, there is a slight time lag between them, and the value of _D2 is always "1" at the falling edge of the clock signal.
, so Q ₂ will not be set to "0" by mistake.

Then, at the subsequent falling edge of the clock signal, the flip-flop 2 at that time
Q ₂ is set to “0” by reading the value of D ₂ .
At this time, if a spike pulse P as shown in D ₂ (such a pulse is delayed from the time when a changes from "1" to "0" in FIG. 2, and c changes from "0" to "0" in FIG. 2), 1) occurs, the spike pulse P generated at the falling edge of the clock signal occurs with a slight delay in time after the falling edge of the clock signal, as described above. Incorporating
Q ₂ is never set to ``1'' by mistake. Then, at the next falling edge, the value of D ₂ at that time is read, and the value of Q ₂ is maintained as it is. In this case as well, to be more precise, D ₂ changes from "0" to "1" with a slight delay after the fall of the clock signal, so Q ₂ will not be set to "1" by mistake. Similarly, the waveform of Q ₂ becomes as shown in Q ₂ in FIG. 2.

Furthermore, the outputs of each AND gate d, e, f, g,
The waveforms of h, i, j, each data input D ₃ , D ₄ , D ₅ and each flip-flop output Q ₃ , Q ₄ , Q ₅ are as shown in FIG. The count output consisting of ₁ to _Q5 is as shown in the bottom row of FIG.

In other words, output Q ₅ converts the 10th digit of the count number to "1"
It is set to 1 when the count number is 10, 11, and 12, and the output Q ₁
The combination of _Q4 represents the digit of 1. Therefore Q ₁
is "1" when the count number is odd, Q ₂ is "1" when the count number is 2, 3, 6, 7, and 12, and Q ₃ is "1" when the count number is 4, 5, 6, 7.
When , it becomes "1", and Q ₄ has a count of 8 and 9.
It becomes "1" when . After the count reaches 12, it returns to 1.

In the counter circuit of the present invention, each D
The clock signal CK supplied to flip-flops 1 to 5 is all supplied directly from the clock generation circuit via an inverter as necessary, which is a so-called synchronous system, and the clock signal is input to each D flip-flop based on the clock signal. Since the value of the input data is determined, the timing when setting the output of the D flip-flop may be out of order, or the input data may be incorrect, based on the clock signal delayed by internal gates and wiring capacitances, etc., as in the conventional example above. This system reliably prevents the output of each D flip-flop from being set to an incorrect value by incorporating spike pulses generated in the output side into the output side.
It is possible to realize a decimal counter circuit for a digital watch (that is, a circuit that counts from 1 to 12 and repeats counting from 1) without fear of malfunction.

〔Effect of the invention〕

According to the present invention, the mutual time relationship between the clock signal and the input data will not be distorted under any conditions, and each D flip-flop will not receive erroneous data (spike pulses) at each falling time of the clock signal. Therefore, a decimal counter circuit suitable for use in a digital clock is obtained, which is free from the risk of malfunction due to reading (including).

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a hexadecimal counter circuit as an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the circuit in FIG. 1, and FIG. FIG. 4 is a diagram showing a conventional example of a hexadecimal counter circuit, and FIG. 4 is a diagram showing a timing chart when the circuit in FIG.
FIG. 6 and FIG. 6 are diagrams each showing a timing chart when the circuit of FIG. 3 malfunctions. (Explanation of symbols), 1, 2, 3, 4, 5...D flip-flop, 21, 22, 23, 31, 3
2, 33, 41, 42, 51, 52...And Gate, 24, 34, 43, 53...Noah Gate,
11, 12, 35, 44, 54...inverter,
6, 7, 8, 9, 10...D flip-flop,
71, 72, 73, 101, 102... AND gate, 74, 81, 91, 103... Noah gate, 61, 62, 104... Inverter.

Claims (1)

[Claims] 1. A first D flip-flop 1 to a fifth D flip-flop 5 are provided, the first D flip-flop 1 having a clock input terminal, a set terminal, a data input terminal, and an output terminal; Each of the second D flip-flop 2 to fifth D flip-flop 5 has a clock input terminal, a reset terminal, a data input terminal, and an output terminal, and each of the first D flip-flop 1 to fifth D flip-flop 5 has a clock input terminal, a reset terminal, a data input terminal, and an output terminal. The clock signal (CK) from the clock generation circuit is directly supplied to each clock input terminal of the first D flip-flop 1, and the inverted output of the first D flip-flop 1 is input to the data input terminal of the first D flip-flop 1. The data input terminal of the second D flip-flop 2 is supplied with the AND of the output of the first D flip-flop 1 and the output of the second D flip-flop 2, and the inverse of the first D flip-flop 1. The logical product of the output and the output of the fifth D flip-flop 5, the inverted output of the first D flip-flop 1, the inverted output of the second D flip-flop 2, and the output of the third D flip-flop 3. logical product and
A signal obtained as an inverted logical sum with the output of the fourth D flip-flop 4 is input, and a signal obtained by inverting the output of the first D flip-flop 1 and the second D flip-flop 3 is input to the data input terminal of the third D flip-flop 3. the AND of the output of the D flip-flop 2 and the inverted output of the third D flip-flop 3;
The logical product of the inverted output of the first D flip-flop 1, the output of the second D flip-flop 2, and the output of the third D flip-flop 3, the inverted output of the second D flip-flop 2, and the third A signal obtained as a logical sum of the output of the first D flip-flop 1 and the output of the second D flip-flop 3 is input to the data input terminal of the fourth D flip-flop 4. As the logical sum of the logical product of the output of the D flip-flop 2 and the output of the third D flip-flop 3, and the logical product of the inverted output of the first D flip-flop 1 and the output of the fourth D flip-flop 4. The obtained signal is input to the data input terminal of the fifth D flip-flop 5, and the logical product of the output of the first D flip-flop 1 and the output of the fourth D flip-flop 4 and the second A signal obtained as the logical sum of the inverted output of the D flip-flop 2 and the output of the fifth D flip-flop 5 is input, and each of the first D flip-flop 1 to the fifth D flip-flop 5 outputs the The first D flip-flop is configured to read an input signal value input to the data input terminal at each falling time of the clock signal and hold the input signal value until the next falling time of the clock signal. 1 to the fourth D
The binary output from each output terminal of the flip-flop 4 counts the digits 1 to 9, and the binary output from the output terminal of the fifth D flip-flop 5 counts the digits of 10, which are then combined. A hexadecimal counter circuit characterized in that it is configured to repeatedly count numbers from 1 to 12.