JPH07111866B2 - Solid-state electron beam generator - Google Patents

Description

The present invention relates to a solid-state electron beam generator.

[Prior Art] One of the conventionally known solid-state electron beam generators is, for example, the device disclosed in US Pat. No. 4,259,678. The device disclosed in this US patent forms a pn junction on a Si semiconductor substrate and applies a reverse voltage to the pn junction.
The avalanche effect produces electrons with higher energy than the thermal equilibrium state (hereinafter referred to as hot electrons), and the kinetic energy of hot electrons is used to extract an electron beam into a vacuum.

However, in such a device, there is a problem that the amount of current taken out is small because the proportion of hot electrons generated by the avalanche effect that has energy higher than the vacuum level is small.

A second solid-state electron beam generator known in the prior art, as disclosed in Japanese Patent Publication No. 54-30274, has
p consisting of Al _x Ga _(1-x) P (0 ≦ x ≦ 1) on aP semiconductor substrate
An n-junction region is provided, and a forward voltage is applied to the pn-junction region to take out the electrons injected from the n-region to the p-region.

However, such a device has an advantage that the amount of carriers can be increased as compared with the case of the above-mentioned US patent, but on the other hand, since there is no region for forming hot electrons, electron emission into a vacuum is performed. Low efficiency, and
The GaP substrate has the defect that it has many crystal defects and cannot form a good pn junction region.

Further, US Pat. No. 3,119,947, which is known prior to the above-mentioned two prior arts, discloses a device in which an npn region is formed on a Si semiconductor substrate and a voltage is applied between both n-type regions to emit electrons. Is proposed. According to such an npn type device, the emission efficiency of the device described as the first prior art (device utilizing pn junction) is about 10 ^-6 , whereas the emission efficiency is improved to about 10 ^-4 . It is possible.

However, the p-type region and the n-type region on the electron emission surface side need to be as thin as 100Å and be evenly provided.
There was a problem that its fabrication was difficult and not realistic.

[Problems to be Solved by the Invention] Therefore, in view of the above points, an object of the present invention is to provide a solid-state electron beam generator which facilitates a manufacturing process with a simple structure and sufficiently enhances electron emission efficiency. To do.

[Means for Solving the Problems] In order to achieve such an object, in the present invention, an emitter region having a first band gap and a base region having a second band gap narrower than the first band gap are provided. And a heterobipolar semiconductor consisting of a collector region having an electron emission surface are formed on the GaAs epitaxial film provided on the Si substrate, the mixed crystal ratio of the predetermined material gradually changes in the thickness direction. An inclined layer is inserted between the emitter region and the base region, electrons are injected from the emitter region to the base region, and a reverse bias voltage is applied between the base region and the collector region. The electrons are emitted from the electron emission surface.

[Operation] By growing an AlGaAs-based film on a Si substrate, electrons are injected from the emitter region having a wide bandgap to the base region having a narrow bandgap through the graded layer, and further generated in the collector region. The electrons are accelerated to give sufficiently large kinetic energy to the electrons, and the electrons are emitted from the end face of the collector region. Since the Si substrate has low thermal resistance, an electron beam generator with high current density can be realized. Further, it becomes easy to connect the Si integrated circuit and the electron beam generator.

[Examples] Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 is a sectional configuration diagram showing an embodiment of the present invention.

In this embodiment, MOCVD (Metalorganic Chromium) is formed on the Si substrate 1.
and the AlP layer 2 and
The AlGaP layer 3 is grown, and then the GaP and GaAsP superlattice layers 4, G
A superlattice layer 5 of aAsP and GaAs is provided, and a GaAs layer 6 is grown on it. Further, on the GaAs layer 6, an n ⁺ type GaAs layer 7, N type Al _x Ga
_(1-x) As layer 8 (0 <x ≦ 1) is grown. This N type Al _x
Except for the electron beam generating portion of the Ga _(1-x) As layer 8, oxygen is implanted by an ion implantation device to form an inactive layer 9.

On the N-type Al _x Ga _(1-x) As layer 8, the mixed crystal ratio x of Al is gradually decreased and the gradient (gradient) is continuously changed to GaAs.
ed) forming layer 20. Furthermore, on the gradient layer 20, p
A type GaAs layer 10 and an n type GaAs layer 11 are provided. Also, this n
A work function lowering material (for example, cesium oxide (Cs-O)) 12 is diffused or attached to the surface of the type GaAs layer 11.

The configuration described above will be described in more detail below.

Reference numeral 8 is an N-type Al _x Ga _(1-x) As layer which acts as an emitter. Here, x represents a mixed crystal ratio of Al, and has a value of 0 <x ≦ 1. Moreover, capital “N” represents an N-type region having a wide band gap. 9 is this N-type Al _x Ga _(1-x)
It is an inactive layer formed by implanting oxygen into the As layer.

10 is a p-type GaAs layer which acts as a base. Here, the lower case "p" represents a p-type region having a narrow band gap. It is also possible to control the size of the band gap by adding Al instead of the p-type GaAs layer to form a p-type Al _z Ga _(1-z) As layer (0 ≦ z <x). is there.

Reference numeral 11 is an n-type GaAs layer which acts as a collector. Here, the lower case "n" represents an n-type region having a narrow bandgap, like "p" described above. Note that n-type
N-type Al _t Ga _(1-t) As layer (0 ≦ t ≦ 1) instead of GaAs layer
It is also possible to use.

Further, 12 is a Cs-O layer adhered to or diffused on the surface of the collector layer 11, and acts as an electron emission surface. This Cs
-In place of the O layer, an alkali metal such as Cs and Cu, Ag, Au, S
It is also possible to attach or diffuse a material containing at least one of b, Bi, Se, As, P, Te, Si and O.

Reference numeral 13 is an emitter electrode, 14 is a base electrode, and 15 is a collector electrode.

Au-Ge, Au-Ge-Ni, etc. are used as electrodes for n-type and N-type semiconductors, and Au-Sn, Ag-Zn, Au-Be, A are used as electrodes for p-type semiconductors.
u-Zn or the like may be used. Although the p-type GaAs electrode is formed directly on the p-type GaAs surface in FIG. 1, the electrode may be formed after the Be ⁺ ions are doped under the electrode formation portion to form the p ⁺ -type region. Alternatively, p ⁺ type on the p-type GaAs surface
It is also possible to grow a GaAs layer and form an electrode thereon.

As described above, in the first embodiment of the present invention, Ga is formed on the Si substrate.
An Npn type epitaxial layer of As-Al _x Ga _(1-x) As system is grown.

Next, the operating principle of this embodiment will be described with reference to the energy band diagram shown in FIG.

In Fig. 2, the solid line is the energy level [eV] during thermal equilibrium, and the dotted line is the energy level [eV] during bias application.
V] is shown. The emitter layer 8 is made of a wide bandgap material, Al, in order to increase carrier injection efficiency into the base.
_x Ga _(1-x) As is used. In this embodiment, the mixed crystal ratio of Al x
Makes it possible to obtain a good heterojunction and
Although X = 0.3 was set in consideration of the influences of −band and X-band, the value is not limited to this value.

Furthermore, the doping amount of the emitter layer 8 is high (5 × 10 ¹⁷
~ 1 × 10 ¹⁹ cm ^-3 ), as many carriers as the base layer 10
To be injected into. With such a doping amount, a degenerate state occurs, and the Fermi level is located above the conduction band.

Since the graded layer 4 is inserted between the emitter layer 8 and the base layer 10, the mixed crystal ratio x of Al gradually decreases,
At the boundary with 10, x = 0. By inserting such a graded layer 20, spikes or the like do not occur at the hetero interface between the emitter layer 8 and the base layer 10, as shown in FIG. In this way, there are no spikes or other barriers,
Many carriers are injected into the base layer 10, and the injection efficiency is improved.

As the base layer 10, a p-type which is a narrow band gap material
A GaAs layer is used. The doping amount of the base layer 10 is 5 × 10 ¹⁸ cm ^-3 to reduce the resistance, and the thickness of the base layer is 300 Å to reduce scattering in the base region.

An n-type GaAs collector layer 11 is grown on the p-type GaAs base layer 10. The surface of the n-type GaAs collector layer 11 has Cs-O1
Since 2 is diffused (or adhered), the work function of the collector layer surface is as low as 1.4 eV. As described above, a material containing {alkali metal such as Cs + (Sb, Bi, Se, As, P, Te, Cu, Ag, Au, Si, O)} is also used for this surface layer. be able to.

The amount of doping into the collector layer 11 is set to be highly doped (1 × 10 ¹⁸ / cm ⁻³ ) so that the contact with the collector electrode 15 becomes ohmic and the resistance becomes low. In this embodiment, the collector layer 11
Although the film thickness of was set to 1000Å, it is not limited to this value. That is, if the ohmic contact with the collector electrode 15 is favorably performed, it is desirable that the collector layer 11 be thinner. Each of these layers is an MBE device or M
A good quality and uniform film is formed by growing using an OCVD device or the like.

Next, description will be given when the bias is applied (see the broken line in FIG. 2). When a forward bias voltage is applied between the emitter and the base, a reverse bias voltage is applied between the base and the collector, and a positive bias is applied to the collector for the external accelerating electrode (not shown), the emitter to the base is applied. The carriers (electrons) injected into are accelerated by the electric field between the base and collector, and are emitted from the surface where Cs-O or the like is diffused or adhered. The emitted or attached electrons are generated by an external electric field formed by an external acceleration electrode (not shown),
Gain more kinetic energy.

In this embodiment, since the graded layer is provided between the emitter layer and the base layer, a barrier such as a spike does not occur between the two layers. Therefore, the amount of carriers injected from the emitter layer to the base layer increases, the number of carriers accelerated by the reverse bias between the base and collector also increases, and the electron emission efficiency improves.

FIG. 3 is a sectional configuration diagram showing a second embodiment using a Si substrate. In the second embodiment, an element similar to that of the first embodiment shown in FIG. 1 is manufactured by the ion implantation technique.

In FIG. 3, 30 is a Si substrate, 32 is an AlP layer, and 34 is AlGaP.
Reference numeral 36 is a layer of GaP and GaAsP, 38 is a layer of GaAsP and GaAs, and 40 is a GaAs layer. The layer structure of each of these layers is
The layer structure is the same as that of the first embodiment shown in FIG.

Further, 42 is an n ⁺ type GaAs layer for obtaining ohmic contact with the emitter electrode 44, and 46 is N type Al _x Ga _(1-x) As (0 <x ≦
1) As the emitter layer, 48 is separated from the emitter layer 46,
Gradient layer with gradually decreasing Al mixed crystal ratio, 50 p-type GaAs base layer, 52 n-type GaAs collector layer, 54 collector electrode
An n ⁺ type GaAs layer for obtaining ohmic contact with 56, and 58 is a layer obtained by diffusing (or adhering) Cs-O or the like in order to lower the work function. Reference numeral 66 is a base electrode, and 62 is an external acceleration electrode.

After the n ⁺ -type GaAs layer 54 is formed, a p ⁺ -type region 64 in which Be is ion-implanted in the p-type GaAs (base) electrode formation region, and a region in which B is ion-implanted for insulation between the base-emitter and element isolation Forming 68. Further, a SiO ₂ protective layer 60 is formed and a collector electrode 56 and a base electrode 66 are produced. Regarding the emitter electrode 44, a hole is dug until it reaches the n ⁺ type GaAs layer 42, and an electrode of Au-Ge / Au or the like is formed therein.

Finally, Cs-O is diffused (or attached) to form the layer 58, and the fabrication of this example is completed. Unlike the first embodiment described above, the second embodiment has a p-type GaAs base layer.
Not only does a difficult process such as etching up to 10 (see FIG. 1) become unnecessary, but it has the advantage that the device surface becomes flat.

The operation principle and the like of the second embodiment are the same as those of the first embodiment, and therefore the description thereof is omitted.

In this way, by adopting the planar type device configuration, it is possible to appropriately deal with so-called multi-processing in which a plurality of devices are arranged on the same plane.

Although the first and second embodiments described above use the buffer layer using the superlattice layer, the ultrathin buffer layer grown at low temperature on the Si substrate is used. (GaAs / GaAs buffer layer (<200Å)
/ Si type).

[Effects of the Invention] As described in detail above, according to the present invention, the effects listed below can be obtained.

Since the band gap between the emitter and the base is different (Npn structure) and the graded layer is inserted between the emitter and the base, the amount of carriers injected from the emitter to the base increases.

Furthermore, the carriers injected into the base are accelerated by the electric field, so that the kinetic energy can be increased.

As a result, the electron emission efficiency is significantly improved.

Since the emitter region and the base region can be formed as an epitaxial film of about several tens of liters using an MBE device or a MOCVD device, a high quality and uniform layer structure can be easily formed.

Moreover, since the thickness of each layer can be reduced, the driving voltage can be reduced.

Since heat resistance and low Si can be used as the substrate, the problem of heat generation can be reduced.

Since an electron beam generator (device) can be manufactured using a Si substrate, it is easy to arrange a plurality of electron beam generators on the same substrate and to combine them with devices having other functions. . As a result, it is possible to increase the degree of integration of semiconductor devices.

Further, according to the embodiments of the present invention, the following effects can be obtained in addition to the effects of the above invention.

When the present invention is implemented using the ion implantation technique,
It is possible to increase the degree of integration by eliminating processes such as etching, flattening the surface of the device, and forming other devices on the same substrate.

[Brief description of drawings]

FIG. 1 is a sectional configuration diagram showing a first embodiment of the present invention, FIG. 2 is an energy band diagram showing an energy state of the first embodiment, and FIG. 3 is a sectional configuration showing a second embodiment of the present invention. It is a figure. 1 ... Si substrate, 2 ... AlP layer, 3 ... AlGaP layer, 4 ... GaP / GaAsP superlattice, 5 ... GaAsP / GaAs superlattice, 6 ... GaAs layer, 7 ... n ⁺ type GaAs layer , 8 ... N-type Al _x Ga _(1-x) As layer (emitter), 9 ... N-type Al _x Ga _(1-x) As oxygen injection inactive layer, 10 ... p-type GaAs layer (base) , 11 n-type GaAs (collector), 12 Cs-O diffusion layer, 20 graded layer.

Claims (5)

[Claims] 1. A heterobipolar semiconductor comprising an emitter region having a first bandgap, a base region having a second bandgap narrower than the first bandgap, and a collector region having an electron emission surface, Si
When forming on the GaAs epitaxial film provided on the substrate, insert a gradient layer in which the mixed crystal ratio of the predetermined material is gradually changing in the thickness direction, between the emitter region and the base region, Electrons are injected from the emitter region to the base region, and a reverse bias voltage is applied between the base region and the collector region to emit the electrons from the electron emission surface. Solid-state electron beam generator. 2. An N-type Al _x Ga.sub. _(1-x) As layer (where 0 <x ≦ 1) having a first bandgap is formed on a Si substrate to form the emitter region, and A p-type Al _z Ga _(1-z) As layer (where 0 ≦ z <x) having a band gap is formed as the base region, and an n-type Al _t Ga _(1-t) As layer (here, , 0 ≦ t ≦ 1) is set as the collector region. The solid-state electron beam generator according to claim 1, wherein 3. A solid-state electron beam generator according to claim 1, wherein a material having an alkali metal component is diffused or adhered to the electron emission surface of the collector region. 4. The solid-state electron according to claim 2, wherein a layer in which the mixed crystal ratio x of the Al _x Ga _(1-x) As layer is gradually changed is used as the gradient layer. Beam generator. 5. The solid state electron beam according to claim 2, wherein oxygen is injected into a predetermined region of the N-type Al _x Ga _(1-x) As layer to form an inactive region. Generator.