JPH0711650B2 - Optical D flip-flop circuit - Google Patents

Description

The present invention relates to an optical digital logic circuit used in an optical communication system, an optical information processing system, an optical switching system, an optical computer, and the like.

<Prior Art> With the recent development of optical fiber technology and optical semiconductor technology, a long-distance optical communication system for the purpose of backbone transmission and an optical LAN system for highly efficiently connecting distributed processing devices have been put to practical use. In these systems, optical technology is mainly used as a connecting means between functional devices, and the function is exclusively for LSI.
It is largely owed to the electronic circuit technology centered on.

Reflecting the arrival of the advanced information society in the near future, as the diversification of information to be processed and the increase in capacity further increase the processing speed and the processing complexity. To meet these demands, it is necessary to use optical technology not only as a connecting means but also as a logic processing means. That is, the transmitted optical digital signal can be digitally processed as it is, and the processing result can be output as light to be transmitted to another device.
Optical processing devices (optical information processing systems, optical switching systems, etc.) that make full use of characteristics such as broadband characteristics and non-inductive characteristics are essential. To realize this type of device, an optical logic functional block similar to that used in a general electric logic circuit, for example,
Optical gates (INVERTOR, OR, AND, EXOR, etc.), optical flip-flop circuits, optical shift register circuits, optical counters, etc. must be constructed.

Conventionally, none of these optical logic function blocks has been practically used.

<Object of the Invention> In view of the above, the present invention is to provide a practical optical D flip-flop circuit.

<Structure of the Invention> In order to achieve the above object, the present invention provides the first, second, and third optical bistable elements, and a combined output of optical digital data and an optical clock pulse as the first output. Of the optical bi-stable element, a first splitter for splitting the optical output signal from the first optical bistable element into two, and one of the two split by this splitter. A second multiplexer for supplying a combined output of an optical output signal and an inverted optical clock pulse of the optical clock pulse to the second optical bistable element, and another one divided by the first branching device. A third multiplexer for supplying a combined output of the optical output signal of the second optical bistable element and the optical output signal from the second optical bistable element to the third optical bistable element, The bistable element sets the optical digital data at the rising edge of the optical clock pulse, and the second optical bistable element Sets the optical digital data at the rising edge of the inverted optical clock pulse, and the third optical bistable element outputs an optical output obtained by subjecting the optical output signal from the third multiplexer to peak value shaping. It was done like this.

Further, in order to achieve the above-mentioned object, the present invention provides a first optical bistable element having a current clock terminal and a first optical bistable element.
A second optical bistable element having a branching device for dividing the optical output from the optical bistable element into two and an inverting current clock terminal, and receiving one optical output signal from the branching device; A multiplexer that multiplexes and outputs the other optical output signal from the branching device and the optical output from the second optical bistable element;
A third optical bistable element to which an optical output from the multiplexer is input, wherein the first optical bistable element is provided with the first optical bistable element at the rising edge of the current clock applied to the current clock terminal. The optical digital data applied to the bistable element is set, and the second optical bistable element sets the optical digital data at the rising edge of the inversion current clock applied to the inversion current clock terminal, and the third optical bistable element is set. The optical bistable element is adapted to output an optical output obtained by subjecting the optical output from the multiplexer to peak value shaping.

<Example> Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is an optical D flip-flop circuit diagram showing an embodiment of the present invention, and FIG. 3 is a time chart showing its logical operation. Referring to both figures, the optical clock L _C is a multiplexer having an optical digital data L _D and the amplitude intensity A _C having an amplitude intensity A _D
The signals are combined at 13 and input to the optical bistable element 10. In the optical bistable element 10, as shown in FIG. 5, the optical output Pout is the optical input Pi.
A history is shown for changes in n, and a range of input strength (P
Range) of P _C from _A, in which take two stable output light intensity. Here, the characteristics of the optical bistable element 10 will be described in more detail with reference to FIG.

As the optical input Pin increases, it gradually increases with OAB, the optical output Pout maintains a low value P _L , and when the optical input Pin reaches P _B , the optical output Pou
The value of t rapidly increases from B to C, becomes a high value P _H , and then gradually increases to CD. Conversely, when going subtracting the light input Pin is gradually decreases DCE and output, the light input Pin is to P _E, the light output Pout retains a high value P _H, when the light input Pin becomes P _A light Output Pout is E
It decreases sharply to A, becomes a low value P _L , and then gradually decreases to AO.

As an example of an element exhibiting such optical bistable characteristics,
The optical bistable semiconductor laser shown in the figure has been announced (Odagiri, et al .: DC-PBH optical bistable semiconductor laser with tandem electrode structure, National Institute of Electronics and Communication Engineers, NO.937 (1983)).

The optical bistable semiconductor laser has a Fabry-Perot cavity surface 3
It has P-division P-side electrodes 31, 32 electrically insulated by a slit 33 provided in parallel with 7, 38. Each electrode 3
By appropriately biasing currents I ₁ and I ₂ to ₁ , 32, the relationship between the optical input Pin and the optical output Pout can have a bistable characteristic as shown in FIG. Now, returning to FIGS. 1 and 3, the logical operation of the present invention will be described.

And an amplitude intensity A _C of the amplitude intensity of light digital data L _D A _D and optical clock L _C is the following relationship is set to satisfy.

Here, P _B , P _C and P _E are optical inputs at the points B, C and E of the optical bistable characteristic of FIG.

That is, the expression (1) means the following.

In a state where the light output L ₁₀ of the optical bistable device 10 holds a low value P _L ( "0" state), the input optical digital data L _D and optical clock L _C and at the same time a high value ( "1" state ), The optical output L ₁₀ can take a high value P _H (“1” state),
When both inputs do not match, it keeps a low value P _L (“0” state).

On the other hand, in a state in which the light output L ₁₀ of the optical bistable device 10 holds a high value P _H ( "1" state), either the input or whether the input optical digital data L _D or optical clock L _C is Even if it takes a low value (“0” state), the optical bistable element 10 keeps a high value (“1” state), and both inputs simultaneously have a low value (“0” state).
State) takes a low value P _L (“0” state). These relationships are shown in the truth table of FIG.

Therefore, as shown in FIG. 3, the input optical digital data L _D is set in the optical bistable device 10 in FIG. ₁ at the time of rising of the optical clock L _C at Cr ₁ , Cr ₂ ,. At the fall of digital data, the optical output L ₁₀ reset by D ₁ , D ₂ , ... Is obtained. However, the pulse width of the input optical digital data L _D is not faithfully reproduced in the optical output L ₁₀ . Therefore,
It is necessary to further process the optical output L _{10 according} to the following logic.

Referring to FIG. 1, the optical output L ₁₀ is equally divided into an optical output L ₁₀₁ and an optical output L ₁₀₀ by the branching device 14. Due to the subsequent logical operation, the amplitude intensities of the optical output L ₁₀₁ and the optical output L ₁₀₀ must satisfy the amplitude intensity A _D shown in equation (1). In order to meet this condition, the optical output L of the optical bistable element 10
High value P _H of ₁₀ is set.

Reversed polarity of optical output L ₁₀₁ and optical clock L _C , inverted optical clock of amplitude strength A _C And are multiplexed by a multiplexer 15 and input to the optical bistable element 11. The characteristics of the optical bistable element 11 are exactly the same as those of the optical bistable element 10.

Therefore, as shown in FIG. Optical output L ₁₀ is set, inverted optical clock At the fall of The optical output L ₁₁ reset by is obtained. Then the light output L
₁₀₀ and the optical output L ₁₁ are combined by the multiplexer 16, and the optical output L ₁₆ is obtained. At the optical output L ₁₆ , as shown in FIG. 3, the sum signal of the optical output L ₁₀₀ and the optical output L ₁₁ is obtained,
Its amplitude is not at the logical level. So the optical output
L ₁₆ is input to the optical bistable element 12 to perform amplitude shaping.

The characteristics of the optical bistable element 12 are as follows.
Unlike FIG. 11, as shown in FIG. 6, when the optical input Pin exceeds the threshold Pth, the optical output Pout has a comparator characteristic in which it rapidly increases from a low value P _L to a high value P _H. To obtain this characteristic, the currents I ₁ and I ₂ of the optical bistable semiconductor laser shown in FIG. 4 may be set to appropriate values.

As shown in the waveform of the optical output L ₁₆ of the multiplexer 16 in FIG.
The threshold Pth value is larger than the low value P _L , and the significant minimum output A _S
If it is set to be smaller, the output optical digital data L _O having the amplitude intensity P _H can be obtained.

After all, the output optical digital data L _O can obtain a waveform in which the input optical digital data L _D is latched in synchronization with the rising times Cr ₁ , Cr _2, ... Of the optical clock L _C. Therefore, it can be seen that the circuit of FIG. 1 operates as an optical D flip-flop circuit. Optical bistable device 1 in the first embodiment described above
The bistable semiconductor lasers shown in FIG. 4 are taken as examples 0, 11, and 12, but the invention is not limited to this, and the optical output is binary stable with respect to the optical input, and exhibits the hysteresis characteristic. It is obvious that the optical D flip-flop according to the present invention can be realized as long as it is a device.

A second embodiment of the present invention is shown in FIG.

The optical bistable elements 10 and 11 in this embodiment are different from those in the first embodiment in that they are specified to the bistable semiconductor laser shown in FIG. .

That is, the current clock I _C or the inverted current clock is applied to the electrode 31 of the bistable semiconductor laser of FIG. Is applied, the same operation of the optical D flip-flop as in the first embodiment is performed.

In order to guarantee the same operation as in the first embodiment, the amplitude value of the current clock I _C to the optical bistable semiconductor laser and the amplitude intensity A _{D of the} input optical digital data L _D are similar to those in the first embodiment. It is necessary to add various conditions.

FIG. 7 schematically shows the conditions for the amplitude intensity A _D of the input optical digital data L _D and the amplitude value of the current clock I _C.

The upper right of FIG. 7 shows the injection current of the optical bistable semiconductor laser of FIG.
The relationship between I ₁ and the optical output Pout is shown. When the injection current I ₁ increases and is below the threshold value Ith ₂ , the optical output Pout holds a low value P _L. Once the threshold Ith ₂ is exceeded, the optical output Pout
Rapidly increases to a high value P _H , and the optical output is increased even if the injection current I ₁ is increased.
Pout holds the high value P _H as it is. When the injection current I ₁ decreases and becomes less than or equal to the threshold value Ith ₁ , the optical output Pout sharply decreases from the high value P _H to the low value P _L. Injection current I ₁ optical output Pout to the injection current of optical bistable laser diode having such a characteristic
I ₁ is a value slightly smaller than threshold Ith ₁ Ib ₁ and threshold Ith ₁ and threshold Ith
When set to the middle value Ib ₂ and _2, it is possible to obtain the Figure 7 the upper left of the relation to the optical bistable laser diode of the optical input Pin and the optical output Pout.

A bistable characteristic 100 is obtained when I ₁ = Ib ₂ , and a bistable characteristic 101 is obtained when I ₁ = Ib ₁ . In the stability characteristic 100, when the optical input Pin increases and exceeds the threshold Pth ₁ , the optical output Pout
Becomes a high value P _H, the light input Pin decreases, even without input,
Holds a high value P _H. On the other hand, with the bistable characteristic 101,
When the optical input Pin increases and exceeds the threshold Pth ₃ , the optical output Pout
Becomes a high value P _H. When the optical input Pin decreases and becomes less than or equal to the threshold Pth ₂ , the optical output Pout sharply decreases from the high value P _H to the low value P _L.
At this time, it is assumed that the threshold Pth ₁ is set smaller than the threshold Pth ₂ .

The current clock I _C sets a low value (“0” state) to Ib ₁ and a high value (“1” state) to Ib ₂ as shown in the upper right and lower part of FIG. 7.

On the other hand, the amplitude intensity A _D of the input optical digital data I _D is set to an intermediate value between the threshold Pth ₂ and the threshold Pth ₃ , as shown in the upper left and lower left of FIG.

Now, the amplitude intensity A _{D of} the optical input digital data L _D and the amplitude value condition of the current clock I _C are set as described above, and referring to FIG. 7, the operation of the optical bistable semiconductor laser 10 of FIG. Will be explained.

When the current clock I _C has a low value Ib ₁ (“0” state), the relationship between the optical input Pin and the optical output Pout is governed by the optical bistable characteristic 101 at the upper left of FIG. 7. Therefore, input optical digital data L _D
Is a high value (“1” state), its operating point is Q ₁ , and a low value (“0” state), its operating point is Q ₀ ,
In either case, the optical output L ₁₀ of the optical bistable semiconductor laser ₁₀ has a low value P _L (“0” state).

The current clock I _C has a low value Ib ₁ (“0” state) to a high value Ib ₂
In the (“1” state), the relationship between the optical input Pin and the optical output Pout is governed by the optical bistable characteristic 100. Therefore, if the input optical digital data L _D has a high value A _D (“1” state), the operating point becomes Q ₃ , and the optical output L of the optical bistable semiconductor laser 10
_10, as shown in the optical output of the optical bistable laser diode of the lower right Figure 7, takes a high value P _H ( "1" state).

After all, even if either the input optical digital data L _D or the current clock I _C has a high value (“1” state), the optical bistable semiconductor laser 10
The optical output L ₁₀ cannot be high value P _H (“1” state), and high value P is high only when both inputs are high value (“1” state) at the same time.
_H (“1” state) is obtained.

Next, the optical output L _{10 of} the optical bistable semiconductor laser ₁₀ has a high value P _H.
Current clock I _C when held in (1 state)
Becomes a value Ib ₁ (“0” state) lower than the optical input digital data L _D (case (b) of FIG. 7) and the optical input digital data L _D is a value lower than the current clock I _C (lower) ( "0")
There is a case (case (b) in FIG. 7).

In the case of (b), the relationship between the light input Pin and the optical output Pout is dominated by optical bistable characteristics 101, in operating point Q _2, the light output L ₁₀ is a high value P _H ( "1" state) And the optical input digital data L _D takes a low value (“0” state), the operating point becomes Q ₀ , and the optical output L ₁₀ becomes a low value P _L (“0” state).

On the other hand, in the case of (b), the optical input Pin and the optical output Pou
The relationship with t is dominated by the optical bistable characteristic 100, and the operating point is Q
_4, the light output L ₁₀ holds a high value P _H ( "1" state), the current clock I _C becomes a lower value Ib ₁ ( "0" state), the operating point Q _0, and the light output L ₁₀ becomes a low value P _L (“0” state).

After all, while the optical output L _{10 of} the optical bistable semiconductor laser 10 holds a high value (“1” state), either one of the inputs, that is, the input optical digital data L _D or the current clock I _C is low. take the values ( "0" state), the light output L ₁₀ holds it high value P _H ( "1" state), when both input is taken low ( "0" state) at the same time, light The output L ₁₀ becomes a low value P _L (“0” state). Next, an optical bistable semiconductor laser
Since the operation of 11 is the same as that of the optical bistable semiconductor laser 10 and the operation of the optical bistable semiconductor laser 12 is the same as that of the optical bistable element 12 of the first embodiment, here,
A description of these operations will be omitted.

It can be seen that the operation of the optical bistable semiconductor laser described above is exactly the same as the operation of the optical bistable element at the optical clock L _C in the case of the first embodiment. Accordingly, the logical operation of the second embodiment is a timing chart showing the logical operation of FIG. 3, the inverted optical clock to the optical clock L _C The current clock I _C and the reverse current clock It can be understood by substituting each of them with each other, and the second embodiment can realize the optical D flip-flop operation similar to that of the first embodiment.

In the description of the first and second embodiments, the optical bistable element, the branching device, and the multiplexer are treated as separate parts, but if these functions are integrated on one board, It is obvious that a compact and economical optical D flip-flop circuit can be realized.

<Effects of the Invention> As described above, according to the present invention, a compact optical D flip-flop suitable for integration is realized by using an optical bistable element as a basic element, and an optical digital signal transmitted is optically converted. As it is, digital arithmetic processing becomes possible, which makes a great contribution to the construction of optical information processing systems, optical switching systems, and optical computers.

[Brief description of drawings]

FIG. 1 is an optical D flip-flop circuit diagram of the first embodiment of the present invention, FIG. 2 is a circuit diagram of the second embodiment of the present invention, and FIG. 3 is a logical operation of the circuit of the first embodiment. 4 is a schematic diagram of the optical bistable semiconductor laser, FIGS. 5 and 6 are characteristic diagrams of optical input and output of the optical bistable element, and FIG. 7 is a diagram of the optical bistable semiconductor laser. FIG. 8 is a diagram showing a truth table of the flip-flop circuit of the embodiment. L _D …… Input optical digital data, L _C …… Optical clock, I _C …… current clock, 10,11,12 …… Optical bistable element, 13,15,16 …… Multiplexer, 14 …… Splitter L _O …… Output optical digital data.

Claims (2)

[Claims] 1. A first optical bistable element for supplying a combined output of first, second, and third optical bistable elements, and optical digital data and an optical clock pulse to said first optical bistable element. A wave instrument,
A first branching device that divides an optical output signal from the first optical bistable element into two parts, and one optical output signal that has been divided into two parts by the branching part and an inverted optical clock pulse of the optical clock pulse are combined. A second multiplexer for supplying a wave output to the second optical bistable element, the other optical output signal split by the first branching device, and the light from the second optical bistable element. A third multiplexer for supplying a combined output with the output signal to the third optical bistable element, wherein the first optical bistable element outputs the optical digital data at the rising edge of the optical clock pulse. And the second optical bistable element sets the optical digital data at the rising edge of the inverted optical clock pulse,
The optical D flip-flop circuit, wherein the third optical bistable element outputs an optical output obtained by subjecting the optical output signal from the third multiplexer to peak value shaping. 2. A first optical bistable element having a current clock terminal, and an optical output from the first optical bistable element.
A second optical bistable element, which is provided with a branching device for splitting and an inverting current clock terminal, and receives one optical output signal from the branching device, and another optical output signal from the branching device. The optical output from the second optical bistable element is combined and output, and a third optical bistable element to which the optical output from the multiplexer is input, The first optical bistable element sets the optical digital data applied to the first optical bistable element at the rising edge of the current clock applied to the current clock terminal, and the second optical bistable element sets the inverted optical data. The optical digital data is set at the rising edge of the inversion current clock applied to the current clock terminal,
2. The optical D flip-flop circuit, wherein the optical bistable element of (1) outputs an optical output obtained by performing peak value shaping on the optical output from the multiplexer.