JPH0546640B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to optical digital logic circuits used in optical communication systems, optical information processing systems, optical switching systems, computers, and the like.

<Prior art> In recent years, advances in optical fiber technology and optical semiconductor technology have led to the development of long-distance optical communication systems for backbone transmission and optical LANs that connect distributed processing devices with high efficiency.
The system has been put into practical use. In these systems, optical technology is mainly used as a means of connection between functional devices, and the functionality is largely dependent on electronic circuit technology centered on LSI.

Reflecting the advent of a highly information-oriented society in the near future, as the information to be processed becomes more diverse and larger in volume, there are demands for ultra-high processing speeds and increasingly complex processing. To address these demands, optical technology must not only be used as a means of connection;
It has become necessary to use it as a means of logical processing.

In other words, it is possible to perform digital arithmetic processing on the transmitted optical digital signal as it is, output the processing result as light, and transmit it to other devices.
Optical processing equipment (optical information processing systems, optical switching systems, etc.) that fully takes advantage of the characteristics of light, such as high speed, broadband, and non-inductive properties, is essential.

The implementation of this type of device requires optical logic function blocks similar to those used in general electrical logic circuits, such as optical dates (INVERTOR, OR, AND,
EXOR, etc.), optical flip-flop circuits, optical shift register circuits, optical counters, etc. must be configured.

Hitherto, none of these optical logic function blocks have been put to practical use.

<Object of the present invention> In view of the above, the present invention is to provide a practical optical shift register.

<Configuration of the Invention> The optical shift register circuit of the present invention has a configuration in which a plurality of optical flip-flop circuits are connected in cascade.
a third optical bistable element; a first multiplexer that combines an input optical signal and an optical clock and outputs the combined light to the first optical bistable element; an optical splitter that divides the optical output signal from the stable element into two;
A second combiner that combines one of the optical output signals divided into two by the splitter with an inverted optical clock that is inverted with respect to the optical clock, and outputs the combined signal to the second optical bistable element. a third optical bistable device that combines the other optical output signal split by the splitter and the optical output signal from the second optical bistable device and inputs the combined signal to the third optical bistable device; a first optical bistable element having a current clock input terminal, and an optical splitter that divides the optical output signal from the first optical bistable element into two; a second optical bistable element having a current clock input terminal and receiving one of the optical output signals divided into two by the optical splitter as input light; and this second optical bistable element. a multiplexer that multiplexes the optical output signal from the optical splitter and the other optical output signal split into two by the optical splitter, and a third optical dual-wavelength multiplexer that receives the optical output signal from the multiplexer as input light. Two types of guide elements are used. In another configuration, a plurality of optical flip-flop circuits are connected in cascade via an optical splitter, and the output end of the optical splitter that is not connected to the optical flip-flop circuit is used as the intermediate tap output end. The optical flip-flop circuit uses the two types described above. That is, in the present invention, there are a total of four types of optical shift registers.

<Example> Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an optical shift register circuit showing a first embodiment of the present invention. This circuit is a 4-bit optical shift register circuit constructed by connecting four optical D flip-flop circuits 1, 2, 3, and 4 in series. Before explaining the operation of the optical shift register circuit, first, the configuration and operation of the optical D flip-flop circuit will be explained. FIG. 2 shows an optical D flip-flop circuit which is a basic circuit block of the optical shift register circuit according to the present invention, and FIG. 3 is a time chart showing its logical operation. This will be explained below with reference to both figures.
Optical digital data L _D having amplitude strength A _D and optical clock L _{C having amplitude strength A c are} combined by a multiplexer 13 and input to the optical bistable element 10 .

As shown in FIG. 8, in the optical bistable element 10, the optical output Pout shows a history with respect to changes in the optical input Pin, and within a certain input intensity range (range from P _A to P _C ),
It has two stable output light intensities. Here, the characteristics of the optical bistable device 10 will be explained in further detail with reference to FIG. 8.

As the optical input Pin increases, the optical output Pout becomes OAB
When the optical input Pin reaches _{P B ,} the optical output Pout rapidly increases from B to C, reaches a high value P _H , and then gradually increases to CD. Conversely, optical input
When decreasing Pin, DCE and optical output Pout gradually decrease, until optical input Pin reaches P _E , optical output Pout maintains a high value P _H , and when optical input Pin reaches P _A , optical output
Pout decreases more rapidly from E to A, reaches a low value P _L , and then gradually decreases to AO.

As an example of a device having such optical bistable characteristics, an optical bistable semiconductor laser shown in FIG. 7 has been announced. (Odagiri, et al. Tandem electrode structure DC
-PBH Optical Bistable Semiconductor Laser, National Conference of the Institute of Electronics and Communication Engineers, No. 937 (1983)). The optical bistable semiconductor laser has two divided P-side electrodes 31 and 32 that are electrically insulated by a slit 33 provided in parallel to Fabric Perot cavity surfaces 37 and 38. By applying appropriate bias currents I ₁ and I ₂ to each electrode 31 and 32, the relationship between optical input Pin and optical output Pout is as follows.
It is possible to provide bistable characteristics as shown in FIG. Now, returning to Figures 2 and 3, the light D
The configuration of a flip-flop and its logical operation will be explained.

The amplitude intensity A _D of the optical digital data L _D and the amplitude intensity A _{C of the optical clock L C are} set so that the following relational expression holds.

P _E A _D ≦P _B P _E A _C ≦P _B A _D +A _C P _C ...(1) Here, P _B , P _C and P _E are point B and C of the optical bistable characteristic in Fig. 8. This is the optical input at point and point D. That is, equation (1) means the following.

The optical output L 10 of the optical bistable element ₁₀ is a low value P _L (“0”
state), the input optical digital data L _D and optical clock L _C are simultaneously held at a high value (“1”).
light output L ₁₀ is a high value P _H
(“1” state), and when both inputs do not match, it holds a low value P _L (“0” state).

On the other hand, the optical output L ₁₀ of the optical bistable element 10 is a high value P _H
Even if either input, that is, input optical digital data L _D or optical clock L _C takes a low value (“0” state), the optical bistable element 10 remains at a high value (“1” state)
is held, and both inputs are at a low value (“0” state) at the same time.
When it takes , it becomes a low value P _L (“0” state).
These relationships are shown in the truth table of FIG.

Therefore, the optical bistable element 10 in FIG.
As shown in Figure 3, when the optical clock L _C starts up
Input digital data L _D is set by Cr ₁ , Cr ₂ , . . . , and when the input optical digital data falls D ₁ ,
The optical output L ₁₀ reset by D ₂ , . . . is obtained. However, the optical output L ₁₀ does not faithfully reproduce the pulse width of the input optical digital data _LD . Therefore, it is necessary to further process the optical output _L10 according to the following logic. By the turnout 14,
The light output L ₁₀ is equally divided into a light output L ₁₀₁ and a light output L ₁₀₀ . For the subsequent operation, the amplitude intensity of the optical output L ₁₀₁ and the optical output L ₁₀₀ must satisfy the amplitude intensity A _D shown in equation (1). A high value P _H of the optical output L ₁₀ of the optical bistable element 10 is set to meet this condition. The optical output L ₁₀₁ and the inverted optical clock _C with the amplitude intensity A _C are combined by the multiplexer 15 with the inverted polarity of the optical clock L _C and input into the optical bistable element 11 . The characteristics of the optical bistable element 11 are those of the optical bistable element 10.
It is exactly the same as that of . Therefore, when the inverted optical clock _C starts up, the optical bistable element 11
At r ₁ , r ₂ . . . , the optical output L ₁₀ is set, and at the falling edge of the inverted optical clock _C , at f _{1 ,} f ₂ .

Next, the optical output L ₁₀₀ and the optical output L ₁₁ are combined into a multiplexer 16.
The optical output _L16 is obtained. As shown in FIG. 3, the optical output 16 provides a sum signal of the optical output L ₁₀₀ and the optical output L ₁₁ , but its amplitude does not reach the logic level. Therefore, the light output L ₁₆
is input to the optical bistable element 12 and amplitude-shaped. The characteristics of the optical bistable element 12 are the same as those of the optical bistable element 10 described above.
and 11, as shown in FIG.
When Pin exceeds the threshold Pth, the optical output Pout becomes a low value
It has a comparator characteristic that rapidly increases from P _L to a high value P _H. To obtain this characteristic, the currents I ₁ and I ₂ of the optical bistable semiconductor laser shown in FIG. 7 may be set to appropriate values. By setting the threshold value Tth as shown in FIG. 3, it is possible to obtain output optical digital data L _O having an amplitude intensity P _H .

As a result, the output optical digital data _LO has a waveform in which _{the input optical digital data LD is} latched in synchronization with the rise of the optical clock LC Cr ₁ , Cr ₂ .

Therefore, it has become clear that the circuit shown in FIG. 2 operates as an optical D flip-flop circuit. By cascading four stages of the optical D flip-flop circuits, the optical shift register circuit according to the first embodiment of the present invention shown in FIG. 1 can be realized. In this optical shift register circuit, the optical output of each optical D flip-flop stage
L ₁ , L ₂ , L ₃ and L ₄ are directional couplers K ₁ , K ₂ , K ₃
The input optical digital data retrieved by K ₄
Optical digital data of _LD with 1-bit delay, 2-bit delay, 3-bit delay, and 4-bit delay is obtained as shown in FIG.

Optical bistable element 1 in the first embodiment described above
0, 11, and 12 use the optical bistable semiconductor laser shown in FIG. 7 as an example, but the present invention is not limited to this, and the optical bistable semiconductor laser has binary stable optical output with respect to optical input and exhibits hysteresis characteristics. It is obvious that the optical shift register circuit of the present invention can be realized as long as it is a stable element.

In the above embodiment, an example was shown in which the optical flip-flop circuits were connected through a branch, but the output of the flip-flop circuit at the previous stage may be directly connected to the input terminal of the flip-flop circuit at the next stage. However, in this case, the output is taken out from the final stage, so the range of application is narrower than that of the above-mentioned embodiments. This also applies to the embodiments described below.

Next, a second embodiment of the present invention is shown in FIG.
As in the first embodiment, this is a 4-bit optical shift register circuit in which four optical D flip-flop circuits 1, 2, 3, and 4 are connected in series. The difference from the first embodiment is that the clock signal to be applied to the optical bistable elements 10 and 11 used in the optical D flip-flop circuits 1, 2, 3 and 4 is supplied by a current clock _IC .

Before explaining the operation of the optical shift register circuit according to this embodiment, first, the configuration and operation of the optical D flip-flop circuit will be explained.

FIG. 6 shows an optical D flip-flop circuit constituting the second embodiment. Similar to the optical D flip-flop constituting the first embodiment, input optical digital data L _D is input to the optical bistable semiconductor laser 10 . In synchronization with the rise of the current clock _IC , the input optical digital data L _D is set, and the optical output L ₁₀
is obtained. The optical output L ₁₀ is equally divided into two optical outputs L ₁₀₁ and L ₁₀₀ by the splitter 14 . Light output L ₁₀₁
is input to the optical bistable semiconductor laser 11, and the optical output _L101 is set in synchronization with the rise of the inversion current clock _C , so that the optical output _L11 is obtained. The optical output L ₁₁ and the optical output L ₁₀₀ are combined by a multiplexer 16, and the obtained optical output L ₁₆ is further input to the optical bistable semiconductor laser 12 to obtain output optical digital data L _O.
The output optical digital data _LO is an output signal obtained by latching the input optical digital _LD at the rising edge of the current clock _IC .

In order to guarantee this operation, the amplitude value of the current clock I _C (or inverted current clock _C ) to the optical bistable semiconductor laser and the amplitude intensity A _D of the input optical digital data L _D (or optical output I ₁₀₁ ) are determined. It is necessary to add conditions similar to those in the first embodiment. 1st
FIG. 0 schematically shows the conditions for the amplitude intensity of the input optical digital data L _D and the amplitude value of the current clock Ic.

The upper right of FIG. 10 shows the relationship between the injection current I ₁ and the optical output Pout of the optical bistable semiconductor laser of FIG. 7. As the injection current I ₁ increases and becomes less than the threshold value Ith ₂ ,
The optical output Pout maintains a low value _PL . Once,
When the threshold value Ith ₂ is exceeded, the optical output Pout rapidly increases to a high value _PH , and even if the injection current I ₁ increases, the optical output Pout remains at the high value _PH . When the injection current I ₁ decreases and becomes below the threshold value Ith ₁ , the optical output Pout suddenly decreases from a high value _PH to a low value _PL . The injection current I ₁ of an optical bistable semiconductor laser having such characteristics as the optical output Pout with respect to the injection current I ₁ is set to a value Ib ₁ slightly smaller than the threshold value Ith ₁ and an intermediate value Ib ₂ between the threshold value Ith ₁ and the threshold value Ith _2. When set to , the optical input of the optical bistable semiconductor laser
The relationship between Pin and optical output Pout at the top left of FIG. 10 can be obtained.

In the case of I ₁ = Ib ₂ , the bistable property ₁₀₀ is
In the case of Ib ₁ , a bistable characteristic 101 is obtained. With the bistable characteristic 100, when the optical input Pin increases and exceeds the threshold value Pth ₁ , the optical output Pout becomes a high value P _H , and the optical input Pin decreases, and even with no input, the optical output P out becomes a high value P _H
is held. On the other hand, in bistable property 101,
When the optical input Pin increases and exceeds the threshold value Pth ₃ , the optical output Pout becomes a high value P _H. Optical input pin decreases,
When the threshold value Pth ₂ or less, the optical output Pout becomes a high value P _H
decreases rapidly from to a low value P _L. At this time, the threshold Pth ₁
It is assumed that Pth is set smaller than the threshold Pth ₂ . The current clock I _C is set to a low value (“0” state) at Ib ₁ and a high value (“1” state) to Ib ₂ , as shown in the upper right and middle lower portions of FIG. 10.

On the other hand, the amplitude intensity of the input optical digital data L _D
A _D is the threshold value as shown in the upper left and lower left of Figure 10.
Set to an intermediate value between Pth ₂ and threshold Pth ₃ . Now, set the amplitude intensity A _D of the input optical digital data L _D and the amplitude value conditions of the current clock I _C as above, and
The operation of the optical bistable semiconductor laser 10 shown in FIG. 6 will be explained with reference to FIG.

The operation of the optical bistable semiconductor laser 11 is the same as that of the optical bistable semiconductor laser 10, and the operation of the optical bistable semiconductor laser 12 is the same as that of the optical bistable element 12 of the first embodiment. Therefore, the explanation of these operations will be omitted.

When the current clock I _C is a low value Ib ₁ (“0” state), the relationship between the optical input Pin and the optical output Pout is shown in Figure 10.
It is dominated by the optical bistability characteristic 101 on the upper left. Therefore, when the input optical digital data L _D is a high value A _D (“1” state), its operating point is Q ₁ , and when it is a low value (“0” state), its operating point is Q _0. ,
In either case, the optical output L ₁₀ of the optical bistable semiconductor laser 10 takes a low value P _L (“0” state).

When the current clock I _C changes from a low value Ib ₁ (“0” state) to a high value Ib ₂ (“1” state), the optical bistable characteristic 100 governs the relationship between the optical input Pin and the optical output Pout. Therefore, if the input optical digital data L _D takes a high value A _D (“1” state), its operating point will be
Q ₃ , and the optical output of the optical bistable semiconductor laser 10
L ₁₀ takes a high value P _H (“1” state).

In the end, even if either the input optical digital data L _D or the current clock I _C has a high value (“1” state), the optical output ₁₀ of the optical bistable semiconductor laser 10 will have a high value P _H
(“1” state), and only when both inputs are high at the same time (“1” state), the high value P _H (“1” state)
become.

While the optical output L ₁₀ of the optical bistable semiconductor laser 10 maintains a high value P _H (“1” state), the current clock I _C changes to a low value Ib ₁ (“0” state) earlier than the input optical digital data L _D. ” state) (case A in Figure 10) and when the input optical digital data L _D becomes a low value (“0”) earlier than the current clock I _C (case B in Figure 10). exist.

In case A, optical input Pin and optical output Pout
The relationship between the two is governed by the optical bistable characteristic 101, the operating point is Q ₂ , the optical output L ₁₀ maintains a high value P _H (“1” state), and the optical input digital data L _D maintains a low value (“1” state). 0” state), its operating point is Q ₀
Therefore, the optical output L ₁₀ becomes a low value P _L (“0” state).

On the other hand, in case B, the relationship between the optical input Pin and the optical output Pout is governed by the optical bistable characteristic 100, the operating point is Q ₄ , and the optical output L ₁₀ is a high value P _H (“1”
state) and the current clock I _C is set to a low value Ib ₁
(“0” state), its operating point becomes Q ₀ ,
The light output L ₁₀ becomes a low value P _L (“0” state).

In the end, the optical output L ₁₀ of the optical bistable semiconductor laser 10
While holding a high value (“1” state),
Either the input optical digital data L _D or the current clock I _C has a low value (“0”).
state), the optical output L ₁₀ remains high.
When P _H (“1” state) is held and both inputs simultaneously take a low value (“0” state), the optical output L ₁₀ becomes a low value P _L (“0” state).

It can be seen that the operation of the optical bistable semiconductor laser described above is exactly the same as the operation of the optical bistable element in the optical clock _IC in the first embodiment. Therefore, the timing chart of the optical D flip-flop circuit in the second embodiment is the same as the timing chart of the optical D flip-flop circuit in the first embodiment (FIG. 3).
Then, the optical clock L _C and the inverted optical clock _C are, respectively,
This is equivalent to replacing the current clock I _C with an inverted current clock _C.

Now, returning to FIG. 5, the explanation of the optical shift register of the second embodiment will be continued.

The optical D flip-flop circuits described above are connected in cascade in four stages, and the optical outputs L ₁ , L ₂ , L ₃ and L ₄ of each stage are obtained through branchers K ₁ , K ₂ , K ₃ and K ₄ . It will be done.
The optical bistable semiconductor laser 10 is clocked by a current clock _IC , and the optical bistable semiconductor laser 11 is clocked by an inverted current clock _C obtained from electrical inverters INV1, INV2, INV3, and INV4. Current clock I _C and inverted current clock _C are supplied by electric clock E _C. The above logical operation can be understood by replacing the optical clock L _C with an electric clock E _C in the optical shift register operation diagram according to the first embodiment shown in FIG. The same optical shift register operation as in the example can be realized.

In the above description of the first and second embodiments, the optical bistable element, coupler, splitter, and multiplexer were treated as individual components, but it is important to integrate these functions on a single board. For example, it is obvious that a small and economical optical shift register circuit can be realized. or,
In the above embodiment, a 4-bit optical shift register was explained as an example, but the invention is not limited to this.
It is clear that a multi-bit optical shift register circuit can be realized by cascading an arbitrary number of optical D flip-flops.

<Effects of the Invention> As explained above, according to the present invention, an optical shift register circuit that is compact and suitable for integration using an optical bistable element as a basic element is realized, and the optical shift register circuit that is small and suitable for integration is realized. Digital arithmetic processing is now possible, and optical functional circuits essential for constructing optical information processing systems, optical switching systems, and optical computers are provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an optical shift register according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of an optical D flip-flop constituting the optical shift register circuit according to a first embodiment of the present invention, and FIG. 4 is a timing chart of an optical D flip-flop circuit, FIG. 5 is a timing chart of an optical shift register circuit according to a second embodiment of the present invention, and FIG. 6 is a timing chart of an optical shift register circuit according to a second embodiment of the present invention. The optical D flip-flop circuit that constitutes the shift register circuit, Figure 7 is a schematic diagram of the optical bistable semiconductor laser, Figures 8 and 9
The figure shows the optical input-output characteristic diagram of an optical bistable element, the first
0 is a bias current-optical input-optical output characteristic diagram of an optical bistable semiconductor laser, and FIG. 11 is a diagram showing a truth table of an optical flip-flop. 1, 2, 3, 4... Optical D flip-flop circuit, 10, 11, 12... Optical bistable element, L _D ...
…Input optical digital data, L _C …Optical clock,
L _C ...Inverted optical clock, I _C ...Current clock,
I _C ... Reversing current clock, L ₁ , L ₂ , L ₃ , L ₄ ...
Light output at each stage.

Claims (1)

[Scope of Claims] 1. Consists of a configuration in which a plurality of optical flip-flop circuits are connected in cascade, and the optical flip-flop circuit further includes first, second, and third optical bistable elements;
a first multiplexer that combines an input optical signal and an optical clock and outputs the combined light to the first optical bistable element; an optical splitter that splits one of the optical output signals into two, and one of the optical output signals split into two by the splitter is multiplexed with an inverted optical clock that is inverted with respect to the optical clock, and the second optical bistable element A second multiplexer outputs the optical output signal to the third optical bistable element, and combines the other optical output signal split by the splitter and the optical output signal from the second optical bistable element to output the optical output signal to the third optical bistable element. 1. An optical shift register circuit comprising: a third multiplexer for inputting to a stabilizing element. 2. A configuration in which a plurality of optical flip-flop circuits are connected in cascade via an optical splitter, and the output end of the optical splitter that is not connected to the optical flip-flop circuit is used as an intermediate tap output end,
Furthermore, the optical flip-flop circuit includes a first
a first multiplexer that combines second and third optical bistable elements, an input optical signal and an optical clock, and outputs the combined light to the first optical bistable element; an optical splitter that divides the optical output signal from the optical bistable element into two; and an inverted optical clock that inverts one of the optical output signals divided into two by the splitter with respect to the optical clock. a second multiplexer that combines and outputs the signal to the second optical bistable element; the other optical output signal split by the splitter; and an optical output signal from the second optical bistable element. and a third multiplexer that multiplexes the signals and inputs the combined signals to the third optical bistable element. 3. The optical flip-flop circuit is composed of a plurality of optical flip-flop circuits connected in cascade, and the optical flip-flop circuit further includes a first optical bistable element having a current clock input terminal, and a light output from the first optical bistable element. a second optical splitter that is provided with an optical splitter that splits the output signal into two, and a current clock input terminal, and that uses one of the optical output signals split into two by the optical splitter as input light; a stable element, a multiplexer for multiplexing the optical output signal from the second optical bistable element and the other optical output signal split into two by the optical splitter, and an optical multiplexer for combining the optical output signal from the second optical bistable element and the other optical output signal split into two by the optical splitter; An optical shift register circuit comprising a third optical bistable element whose output signal is input light. 4. A plurality of optical flip-flop circuits are connected in cascade via an optical splitter, and the output end of the optical splitter that is not connected to the optical flip-flop circuit is used as an intermediate tap output, and further, The optical flip-flop circuit includes a first optical bistable element having a current clock input terminal, an optical splitter that divides an optical output signal from the first optical bistable element into two, and a current clock input terminal. a second optical bistable element which is provided with the optical splitter and receives one of the optical output signals divided into two by the optical splitter as input light; and an optical output signal from the second optical bistable element. and the other optical output signal split into two by the optical splitter, and a third optical bistable element that receives the optical output signal from the multiplexer as input light. An optical shift register circuit characterized by: