JPH07118518B2 - Semiconductor memory - Google Patents

Description

The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having at least one write signal line pair or read signal line pair.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a conventional semiconductor memory.

D ₁ , D ₂ , D ₃ , D ₄ ; ₁ , ₁ , ₂ , ₃ and ₄ are digit lines, I is a drive circuit for driving a write signal line, and M ₁ , M ₂ , ..., M ₁₂ are 1 bit each. , O is an output amplifier that outputs a read signal, RD, ▲ ▼ are read signal line pairs, S ₁ , S ₂ , S
₃ , S ₄ are tangential circuits, W ₁ W ₂ , W ₃ are word lines, WR, ▲ ▼ are write signal line pairs, X is a row decoder, Y is a column decoder,
Y ₁ , Y ₂ , Y ₃ and Y ₄ are output lines.

FIG. 3 is a circuit diagram of an example of a conventional memory cell, showing a resistance load type static memory cell.

FIG. 4 is a circuit diagram of an example of a conventional connection circuit, showing a circuit for connecting the write signal WR, ▲ ▼ or the read signal line RD, ▲ ▼ to the digit line D.

A conventional example will be described with reference to these drawings.

When the content of the memory cell M ₁ is read, when the word line W ₁ is selected by the row decoder X, the content of each memory cell connected to the word line W ₁ is changed to the corresponding digit line.
, D appear as minute potential changes (Q ₃ and Q _{4 in} FIG. ₃ are conducting), the column decoder Y operates and the output line Y ₁ becomes high potential, and Q _{5 in} FIG. 4 is conducting. Digit line D ₁ , ₁
The potential difference between the read signal lines RD and ▲ ▼ is output, the output amplifier O for differential amplification operates, and the write signals WR and ▲ ▼ have the same potential, so the potential difference between the read signal lines RD and ▲ ▼ only. Is amplified and output. When writing the contents to the memory cell M ₁ , the drive circuit I is operated and a potential difference is generated between the write signal line WR and ▲ ▼.
After that, as in the case of reading, first, the word line W ₁ is selected, the output line Y ₁ becomes high potential, Q ₆ and Q _{7 in} FIG. 4 become conductive, and the digit lines D ₁ and ₁ and the write signal line WR. , ▲ ▼ are connected, and the potential output of the write signal is input to the memory cell M ₁ through the digit lines D ₁ , ₁ , and the content is held. At this time, a potential difference occurs between the read signal line RD and {circle around ()}, but since the output amplifier O is not operating, there is no other influence.

As the miniaturization of patterns progresses with the increase in memory capacity, the thickness cannot be ignored with respect to the width and spacing for metal wiring.
The coupling capacitance between adjacent wirings increases. For example, in a 256 kbit memory, the wiring width and spacing are 1-3 μm and the thickness is 0.5
~ 1μm, the capacitance between adjacent wiring is 10-40% of the total wiring capacity
It also becomes. In such a fine pattern, a pair of parallel read signal lines RD, ▲ ▼ of the output bus in the circuit of FIG.
Since the respective coupling capacitances between the respective wirings and the peripheral wirings are different, if the potentials of these peripheral wirings change before the operation of the output amplifier O is completed, noises of different magnitudes appear on the read signal line RD and ▲ ▼. Will occur. Further, the pair of parallel write signal lines WR, ▲ ▼ of the input bus have different coupling capacitances between them and the peripheral wirings, so that the potential of these peripheral wirings is held in the memory cell M. If the change is made before, noises of different magnitudes are also generated in the write signal line WR and ▲ ▼. The noise source may be a word line near the input / output bus, a signal line for driving the column decoder, or another signal line in the input / output bus.

[Problems to be solved by the invention]

In the conventional semiconductor memory described above, the coupling capacitance between the read signal line pair or the write signal line pair for transmitting signals of opposite phases and the adjacent signal transmission wiring is equal to each signal line of the signal line pair. However, since noise of different magnitudes is generated in the signal line pair, the output amplifier malfunctions, or incorrect information is input to the memory cell, which causes a drawback that the operation speed of the semiconductor memory decreases.

It is an object of the present invention to provide a semiconductor memory that has low noise and can operate at high speed.

[Means for solving problems]

In the semiconductor memory of the present invention, the output signals of the drive circuit are supplied to each of the plurality of memory cells arranged in a matrix via the connection circuit, and signals of opposite phases are transmitted to equally divide the entire length. A write signal line pair made up of a first signal line and a second signal line, which cross each other at an intersection and switch positions, and are arranged adjacent to each other in parallel at a portion other than the first intersection, The signals stored in the memory cells are read out through the connection circuit and the signals of opposite phases to be supplied to the output amplifier are transmitted and are separated from one end by one-quarter and three-quarters of the total length, respectively. Third signals that are crossed with each other at the second intersection and the third intersection and exchange positions, and are arranged adjacent to each other in parallel with each other at portions other than the second intersection and the third intersection. Line and fourth belief And a read signal line pair comprising a line,
The parallel portion of the third signal line and the fourth signal line is the first portion.
Of the second signal line and the third signal line in parallel with the parallel portion of the signal line and the second signal line by the first signal line and the second signal line, respectively. The first signal line and the second signal line are arranged to face each other at a half of the length of each divided portion, so that the first signal line and the second signal line are respectively connected to the third signal line and the fourth signal line. That is, the coupling capacitances between the two are made equal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

Although the memory cell arrangement is the same as that of the conventional example of FIG. 2, the pair of read signal lines RD and ▲ ▼ of the output bus are not parallel to each other, but intersect at a near the center a that bisects the entire length, and their positions are mutually different. Are replaced with each other. Also, the pair of write signal lines WR and ▲ ▼ of the input bus do not remain parallel,
1/4 and 3/4 of the total length away from the left end 2
_They intersect at points b ₁ and b ₂ and are arranged with their positions interchanged.

That is, the intersections b1 and b2 of the write signal line WR and ▲ ▼ are both displaced from the intersection a1 of the read signal line RD and ▲ ▼.

Therefore, the read signal line RD and ▲ ▼ are the word lines W ₁ , W ₂ ,
It has the same coupling capacitance as W ₃ , the write signal line WR, and the arbitrary signal line such as the signal line in the column decoder Y. Similarly, the write signal lines WR and ▲ ▼ have the same coupling capacitance as the word lines W ₁ , W ₂ , W ₃ , the read signal lines RD, ▲ ▼, and any signal line such as the signal line in the column decoder Y. ing. Although the length of the column decoder Y is slightly smaller than the length of the write signal lines WR, {circle around (3)}, their total length is large, so the difference can be practically ignored.

Therefore, before the operation of the output amplifier O is completed, the word line
W ₁ , W ₂ , W ₃ , signal line in column decoder Y or write signal line W
When the potentials of R and ▲ ▼ fluctuate, noise of equal magnitude is generated in the pair of read signal lines RD and ▲ ▼, and the output amplifier that performs differential amplification does not malfunction. Similarly, when inputting information to the memory cell, the word line
W ₁ , W ₂ , W ₃ , signal line in column decoder Y or read signal line R
If the potential of D, ▲ ▼ fluctuates, write signal line WR and ▲
Since noises of the same magnitude are generated in ▼ and
No erroneous information is written in the flop type memory cell.

The case where the flip-flop type memory cell is provided has been described above. However, even if the type of the memory cell is different, the noise due to the capacitive coupling is smaller than that in the conventional case, and thus the possibility of writing erroneous information is large. Needless to say, it is reduced to.

Also, the case where a pair of signal lines exist in each of the input bus and the output bus has been described, but the number of pairs of signal lines through which signals of opposite phases are transmitted may be arbitrary.

〔The invention's effect〕

As described above, according to the present invention, by arranging the write signal line pair and / or the read signal line pair at one or more locations and arranging the positions thereof interchangeably, each of these signal line pairs can be replaced with another arbitrary one. Since the coupling capacity between the signal line and the signal line can be made equal and small, noise due to capacitive coupling due to potential fluctuation of the signal line can be reduced, and high speed operation of the semiconductor memory can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a conventional semiconductor memory, FIG. 3 is a circuit diagram of an example of a conventional memory cell, and FIG. It is a circuit diagram of an example of a circuit for connection. D ₁ , D ₂ , D ₃ , D ₄ ; ₁ , ₂ , ₃ , ₄ ... Digit line, I ...
… Drive circuit, M ₁ , M ₂ , ……, M ₁₂ …… Memory cell, O …… Output amplifier, RD, ▲ ▼ …… Read signal line, S ₁ , S ₂ , S ₃ , S ₄
...... Connection circuit, W ₁ , W ₂ , W ₃ …… Word line, WR, ▲ ▼
...... write signal line, X ...... row decoder, Y ...... column _{decoder, Y 1, Y 2, Y} 3, Y 4 ...... output line.

Claims (1)

[Claims] 1. A first crossing point for transmitting output signals of a drive circuit to a plurality of memory cells arranged in a matrix form via connection circuits and transmitting signals of opposite phases to divide the entire length equally. And a write signal line pair formed of a first signal line and a second signal line that are adjacent to each other in parallel with each other at positions other than the first intersecting point and that are interchanged in position, and the memory cell A second phase of reading the signal stored in the circuit through the connection circuit and transmitting signals of opposite phases to be supplied to the output amplifier, which are separated from one end by one-quarter and three-quarters of the total length, respectively. Crossing each other at the intersection and the third intersection and switching positions, and third signal lines that are arranged adjacent to each other in parallel to each other at portions other than the second intersection and the third intersection, and Fourth
A pair of read signal lines formed of signal lines, the parallel portion of the third signal line and the fourth signal line being parallel to the parallel portion of the first signal line and the second signal line. The second crossing point and the third crossing point are respectively opposite to the half point of the length of each part where the first signal line and the second signal line are equally divided by the first crossing point. The semiconductor memory is characterized in that the first signal line and the second signal line have the same coupling capacitance between them and the third signal line and the fourth signal line, respectively.