JPH07118697B2 - PN code inspection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PN code inspection circuit used as a transmission line test signal for communication equipment, and more particularly to a PN code inspection circuit which speeds up pulling of a signal under test into an internal PN code generation circuit. .

[0002]

2. Description of the Related Art A method for shortening the synchronization time of a digital control line using a PN code is disclosed in, for example, Japanese Patent Laid-Open No. 2-140031. The synchronous pull-in time shortening method shown therein is composed of a shift register for inputting digital control line data, sequentially shifting and outputting the data, a PN generator for generating a PN pattern, and a PN pattern comparator. The sync pull-in time is shortened by adding a simple circuit to the frame sync circuit that pulls in the digital control line data.

As a conventional PN code checking circuit, a code checking circuit based on a generator polynomial X ¹⁵ + X + 1 (CCITT recommendation 0.151) is shown in FIG. As shown in FIG. 2, the conventional PN code inspection circuit includes a PN code generation circuit 11, a flip-flop 12 for retiming the external input data under test 101, and a signal generated in the PN code generation circuit 11. A comparator 13 for collating with externally input data under test, and a PN code generation circuit 1 for the data under test.
A pull-in counter 14 that counts the number of pull-in when pulling in 1 is provided.

In the conventional circuit, when the PN code is inspected, the external input data is first drawn into the PN code generating circuit 11. At this time, the PN code generating circuit 11 is an n-stage shift register. Since it is composed of, the data under test for n bits must be fetched. Therefore, it is necessary to count the pull-in start control signal from the external control system circuit by the pull-in number counter 14, generate a control signal for pulling in for n clock time, and control the 2-1 selector 15 in the PN code generation circuit. .

[0005]

In this conventional PN code inspection circuit, it is necessary to pull in n clock time when the external data under test is pulled into the PN code generation circuit in the inspection circuit at the start of measurement. The pull-in time increases as the PN code becomes higher-dimensional. Moreover, since the power consumption during pull-in is proportional to the number of stages, the power consumption increases in the high-dimensional PN code inspection circuit.

Therefore, an object of the present invention is to realize the pulling of the data under test into the PN code generation circuit in one clock and to keep the power consumption low even in the high-dimensional PN code inspection circuit.

[0007]

According to the PN code inspection circuit of the present invention, an n-stage shift register of the PN code generation circuit in the inspection circuit is composed of n flip-flops and n 2-1 selectors, Independently of the PN code generation circuit, it has n flip-flops for inputting data under test as a pull-in enable signal.

Further, the PN code check circuit according to the present invention is
A PNn stage code generation circuit, an n stage shift register for inputting data under test from the outside, and a comparator for collating the code generated in the PNn stage code generation circuit with the data under test are provided. The code generation circuit includes n number of flip-flops with enable as a synchronization pull-in enable signal, n number of 2-1 selectors, and a coefficient of a generation polynomial of “1” among the n number of flip-flop outputs.
In the configuration in which the exclusive OR circuit that receives the output of the flip-flop in accordance with the above item is connected in cascade, (i = 1,
2, 3, ..., N), one input of the 2-1 selector is A _i , the other input is B _i , the output is Y _i , the input of the flip-flop is D _i , the output is Q _i , exclusive logic When the output of the sum circuit is represented as P, the input of the flip-flop of the n-stage shift register is represented as D' _{i + 1} , and the output is represented as _{Q'i + 1} , A
_i and Q _{i + 1} , B _i and Q'i _{+ 1} , D _i and Y _i , D' _i and Q ' _i , A _i and P are connected, and D' ₀ is input the data under test from the outside. However, the pull-in control signal is commonly connected to the selection control terminals of the n 2-1 selectors.

[0009]

An embodiment of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a PN code check circuit according to an embodiment of the present invention. Here, n = 15,
A check circuit of a PN15 stage code by the generator polynomial X ¹⁵ X + 1 (CCITT recommendation 0.151) will be shown as an example.

The PN code check circuit according to the present embodiment has a PN code check circuit.
15-stage code generation circuit 1 and data under test 10 from the outside
Shift register 2 for inputting 1 and PN code generation circuit 1
Comparator 3 for collating the code generated in 1. with the data under test
It has and.

The PN code generation circuit 1 is an n-stage shift register consisting of n (= 15) 2-1 selectors 5 and flip-flops 6, and a flip-flop output whose term corresponds to "1" according to the generator polynomial. Is formed from the exclusive OR circuit 4. In the 2-1 selector 5, one input terminal A is connected to the Q output of the flip-flop 6 in the PN code generation circuit 1, and the other input terminal B is the pull-in enable 103 of the shift register 2 to which the data under test is input.
Is connected to the Q output of the flip-flop 7 which uses the signal as an enable signal. 2-1 Selection control terminal S of selector 5
Inputs the pull-in control 102.

The PN code generation circuit 1 includes n (= 15) flip-flops with enable, which are synchronization pull-in enable signals, and n (= 15) 2-1 selectors.
Of the n (= 15) outputs of the flip-flops, the exclusive-OR circuit that receives the output of the flip-flop according to the term of which the coefficient of the generator polynomial is “1” is connected in cascade, and (i = 1, 2, 3, ..., N), one input of the 2-1 selector is A _i , the other input is B _i , and the output is Y.
_i , the input of the flip-flop is D _i , the output is Q _i , the output of the exclusive OR circuit is P, and the input of the flip-flop of the n-stage shift register is D ′ _{i + 1} and the output is Q ′.
When expressed as _{i + 1} , A _i and Q _{i + 1} , B _i and Q ′ _{i + 1} , D _i
And Y _i, D _'i and Q' _i, connects Ai and P, the D _'0 to enter the test data from the outside, the pull-in control signal to the n-number of 2-1 selectors select control terminal They are commonly connected.

When measuring the external input data, the data under test is first pulled into the PN code generation circuit 1.

In this circuit, since the flip-flops of the shift register and the shift register in the PN code generation circuit correspond to each other on a one-to-one basis, the pull-in control 102 sets the 2-1 selector 5 to the input B selection. Data acquisition during measurement is completed in 1 clock. The shift register 2 has a pull-in enable 1 indicating an enable state only for n (= 15) clock time before the pull-in control 102 becomes the pull-in side (2-1 selector 5 selects the input B).
By 03, the data under test is pulled in only for n (= 15) clock time.

In the present embodiment, the synchronization pull-in enable is input to the reset of the flip-flop 7, but this may be appropriately set such as set input according to the application.

[0017]

As described above, in the present invention, the pull-in control of the data under test is performed by the pull-in enable for the shift register for realizing the pull-in of the data under test in one clock time. Since the shift register operates only during the n clock time from the time before the clock is brought into the pull-in state to the start of the pull-in, the power consumption by the shift register can be minimized.

The power consumption in the PN code inspection circuit is P
The flip-flops included in the N code generation circuit and the shift register occupy a large proportion, and the power consumption is proportional to the number n of PN code stages. Especially, in a high-dimensional PN pattern inspection circuit including many flip-flops, power consumption becomes very large. However, in the present invention, since the shift register operates only for n clock times before the n-th clock time when the 2-1 selector becomes the pull-in state and before the start of pull-in, the power consumption by the shift register can be minimized.

[Brief description of drawings]

FIG. 1 is a block diagram of a PN code check circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional PN code check circuit.

[Explanation of symbols]

 1 PN 15-stage code generation circuit 2 15-stage shift register with reset 3 Comparator 4 Exclusive OR circuit 5 2-1 selector 6 Flip-flop 7 Flip-flop with reset 14 Pull-in counter 101 Test data 102 Pull-in control 103 Pull-in enable 104 Matching result 105 Test data 106 Generated data

Claims (2)

[Claims] 1. A PN n-stage code generation circuit, an n-stage shift register for inputting data under test from the outside, and said PN.
A comparator for collating the code generated in the n-stage code generation circuit with the data under test is provided, and the PN n-stage code generation circuit has n flip-flops and n 2-1 selectors, The n-stage shift register has n flip-flops for inputting data under test as pull-in enable signals independently of the PN code generation circuit.
Code checking circuit. 2. A PN n-stage code generation circuit, an n-stage shift register for inputting data under test from the outside, said PN
a comparator for collating the code generated in the n-stage code generation circuit with the data under test, wherein the PN n-stage code generation circuit includes n number of flip-flops with enable as a synchronization pull-in enable signal;
A configuration in which n 2-1 selectors and an exclusive OR circuit that receives the outputs of the flip-flops according to the term of the coefficient of the generator polynomial according to the term “1” among the n flip-flop outputs as the input are cascaded. , (I = 1, 2, 3, ..., N)
, One input of the 2-1 selector is B _i , the other input is B _i , the output is Y _i , the input of the flip-flop is D _i , the output is Q _i , and the output of the exclusive OR circuit is P. the n-input of D flip-flop stage shift register a _i and Q _{i + 1} when the _{'i + 1,} the output Q' representing the _{i + 1,} B _i and Q _{'i + 1,} D _i and Y _i, D _'i and Q' _i, connects Ai and P, enter under test data from the outside to the D _'0, the pull-in control signal in common to the selection control terminal of the n 2-1 selectors A PN code check circuit characterized by being connected.