JPH07120259B2 - Data processing device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a data processing device for performing data transfer by bit boundary.

[Conventional technology]

FIG. 8 is a diagram showing an example in the case of transferring arbitrary bit length data on the data bus or in the register to a register having the same bit length as the data bus width.

The register (source register) 11 and the register (destination register) 12 are registers having the same bit length, and data A and B and data C and D are stored therein (FIG. 8 (1), (2)). In this state, only the data A in the register 11 is transferred to the register 12, and the data A and D are finally stored in the register 12. First, in order to save the data A and B in the register 11, the data A and B are saved in another register. Then register 1
Data other than A of 1 is set to "0", and data other than D of the register 12 is set to "0" ((3) and (4) in FIG. 8). After that, the logical sum of the registers 11 and 12 is calculated and the result is stored in the register 12 ((5) in FIG. 8).

FIG. 9 and FIG. 10 are diagrams showing an example of a case where data is transferred across word boundaries. The lower 11 bits of the data in the register a, which is a saw register, are placed in the upper side of the memory (n, n + 1), and the upper 5 bits of the data in the source register a are placed in the lower side of the memory (n + 2, n + 3). As shown in the figure, the case of writing each will be described with reference to FIG. 10 (here, the memory (n, n + 1) means one data composed of data at addresses n and n + 1).

(1) Transfer the data in register a to register b.

(2) Read data from the memory (n, n + 1) and transfer it to the register c.

(3) The data in register b is shifted to the left by 5 bits.

(4) Set the lower 5 bits of register b to "0".

(5) The upper 11 bits of register c are set to "0".

(6) The logical sum of the data in register b and the data in register c is calculated and stored in register c.

(7) Write the data in register c to memory (n, n + 1).

(8) Transfer the data in register a to register b.

(9) Read data from the memory (n + 2, n + 3) and transfer it to the register c.

(10) Shift the data in register b to the right by 11 bits.

(11) Set the upper 11 bits of register b to "0".

(12) Set the lower 5 bits of register c to "0".

(13) The ethics of the data in register b and the data in register c is calculated and stored in register c.

(14) Write the data in register c to memory (n + 2, n + 3).

In this way, in the data transfer method by word boundary
It also requires 14 steps.

[Problems to be solved by the invention]

In the conventional data transfer method described above, first, all unnecessary data must be set to "0", the logical sum must be calculated using an accumulator, and the result must be stored in a register. If this is the case, the procedure is complicated, such as having to save to another register, resulting in the disadvantage that the number of data processing steps increases and the execution speed decreases.

[Means for solving problems]

The data processing device of the present invention includes a bit boundary register that holds a bit boundary that is bit position information of a transfer boundary of data transferred from a source register to a destination register, and among each bit that configures the data, It has a direction control means to select the bit corresponding to the upper or lower bits of the bit boundary, and when the write signal is input, only the upper or lower bits of the data of the bit boundary selected by the direction means are transferred from the source register to the destination register. And a data transfer control circuit for writing.

[Action]

In this way, the data transfer control circuit can write data from the source register to the destination register only for the bits of data higher or lower than the bit boundary selected by the direction control means based on the bit boundary indicated by the bit boundary register. Therefore, it is not necessary to clear the unnecessary bits for data transfer in each bit of the source register and the destination register, and it is not necessary to clear them. Therefore, if you want to keep the data of the source register as it is, Since it is not necessary to save the data in the data transfer process and the data transfer process can be performed in a small number of steps, it is possible to perform the data transfer at a high speed at a byte boundary or a word boundary, which requires a long execution time.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment in the case of performing data transfer by a bit boundary of the data processing device of the present invention.

In this embodiment, a 16-bit length source register 1 and a bit-boundary register 3 that holds bit boundary information, a 16-bit length destination register 2 that inputs the data of the source register 1, and a bit-boundary information bit The write signal that is input from the boundary register 3 and that corresponds to the bit boundary information and that is higher or lower than the predetermined bit of the destination register 2 is output, and the input write signal of the source register 1 corresponding to that bit is output. The data transfer control circuit 4 writes data in the destination register 2.

FIG. 2 is a circuit diagram showing a concrete example mainly implemented by the data transfer control circuit 4 and the MOS type transistor of FIG. 1 and a connection state to the outside, and FIG. 3 is a waveform diagram showing its operation. .

In the data transfer control circuit 4, the gate is the basic clock φ.
N-type MOS that inputs 1 and has its source connected to ground
Transistors 96, 100, 101, ..., 115, inverters 90, 91, ..., 93 whose input terminals are connected to output terminals Q0, Q1, ..., Q3 of bit boundary register 3 respectively, and a gate connected to the output terminal of inverter 93 The sources are connected to the drains of the N-type MOS transistors 100, 101, to 107, respectively, and the gates are connected to the input terminals of the inverter 93, and the sources are connected to the N-type MOS transistors 108 and 109. N-type MOS transistors 208, 209, ..., 215 respectively connected to the drains of ~, 115, and a N-type MOS transistor whose gate is connected to the output terminal of the inverter 92 and whose source is connected to the drains of the N-type MOS transistors 200, 201, 202, 203, 208, 209, 210, 211, respectively. 300,301,302,3
03,308,309,310,311 and the gate are connected to the input terminal of the inverter 92, the source is N-type is N-type MOS transistor 204,2
05.206.207,212,213,214,215 N-type MOS transistors 304,305,306,307,312,313,3 respectively connected to the drain
14,315, the gate is connected to the output terminal of the inverter 91,
Source is N-type MOS transistor 300,301,304,305,308,30
N-type MOS transistors 400, 401, 404, 405, 408, 409, 412, 413 respectively connected to the drains of 9,312, 313, and a gate connected to the input terminal of the inverter 91 and a source connected to the N-type MOS
N-type MOS transistors 402, 40 connected to the drains of the transistors 302, 303, 306, 307, 310, 311, 314, 315, respectively.
3,406,407,410,411,414,415 and the gate is an inverter 90
Connected to the output terminal of the N-type MOS transistor 40
N-type MOS transistors 500, 502, 504, 506, 508, 5 respectively connected to the drains of 0, 402, 404, 406, 408, 410, 412, 414
10,512,514 and the gate are connected to the input terminal of the inverter 90, and the sources are N-type MOS transistors 401,403,405,407,40
N-type MOS connected to the drains of 9,411,413,415 respectively
Transistors 501,503,505,507,509,511,513,515 and N
Type MOS transistors 500, 501, ~, 515 control lines C0, C1, ~, C15 respectively connected to the drain and the gate is control line C
0, C1, ..., C15 are connected respectively, and the sources are connected to point P.
_The drains are at points P ₁ , P ₂ , ~, P at ₀ , P ₁ , ~, P ₁₅ , respectively.
N-type MOS transistor connected to ₁₆ 600,601, ~, 615
, The gate inputs the basic clock φ1, and the source is the power supply.
Connected to V _CC and the drains are control lines C0, C1, ..., C1 respectively.
P-type MOS transistors 700, 701 to, 715 connected to 5, and
The gate inputs the basic clock φ1, the source is the power supply V _CC
A P-type transistor 98 connected to the point P ₀ and the drain of the N-type MOS transistor, and a point P ₁ ,
P _2, ~, control lines M0 respectively connected to P _16, M1, ~, M15
And a write signal ▲ ▼ is input to one input terminal, and the other input terminal is composed of OR circuits 800, 801, to 815 connected to the control lines M0, M1, to M15, respectively.

The OR circuit 800, 801, of the data transfer control circuit 4
The outputs of ˜, 815 are output to the register cells B0, B1, ˜, B15 forming the destination register 2, respectively.

The gates of the register cells B0, B1, ..., B15 are OR circuits 800,
The P-type MOS transistor Q _P for inputting the outputs of 801, ..., 815 and the source for inputting the bit data of the corresponding source register 1 of each register cell B0, B1, ..., B15, the gate and the drain, respectively. An N-type MOS transistor Q _N connected to the gate and drain of the P-type MOS transistor Q _P ,
An input terminal is connected to the drain of the P-type MOS transistor Q _P and an input terminal is connected to the output terminal of the inverter I.
It has an inverter J whose output end is connected to the source of the N-type MOS transistor Q _N.

Next, the operation of this embodiment will be described with reference to FIG.

When the basic clock φ1 is "0", the N-type MOS transistors 96, 100, 101, ..., 115 are off and the P-type MOS transistors 98, 700, 701, ..., 715 are on. Therefore, the point P ₀
Is connected to the power supply V _CC through the P-type MOS transistor 98,
The gates of N-type MOS transistors 600, 601, to 615 are also P-type M
The signal line X is precharged because it is connected to the power supply V _CC through the OS transistors 700, 701 to 715. Further, while the basic clock φ1 is at "0" level, the register cells B0, B1,
Writing to ~, B15 is prohibited.

Next, when the basic clock φ1 becomes "1" level, the bit boundary register 3 outputs the set output to the output terminals Q0, Q1,
Output to Q2 and Q3 (in this specific example, the output levels of the output terminals Q0, Q1, Q2, and Q3 are "1", "0", "0", and "1" levels, respectively). When the output terminal Q0 is at "1" level, the N-type MOS transistors 501, 503, 505, 507, 509, 511, 513, 515 turn on, and N
Type MOS transistors 500, 502, 504, 506, 508, 510, 512, 514 are turned off. When the output terminal Q1 is at "0" level, the N-type MOS transistors 400, 401, 404, 405, 408, 409, 412, 413 turn on, and the N-type MOS transistors 402, 403, 406, 407, 410, 411, 41.
4,415 turns off. Similarly, depending on the output levels of the output terminals Q2 and Q3, N-type MOS transistors 200, 201, to 215, 300, 301,
~, 315 on / off is set. Further, since the basic clock φ1 is at "1" level, the N-type MOS transistors 96, 10
0,101, to 115 are turned on, and P-type MOS transistors 98,700,70
1, ~, 715 are off. In this case, each control line C0, C1, ..., C
N-type MOS transistor 100,10 connected between 15 and ground
It is the N-type MOS transistors 109, 209, 309, 409, 509 between the control line C9 and ground that all 1, to 515 are turned on.
Therefore, only the control line C9 becomes the "0" level. When the control line C9 is at "0" level, the N-type MOS transistor 609 is turned off. Since the N-type MOS transistor 609 is off, points P ₁₀ , P ₁₁ , ~, P ₁₆ of the control line X hold the precharged potential "1" level, and points P ₀ , P ₁ , ~, P _{Since 9} is connected to the ground through the N-type MOS transistor 96 which is turned on, it becomes "0" level. On the other hand, the input terminal is the control line M9, M10,
The OR circuits 809, 810, ~, 815 connected to the "1" level points P ₁₀ , P ₁₁ , ~, P ₁₆ via ~, M15 respectively output the write signal WR input to the other input terminals. Ban. However, one of the input terminals of the OR circuits 800, 801, to 808 has a control line M.
0, M1, ~, through M8 "0" level points P _1, P _2, ~, and outputs a write signal WR to input because it is connected to P ₉ to the other input terminal. Therefore, the OR circuit 809,810,
Although the data D9, D10, ~, D15 from the source register 1 is not written to the register cells B9, B10, ~, B15 of the destination register 2 which are write-protected by ~, 815,
The data D0, D1, ..., D8 from the source register 1 is written in the register cells B0, B1, ..., B8 to which the write signals are input by the OR circuits 800, 801, ..., 808. As described above, in this specific example, based on the bit boundary specified by the bit boundary register 3, data can be written only to the corresponding register of the destination register 2 and the register cell corresponding to the bit lower than the register cell, Writing data to the register cell is prohibited.

FIG. 4 is a diagram schematically showing data writing. In order to create the data C, B from the data A, B of the source register 1 and the data C, D of the destination register 2, simply the data A, B of the source register 1 is processed according to the processing of this specific example. If it is written in, the data C and B can be obtained in the destination register 2.

FIG. 5 shows a second specific example of the embodiment shown in FIG. In the first specific example, only the register cells corresponding to the bits lower than the predetermined bit can be written, but this specific example has means for selecting the lower or higher bits than the predetermined bit. Therefore, the description will be focused on this selecting means, and the other parts are similar to those of the first specific example, and detailed description thereof will be omitted.

This selecting means is an inverter 9 for inputting the direction control signal DIR.
4, the gate is the input terminal of the inverter 94, and the drain is the point P.
₁₆ , an N-type MOS transistor 95 whose source is connected to the ground, and an N-type MOS transistor whose gate is connected to the output terminal of the inverter 94, whose drain is connected to the point P ₀ , and whose source is connected to the drain of the N-type MOS transistor 96, respectively. It is composed of a MOS transistor 97.

Therefore, as in the case described in the first specific example, if the direction control signal DIR is "0" level when the control line C9 is selected and becomes "0" level, the N-type MOS transistor
Since 95 is off and the N-type MOS transistor 97 is on, it is exactly the same as in the first embodiment, and only the register cells B0, B1, ..., B8 of the destination register 2 can be written. However, when the direction control signal DIR is at "1" level, the N-type MOS transistor is turned on and the N-type MOS transistor is turned on.
97 the point P ₁ to become _{OFF, P 2, ~, "1} " level of the P ₉ is held, the point _{P 10, P 11, ~,} P 16 is N-type MOS transistor 95
Since it is connected to the ground via, it becomes "0" level. One input terminal is "1" level points P _1, P _2, ~, OR circuits 800 and 801 connected to the P _9, ~, 808 prohibits the output of the write signal WR to input to the other input terminal. The OR circuit 809,810, whose one input terminal is connected to the points P ₁₀ , P ₁₁ , ..., P ₁₆ at the "0" level
~, 815 outputs the write signal WR. Register cell B of destination register 2 to which write signal WR is input
Only 9, B10, to, B15 can be written, and register cell B
Writing to 0, B1, to, B8 is prohibited.

FIG. 6 is a diagram schematically showing. Source register 1 data A and B and destination register 2 data C and D
To obtain the data C and B, the direction control signal DIR is set to "0" level, and to obtain the data A and D, the direction control signal DIR is set to "1" level. Data C and B or data A and D are obtained, respectively.

FIG. 7 is an explanatory diagram showing a case where the second specific example is applied to the data processing described in FIGS.

(1) Transfer the data in register a to register b.

(2) Read data from the memory (n, n + 1) and transfer it to the destination register c.

(3) Rotate the data in register b to the left by 5 bits.

(4) The bit boundary is set between the 5th bit and the 6th bit, the direction control signal DIR is set to "1", and the data of the 5th bit and below is write-inhibited. Write through.

(5) Write the data in register c to memory (n, n + 1).

(6) Read the data in the memory (n + 2, n + 3) and transfer it to the register c.

(7) The direction control signal DIR is set to "0", and the data in the register b is written into the register c via the data transfer control circuit 4.

(8) Write the data in register c to memory (n + 2, n + 3).

In this way, it is possible to execute what has conventionally required 14 steps in 8 steps.

〔The invention's effect〕

As described above, according to the present invention, only the bits of data higher or lower than the bit boundary selected by the direction control means based on the bit boundary designated by the bit boundary register are written from the source register to the destination register. As a result, there is an effect that it is possible to perform high-speed transfer of data that crosses a byte boundary and a word boundary, which takes a long time to execute.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data processing device of the present invention, and FIG. 2 is a circuit diagram showing a first specific example in which the data transfer control circuit 4 of FIG. FIG. 3 is a waveform diagram showing the operation of the first concrete example, and FIG.
5 schematically shows a state in which data is written from the source register 1 to the destination register 2 according to the concrete example of FIG. 5, FIG. 5 is a circuit diagram showing a second concrete example of the data transfer control circuit 4, and FIG. FIG. 7 is a diagram schematically showing a state in which data is written from the source register 1 to the destination register 2 according to the second specific example. FIG. 7 shows that the data in the source register 1 is transferred by the data transfer control circuit 4 over a word boundary. Fig.8,9,10
The figure is a diagram showing a state in which data is transferred by a conventional method. 1 ... Source register, 2 ... Destination register, 3 ... Bit boundary register, 4 ... Data transfer control circuit, 90,91, ..., 93 ... Inverter, 95,96,9
7 ... N-type MOS transistor, 98 ... P-type MOS transistor, 100,101,-, 615 ... N-type MOS transistor, 700,70
1, ～, 715 …… P-type MOS transistor, 800,801, ～, 815…
... OR circuit, B0, B1, ~, B15 ... register cell, C0, C1,
〜, C15 …… Control line, M0, M1, 〜, M15 …… Control line, ▲ ▼
…… Write signal, DIR …… Direction control signal, φ1 …… Basic clock.

Claims (1)

[Claims] 1. A data processing device having a function capable of simultaneously transferring data from a source register to all bits of a destination register, and when transferring less than all bits of the destination register, the few bits are transferred. Means for specifying the bit position of the destination register to be supplied, means for supplying the write signal only to the specified bit position, and supply of the write signal to bit positions other than the specified bit position Means for prohibiting the data transfer, and the data transferred from the source register is written only to the designated bit position, and the data stored at that time is stored as it is at other bit positions. And data processing device.