JPH07120341B2 - Data controller - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Outline Industrial field of use Conventional technology Problems to be solved by the invention Means for solving problems Problems Working Example Effect of the invention [Outline] Processing of various data A data controller that shortens the waiting time associated with access competition to shared memory for multiple data processing modules (hereinafter abbreviated as “functional unit”) automatically It was chosen to be the port that controls the access of the functional unit to the shared memory, with the purpose of allocating usage, handling functional unit contention for the shared memory, and preventing unnecessary latency. Recognition means to recognize that,
Based on the recognition of the recognition means, the address of the accessed functional unit is stored, and an instruction means for instructing to execute only data transfer of the functional unit having the stored address is provided. Based on the recognition of the means,
An automatic allocation control circuit that gives priority to multiple ports is provided, and when multiple functional units access the shared memory, multiple ports are sequentially assigned in the order of access according to the priority order, and the shared memory and the functional units that are permitted access. The configuration is such that data transfer between and is performed.

[Industrial application field]

The present invention relates to an apparatus that is composed of a plurality of data processing modules that execute various data processing, and that transfers data between the functional units, and in particular, a shared memory that temporarily stores the data transferred between the functional units. On the other hand, the present invention relates to a data control device that shortens the waiting time due to contention that occurs when each functional unit accesses.

The central processing unit in an information processing system is remarkably improved in performance and speed, and of course the number of data processing is large. Therefore, many files are required to store the data, and this file is Being able to use it from a central processing unit has become essential.

By the way, for example, a disk device used as an external storage device of an information processing system is indispensable as a system resident file and a virtual storage page file, and is also used as a large number of data files for storing enormous amounts of information. To be done.

By the way, it is becoming difficult for a disk controller for realizing such a demand to control and manage a large number of channel paths and disk devices by one processor. Therefore, the idea was to configure functional units corresponding to channels, functional units corresponding to disk devices, shared memory accessed by these functional units, and management functional units that manage all functional units. There is a disk controller in which each functional unit is connected by a common bus.

In a disk controller configured with such functional units, exclusive control is required for access to the memory shared by each functional unit, but it is necessary that there be little waiting time when performing this exclusive control. Is.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a disk controller configured by combining functional units.

Reference numeral 1 denotes a shared memory, which is connected to the common bus 8 via the boat 2 and is accessed by another functional unit connected to the common bus 8 to transfer data.

2 is a port, which is configured as shown in FIG.
Command sent from another functional unit via the receiver 16 and the address of the functional unit indicating the destination of the command,
The address for the common memory 1 indicating the destination is input.

For example, a command for instructing writing or reading of data is input to the decoder 11, an address indicating a destination is input to the comparison circuit 10, and the address is compared with the port address held by the port address 9. If they match, the decoder 11 is effective. Is transmitted.

When the command decoded by the decoder 11 becomes valid, the decoder 11 sets the address register 13 and the data buffer 14
Send the enable signal.

The command buffer 12 stores the address of the shared memory 1 indicating the destination, and the address is sent to the shared memory 1 via the address register 13. Therefore, the data sent by the functional unit after the address indicating the destination is stored in the data buffer.
It is transferred to the shared memory 1 via 14 and written in the shared memory 1.

When reading data from the shared memory 1, the data read to the data buffer 11 at the address sent by the address register 13 is sent to the common bus 8 via the driver 15.

When changing the address held by the port address 9, the address sent by the command buffer 12 is written in the port address 9 based on the signal sent by the decoder 11.

In this way, the port 2 controls access to the shared memory 1 from other functional units.

Numerals 4 and 5 are channel adapters, which are constructed as shown in FIG. 5, and the processor 19 reads out a program from the control memory 20 to operate, and through the interface circuit 17, the start I / O instruction from the channel which is the host device. The common bus control circuit 18
To send an address to the port 2 via the common bus 8 to transfer data with the shared memory 1.

The device adapters 6 and 7 are configured as shown in FIG. 5, and the processor 19 reads out a program from the control memory 20 to operate, sends a command to the disk device through the interface circuit 17, and communicates with the disk device. Data transfer between the shared memory 1 and the shared memory 1 is performed by controlling the common bus control circuit 18 to send an address to the port 2 via the common bus 8.

Reference numeral 3 denotes a resource manager, which is configured as shown in FIG. 6, and the processor 22 reads a program from the control memory 21 to operate and controls the common bus control circuit 23 to make the common bus 8
All start I / O commands from the channels transmitted by the channel adapters 4 and 5 are received and stored in the RAM 24, and the start I / O commands are centrally managed.

Then, the processing instruction is given to the channel adapters 4 and 5 and the device adapters 6 and 7 for each start I / O instruction. Further, the control information for each received all start I / O commands, the control information for each channel path, and the control information for each disk device are centrally stored, and other functional units are passed through the RAM access control circuit 25. It is possible to access the RAM 24 and read the control information.

In the disk controller configured in this way, for example, the channel adapter 4 is selected from the channels of the host device,
Upon receiving the start I / O command, resource manager 3
According to the instruction of (1), the specified disk device is connected to, for example, the device adapter 6 via the common bus 8 and data is transferred to and from the disk device. In this case, since the channel adapter 4 and the device adapter 6 temporarily store the data to be transferred to the shared memory 1, the port 2
To access.

Then, data is alternately stored in the shared memory 1 and data transfer is performed, but when this data transfer is not completed, the channel adapter 5 is selected from the channel and data is transferred to the disk device via the device adapter 7. , In order to temporarily store the data in the shared memory 1 in the same manner,
Although the port 2 is accessed, the port 2 cannot be used because another functional unit is occupied with the shared memory 1 during data transfer. Therefore, the processing efficiency is reduced.

FIG. 7 is a block diagram showing an example of a disk controller having a plurality of ports.

In FIG. 3, since one port has a low processing efficiency, a plurality of ports are provided to improve the processing efficiency in FIG. 7. That is, the ports 26 and 27 are provided in addition to the port 2. For example, the channel adapter 4 uses the shared memory 1
When accessing, the resource manager 3 is inquired about a free port, the port of the address specified by the resource manager 3, for example, port 27 is assigned, the address is sent to the port 27, and the shared memory 1 and the data transfer are performed. I do.

As another method, the channel adapters 4 and 5 and the device adapters 6 and 7 individually scan the ports 2, 26 and 27 respectively to search for a free port and access it.

[Problems to be solved by the invention]

The method of inquiring a free port to the resource manager 3 and allocating the free port has a problem that it takes an unnecessary time because it is kept waiting when an inquiry to the resource manager conflicts.

Further, the method in which each functional unit independently scans a port to search for a vacant port is as follows:
There is a problem that the processing takes time, and similarly, it takes unnecessary time.

The present invention recognizes each of a plurality of ports for recognizing that one has been selected, stores the address of the selected functional unit based on the recognition of the recognizing unit, and stores the address of the functional unit having the stored address. By providing an instruction means for instructing to execute only data transfer and newly providing an automatic allocation control circuit for giving priority to a plurality of ports, access to functional units corresponding to the number of ports is automatically and instantly performed. By allocating the use of the shared memory, it is intended to handle the competition of the functional units with respect to the shared memory 1 and prevent the occurrence of unnecessary processing time.

[Means for solving problems]

 FIG. 1 is a block diagram of the principle of the present invention.

It is assumed that the ports 28 to 30 have the same address. Here, for example, when the functional unit 44 sends a command, the address of the functional unit 44, and the address of the port to the common bus 8, the automatic allocation control circuit 31 follows the predetermined priority order, and the recognition means 42 of the ports 28 to 30 Only the port having the highest priority, for example, the port 28, responds to the signal obtained by decoding the command to be transmitted.

Therefore, the recognition means 42 of the port 28 recognizes that it has been selected, and causes the instruction means 43 to store the address of the functional unit 44 which has sent the address to the common bus 8. Here, the instruction means 43 sends to the functional unit 44 an instruction to access the shared memory 1 only to the functional unit 44 which has sent out the stored address.

Then, when the functional unit 45 sends out the command, the address of the functional unit 45, and the address of the port, the automatic allocation control circuit 31
Is a means of recognizing ports 28 to 30 according to a predetermined priority.
Only the port having the highest priority, for example, the port 29, responds to the signal obtained by decoding the command sent by 42.

Therefore, the recognition means 42 of the port 29 recognizes that it has been selected, and causes the instruction means 43 to store the address of the functional unit 45 which has sent the address to the common bus 8. Here, the instruction means 43 sends to the functional unit 45 an instruction to access the shared memory 1 only to the functional unit 45 which has sent out the stored address.

Then, when the functional unit 46 sends out the command, the address of the functional unit 46, and the address of the port, the automatic allocation control circuit 31
Is a means of recognizing ports 28 to 30 according to a predetermined priority.
Only the port of the next priority, which has already responded to the signal obtained by decoding the command sent by 42, for example, the port 30, is responded to.

Therefore, the recognition means 42 of the port 30 recognizes that it has been selected, and causes the instruction means 43 to store the address of the functional unit 46 which has sent the address to the common bus 8. Here, the instruction means 43 sends to the functional unit 46 an instruction to access the shared memory 1 only to the functional unit 46 that has sent out the stored address.

Then, when the functional unit 47 sends a command, the address of the functional unit 47, and the address of the port, the automatic allocation control circuit 31
Does not respond to the signal obtained by decoding the command transmitted by the recognition means 42 of the ports 28 to 30. Since the port 30 has the lowest priority, the recognition means 42 of the port 30 sends a busy signal to the common bus 8.

[Action]

With the above-mentioned configuration, the automatic allocation control circuit 31 sequentially allocates the access from the functional units to the ports 28 to 30 in accordance with the priority order.
Stores the address of the accessed functional unit in the instruction means 43. Therefore, the instructing unit 43 allows the functional unit having the stored address to transfer data to and from the shared memory 1.
It becomes possible to allocate access in order of priority, and since functional units allocate ports, it is possible to prevent a wait time from occurring.

〔Example〕

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

Ports 28, 29 and 30 have the same structure, and show the parts added to FIG. 4 except the decoder 11 and the data buffer 14. As described above, the decoder 11 sends "1" to the AND circuit 35 when the decoded contents become valid.

Since the flip-flop 34 is not set at the initial stage, "1" is sent to the AND circuit 35, and the AND circuit 35 outputs "1".
To the AND circuit 33. Therefore, the AND circuit 33 is a decoder
The "1" sent by 11 is sent to the flip-flop 34, the flip-flop 34 is set, and the automatic allocation control circuit 31
“1” is sent to the AND circuits 40 and 41, and “0” is sent to the AND circuit 35.

Therefore, the AND circuit 33 sends "0" to the flip-flop 34 again, but the flip-flop 34 sends "1" to the AND circuits 40 and 41 until it is reset.

The address register 37 is enabled by the AND circuit 35 sending "1", stores the address of the functional unit that accessed the port 28, and sends it to the comparison circuit 38. The comparison circuit 38 sends out the address of the functional unit to the common bus 8 every time the functional unit requests data transfer.
The address of the functional unit input from the
When it matches the address stored in 37, "1" is sent to the AND circuit 39.

Therefore, the AND circuit 39 sends "1" sent from the decoder 11 to the data buffer 14, enables the data buffer 14, and causes data transfer between the shared memory 1 and the common bus 8.

When the functional unit that has accessed the port 28 and transferred data to the shared memory 1 sends a command for releasing the coupling with the port 28 after the data transfer is completed, the decoder 11 decodes this command.

The comparison circuit 38 compares with the address of the address register 37,
Since they match, the decoder 11 sends "0" to validate the decoded decoupling command of the decoder 11. Therefore, the NOT circuit 36 outputs "1" to the flip-flop 34.
To reset the flip-flop 34,
The flip-flop 34 sends “1” to the AND circuit 35 again.

Further, the address register 37 is reset when the decoder 11 sends out "0", and erases the stored address of the functional unit.

When the decoded contents become valid, the decoders 11 of the ports 29 and 30 other than the port 28 also send "1" to the AND circuits 35 of the ports 29 and 30, respectively, and the flip-flops 34 of the ports 29 and 30.
Each send "1", the AND circuit 35 of port 29
Sends "1" to the AND circuit 40 of the automatic allocation control circuit 31. At this time, the flip-flop 34 of the port 28 has not yet sent "1" to the AND circuit 40 of the automatic allocation control circuit 31. The circuit 40 does not send "1" to the AND circuit 33 of the port 29.

Therefore, the address register 37 of the port 29 is not enabled, and the AND circuit 41 of the automatic allocation control circuit 31 is also
Since "0" is still sent, the address register 37 of the port 30 is not enabled either, and the address of the functional unit that has accessed the port is stored only in the address register 37 of the port 28.

When the port 28 is occupied and there is a functional unit that accesses the port subsequently, even if the decoder 11 of the port 28 decodes and outputs "1", the AND circuit 35 of the port 28 does not Since the flip-flop 34 is sending out "0", the AND circuit 35 of the port 28 remains until it sends out "0".

Therefore, the address register 37 of the port 28 does not store the address of the new functional unit. However, because the AND circuit 40 of the automatic allocation control circuit 31 outputs “1” from the flip-flop 34 of the port 28, the decoder 11 of the port 29
Sends "1" and the AND circuit 35 of the port 29 sends "1", the "1" is sent to the AND circuit 33 of the port 29 and the address register 3
Send to 7. Therefore, the address register 37 of port 29
Is enabled and stores the address of the new functional unit.

At the same time, the flip-flop 34 of the port 29 sends “1” to the AND circuit 41 of the automatic allocation control circuit 31. Therefore, port 3
When the decoder 11 of 0 sends out "1", the flip-flop 34 of the port 30 sends out "1" to the AND circuit 41 as described above.

At this time, the flip-flop 34 of the port 28 also sets "1" to the AND circuit 4
Since it is transmitting to 1, the AND circuit 41 transmits "1". Therefore, the address register 37 of the port 30 is enabled and stores the address of the functional unit that next accessed the port.

Then, the flip-flop 34 of the port 30 sends "1" to the common bus 8 and makes it a busy signal indicating that all of the ports 28 to 30 are in use.

〔The invention's effect〕

As described above, according to the present invention, when a plurality of functional units access a shared memory, the ports are automatically and instantly allocated in the order of access until all the ports are in use. It is possible to prevent the occurrence of the waiting time and improve the processing efficiency of the input / output control device.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a disk controller configured by combining functional units. , FIG. 4 is a block diagram showing an example of a port, FIG. 5 is a block diagram showing an example of a channel adapter and a device adapter, FIG. 6 is a block diagram showing an example of a resource manager, and FIG. It is a block diagram showing an example of a disk control device provided. In the figure, 1 is a shared memory, 2, 26, 27, 28 to 30 are ports, 3 is a resource manager, 4,5 are channel adapters, 6, 7 are device adapters, 8 is a common bus, 9 is a port address, 10 , 38 is a comparison circuit, 11 is a decoder, 12 is a command buffer, 13,37 is an address register, 14 is a data buffer, 15 is a driver, 16 is a receiver, 17 is an interface circuit, 18, 23 is a common bus control circuit, 19 , 22 is a processor, 20,21 is a control memory, 24 is a RAM, 25 is a RAM access control circuit, 31 is an automatic allocation control circuit, 33,35,39,40,41 is an AND circuit, 34 is a flip-flop, and 36 is A NOT circuit, 42 is a recognition means, 43 is an instruction means, and 44 to 47 are data processing modules (functional units).

Claims (1)

[Claims] 1. A plurality of data processing modules (44) to (45) for executing a process of transmitting and receiving data to and from a central processing unit, and a plurality of data processing modules (for executing a process of transmitting and receiving data to and from a data storage device ( 46) to (47), a shared memory (1) for temporarily storing data transferred between the data processing modules (44) to (47), and a shared memory connected to the shared memory (1) A plurality of ports (28) (29) (30) for controlling access, the data processing modules (44) to (47) and the plurality of ports (2
8) A common bus (8) to which (29) and (30) are connected, and controls data transfer between the central processing unit and the plurality of data storage devices according to an instruction from the central processing unit. In the data control device, the same address is given to the plurality of ports (28) (29) (30), and the data processing modules (44) to (44) to (29) are provided in the respective ports (28) (29) (30). When the port (28) (29) (30) is accessed by (47) and its own port has not been selected by the automatic allocation control means (31) described later, the automatic allocation control means (31)
To the automatic allocation control means (31), a recognition means (42) for recognizing that the command has been decoded, the recognition means (42), and the recognition means (42). ) Stores the addresses of the data processing modules (44) to (47) that have accessed the self-port based on the selected recognition, and thereafter, the connection cancellation from the data processing modules (44) to (47) is performed. An instruction means (43) for instructing to execute only data transfer with the data processing modules (44) to (47) having the stored address is provided respectively until a command is received, and the plurality of ports (28 ) (29) (30) multiple ports that can be generated by giving the same address (28) (29)
By the simultaneous detection of the same access by (30), each port (28) (29) responds to the transmission of the decode signal of the command from the recognition means (42) provided in each port (28) (29) (30). A selection is made to give access permission to the shared memory (1) to the port having the next priority already selected in accordance with the priority set in advance in (30), and the plurality of ports (28) (29) ( When there is an access request to the shared memory (1) from (30), the ports (28), (29) and (30) of the next priority that have already been selected are sequentially assigned in the access order and the permission is selected. An automatic allocation control means (31) is provided, and an access request is made to the ports (28) (29) (30) for the plurality of data processing modules (44) to (47) to access the shared memory (1). According to the above priority, Number said port (28) (29) (30)
And assigning an access order to the data processing modules (44) to (47) whose addresses are stored in the shared memory (1) and the instruction means (43) of the port. Characteristic data control device.