JPH07120665B2 - Semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor device capable of reducing the emitter size.

[Conventional technology]

FIG. 3 is a sectional view showing the structure of a conventional HBT having a self-aligned structure using a dummy emitter.

In this figure, 21 is an ohmic contact layer made of n ⁺ -GaAs for ohmic electrode, 22 is a cap layer made of n-GaAs, 23 is an emitter layer made of n-AlGaAs, and 24 is p ⁺ -.
Base layer made of GaAs, 25 is a collector layer made of n ^-- GaAs, 26 is a subcollector layer made of n ⁺ -GaAs, 27 is an emitter electrode, 28 is a base electrode, 29 is the base electrode 28 and the emitter electrode 27. A SiO ₂ film for insulating the base layer 30 is a Be ⁺ implantation region for contacting the base electrode 28 with the base region.

Next, the manufacturing process will be briefly described.

First, on the sub-collector layer 26, the collector layer 25, the base layer 24,
After epitaxially growing the emitter layer 23, the cap layer 22, and the contact layer 21, in order to contact the base electrode 28 with the base region, the contact layer 21 and the cap layer 22 are formed.
Etching is performed.

After that, Be ⁺ ion implantation is performed using the dummy emitter as a mask to form a Be ⁺ implantation region 30 reaching the base layer 24 from the emitter layer 23. As a result, the emitter layer 23 in the Be ⁺ implantation region 30 is inverted into p type.

Then, after forming the SiO ₂ film 29 to Be ⁺ implanted region 30 on, SiO ₂
Emitter electrode 27 and base electrode 28 using film 29 as a mask
To form.

That is, in the conventional HBT manufactured in this way, B
The e ⁺ implantation region 30 is formed in a self-aligned manner, the base resistance value is low, and excellent characteristics are obtained.

[Problems to be solved by the invention]

In the conventional HBT as described above, Be ⁺
When forming the implantation region 30, it is necessary to remove a part of the contact layer 21 and the cap layer 22 by etching,
In wet etching or the like, there is a problem that the emitter size cannot be reduced due to side etching and variations, and the emitter size varies. Further, there is a problem that it is not possible to form a complete planar structure, which is disadvantageous when integrated into an IC.

The present invention has been made to solve the above problems, and it is possible to obtain a semiconductor device which is capable of reducing the size of the emitter and the homojunction capacitance between the emitter and the base, and which is advantageous in forming an IC. With the goal.

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention is directed to a semiconductor layer of a collector region of a first conductivity type, a semiconductor layer of a base region of a second conductivity type formed on a semiconductor layer of the collector region, and a semiconductor layer of the base region. The semiconductor layer of the first conductivity type emitter region formed on the semiconductor layer, the undoped semiconductor layer formed on the semiconductor layer of the emitter region, and a width slightly larger than the width of the emitter region and separated from the emitter region. A first implantation region of the second conductivity type formed from the undoped semiconductor layer to the semiconductor layer of the base region, the base electrode formed on the first implantation region, and the first implantation region separated from each other, A second injection region of the first conductivity type formed from the undoped semiconductor layer which is a region other than the first injection region to the semiconductor layer of the emitter region, and an emitter electrode formed on the second injection region One in which was formed from.

[Action]

In the present invention, the current injected from the semiconductor layer in the base region controls the current flowing between the semiconductor layers in the second injection region and the collector region, but the undoped state existing between the first injection region and the second injection region is controlled. Due to the semiconductor layer, the junction capacitance between the base electrode and the emitter electrode is small.

〔Example〕

FIG. 1 is a sectional view showing the structure of an embodiment of the semiconductor device of the present invention.

In this figure, 1 is a contact layer made of undoped GaAs as an undoped semiconductor layer, 2 is an emitter layer made of n-AlGaAs as a semiconductor layer in the emitter region,
Reference numeral 3 is a base layer made of p ⁺ -GaAs as a semiconductor layer in the base region, 4,5 are collector layers made of n ⁻ -GaAs and sub-collector layers made of n ⁺ -GaAs, respectively, in the collector region. Is an emitter electrode, 7 is a base electrode,
8 is a SiO ₂ film, 9 is a Be ⁺ implantation region as a first implantation region for contacting the base electrode 7 with the base region, 1
0 is a Si ⁺ implantation region as a second implantation region for contacting the emitter electrode 6 with the emitter region, and 11 is Si ₃
It is a sidewall made of N ₄ film.

2 (a) to 2 (c) are views for explaining one embodiment of a manufacturing method for obtaining the semiconductor device of the present invention.

In these figures, the same reference numerals as in FIG. 1 indicate the same parts, and 12 is a resist pattern.

Next, the manufacturing process will be described.

First, a collector layer 4, a base layer 3, an emitter layer 2 and a contact layer 1 are grown on the sub-collector layer 5, and a mask for forming a Be ⁺ implantation region 9 to be formed later on the contact layer 1 is used. Resist pattern 12 by photolithography
To form. After that, using the resist pattern 12 as a mask, Be ⁺ ion implantation is performed so as to sandwich a partial region to form a Be ⁺ implantation region 9 reaching from the contact layer 1 into the base layer 3 (FIG. 2 (a)). .

Next, after using the resist pattern 12 as a mask to form the SiO ₂ film 8 on the Be ⁺ implantation region 9, the resist pattern 12 is removed. After that, after forming a Si ₃ N ₄ film on the SiO ₂ film 8 and the contact layer 1, selective etching of only the Si ₃ N ₄ film is performed to form Si _{3 on} only the inner side wall of the SiO ₂ film 8. A side wall 11 of N ₄ film is formed (FIG. 2 (b)).

Next, Si ⁺ ions are implanted using the SiO ₂ film 8 and the sidewalls 11 as a mask to reach the emitter layer 2 from above the contact layer 1 sandwiched by the Be ⁺ implantation regions 9.
^{The +} implantation region 10 is formed separately from the Be ⁺ implantation region 9. At this time, the contact layer 1 in the Si ⁺ implantation region 10 becomes n ^{+ type} (FIG. 2 (c)).

It should be noted that the implantation of Be ⁺ and Si ⁺ needs to be performed until the contact layer 1 has a high concentration in order to reduce the contact resistance value.

Then, by lamp annealing, the Be ⁺ implantation region 9 and the S
If the i ⁺ implantation region 10 is simultaneously activated and the emitter electrode 6 and the base electrode 7 are formed by the vapor deposition lift-off method,
The HBT with the structure shown in the figure is completed.

That is, in the HBT of the present invention, since the emitter size can be defined by the width of the emitter layer 2 sandwiched by the Be ⁺ implantation regions 9 formed by ion implantation, the emitter size can be easily reduced. Further, since it can be manufactured without adopting the etching process for the contact layer and the like, side etching and variations in the conventional etching process do not pose a problem, and the emitter size can be reduced stably. Further, the homojunction capacitance between the base and emitter can be reduced, and the operating characteristics (especially high speed operation) are improved.

Further, since a complete planar structure can be realized, the surface unevenness is reduced.

Although the GaAs-based HBT is described in the above embodiment,
The present invention can be applied to other semiconductor material-based HBTs, for example, InP-based, and similar effects can be obtained.

Although Si ⁺ and Be ⁺ are used as the dopant, other dopants may be used.

〔The invention's effect〕

As described above, the present invention has the semiconductor layer of the collector region of the first conductivity type, the semiconductor layer of the base region of the second conductivity type formed on the semiconductor layer of the collector region, and the semiconductor layer of the base region. A semiconductor layer of the first conductivity type emitter region formed on the semiconductor substrate, an undoped semiconductor layer formed on the semiconductor layer of the emitter region, and an undoped semiconductor layer slightly wider than the width of the emitter region and separated from the emitter region. The first implantation region of the second conductivity type formed from the semiconductor layer to the semiconductor layer of the base region, the base electrode formed on the first implantation region, and the first implantation region separated from the first implantation region. A first region formed on the undoped semiconductor layer, which is a region other than the region, until reaching the semiconductor layer in the emitter region
Since the second injection region of conductivity type and the emitter electrode formed on the second injection region are formed, the emitter size can be reduced and the homojunction capacitance between the emitter and the base can be reduced, and excellent characteristics can be obtained. In addition to the above, there is an effect that it is advantageous for IC conversion.

[Brief description of drawings]

1 is a sectional view showing the structure of an embodiment of a semiconductor device of the present invention, FIG. 2 is a view for explaining an embodiment of a manufacturing method for obtaining a semiconductor device of the present invention, and FIG. It is sectional drawing which shows the structure of an example of the conventional semiconductor device. In the figure, 1 is a contact layer, 2 is an emitter layer, 3 is a base layer, 4 is a collector layer, 5 is a subcollector layer, 6 is an emitter electrode, 7 is a base electrode, 8 is a SiO ₂ film, and 9 is Be ^+.
Implant region, 10 Si ⁺ implant region, 11 sidewalls, 12
Is a resist pattern. The same reference numerals in each drawing indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A semiconductor layer in a collector region of a first conductivity type,
A semiconductor layer of a second conductivity type base region formed on the semiconductor layer of the collector region; a semiconductor layer of a first conductivity type emitter region formed on the semiconductor layer of the base region; An undoped semiconductor layer formed on the semiconductor layer, and a second conductive layer formed from the undoped semiconductor layer to the semiconductor layer in the base region so as to be slightly wider than the emitter region and spaced from the emitter region. -Shaped first implantation region, a base electrode formed on the first implantation region, and the undoped semiconductor layer that is a region other than the first implantation region and is separated from the first implantation region. A semiconductor device comprising: a second injection region of the first conductivity type formed up to the semiconductor layer of the emitter region; and an emitter electrode formed on the second injection region.