JPH07120664B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a manufacturing method capable of obtaining a semiconductor device capable of reducing an emitter size.

[Conventional technology]

FIG. 3 is a sectional view showing the structure of a conventional HBT having a self-aligned structure using a dummy emitter.

In this figure, 21 is an ohmic contact layer made of n ⁺ -GaAs for ohmic electrode, 22 is a cap layer made of n-GaAs, 23 is an emitter layer made of n-AlGaAs, and 24 is p ⁺ -.
Base layer made of GaAs, 25 is a collector layer made of n ^-- GaAs, 26 is a subcollector layer made of n ⁺ -GaAs, 27 is an emitter electrode, 28 is a base electrode, 29 is the base electrode 28 and the emitter electrode 27. A SiO ₂ film for insulating the base layer 30 is a Be ⁺ implantation region for contacting the base electrode 28 with the base region.

Next, the manufacturing process will be briefly described.

First, on the sub-collector layer 26, the collector layer 25, the base layer 24,
After epitaxially growing the emitter layer 23, the cap layer 22, and the contact layer 21, in order to contact the base electrode 28 with the base region, the contact layer 21 and the cap layer 22 are formed.
Etching is performed.

After that, Be ⁺ ion implantation is performed using the dummy emitter as a mask to form a Be ⁺ implantation region 30 reaching the base layer 24 from the emitter layer 23. As a result, the emitter layer 23 in the Be ⁺ implantation region 30 is inverted into p type.

Then, after forming the SiO ₂ film 29 to Be ⁺ implanted region 30 on, SiO ₂
Emitter electrode 27 and base electrode 28 using film 29 as a mask
To form.

That is, in the conventional HBT manufactured in this way, B
The e ⁺ implantation region 30 is formed in a self-aligned manner, the base resistance value is low, and excellent characteristics are obtained.

[Problems to be solved by the invention]

In the conventional HBT as described above, Be ⁺
When forming the implantation region 30, it is necessary to remove a part of the contact layer 21 and the cap layer 22 by etching,
In wet etching or the like, there is a problem that the emitter size cannot be reduced due to side etching and variations, and the emitter size varies. In addition, there is also a problem that it is not possible to form a complete planar structure, which is a disadvantage in forming an IC.

The present invention has been made to solve the above problems, and it is possible to obtain a semiconductor device which is capable of reducing the size of the emitter and the homojunction capacitance between the emitter and the base, and which is advantageous in forming an IC. With the goal.

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention comprises a collector layer, a base layer, an emitter layer and a contact layer, which are formed in this order, a resist pattern is then formed on the contact layer, and the resist pattern is used as a mask by ion implantation. Forming a first implantation region of the second conductivity type reaching the base layer from the contact layer except the undoped region, and then forming an oxide film on the first implantation region using the resist pattern as a mask. Then, the resist pattern is removed from the oxide film, then a film is formed on the oxide film and the contact layer, and then only this film is selectively etched to remove only the side wall portion inside the oxide film after the resist pattern is removed. A sidewall is formed on the first implant region to form an undoped region between the extrinsic base region of the first implant region and the emitter region of the second implant region. Using the sidewall and the oxide film as a mask, a second conductivity type second implantation region reaching the base layer from above the contact layer by ion implantation from above the semiconductor layer in the undoped region surrounded by the first implantation region, It is formed so as to be separated from the first implantation region, and then a base electrode is formed on the first implantation region and an emitter electrode is formed on the second implantation region.

[Action]

In the present invention, the current injected from the semiconductor layer in the base region controls the current flowing between the semiconductor layers in the second injection region and the collector region, but the undoped state existing between the first injection region and the second injection region is controlled. Due to the semiconductor layer and the undoped emitter layer, the junction capacitance between the base electrode and the emitter electrode is small.

〔Example〕

FIG. 1 is a sectional view showing the structure of an embodiment of the semiconductor device of the present invention.

In this figure, 1 is a contact layer made of undoped GaAs as an undoped semiconductor layer, 2 is an emitter layer made of undoped AlGaAs as a semiconductor layer in the emitter region, and 3 is p ⁺ -GaAs as a semiconductor layer in the base region. base layer made of, 4 and 5 n as a semiconductor layer of each collector region ^- collector layer made of -GaAs and n ⁺ -GaAs
A sub-collector layer consisting of, 6 is an emitter electrode, 7 is a base electrode, 8 is a SiO ₂ film, 9 is a Be ⁺ implantation region as a first implantation region for contacting the base electrode 7 with the base region, and 10 is an emitter. A region 11 is a Si ⁺ implantation region as a second implantation region for contacting the emitter electrode 6 with the region, and 11 is a sidewall made of a Si ₃ N ₄ film.

2 (a) to 2 (c) are views for explaining one embodiment of a manufacturing method for obtaining the semiconductor device of the present invention.

In these figures, the same reference numerals as in FIG. 1 indicate the same parts, and 12 is a resist pattern.

Next, the manufacturing process will be described.

First, a collector layer 4, a base layer 3, an emitter layer 2 and a contact layer 1 are grown on the sub-collector layer 5, and a mask for forming a Be ⁺ implantation region 9 to be formed later on the contact layer 1 is used. Resist pattern 12 by photolithography
To form. After that, using the resist pattern 12 as a mask, Be ⁺ ion implantation is performed so as to sandwich a partial region to form a Be ⁺ implantation region 9 reaching from the contact layer 1 into the base layer 3 (FIG. 2 (a)). .

Next, after using the resist pattern 12 as a mask to form the SiO ₂ film 8 on the Be ⁺ implantation region 9, the resist pattern 12 is removed. After that, after forming a Si ₃ N ₄ film on the SiO ₂ film 8 and the contact layer 1, selective etching of only the Si ₃ N ₄ film is performed to form Si _{3 on} only the inner side wall of the SiO ₂ film 8. A side wall 11 of N ₄ film is formed (FIG. 2 (b)).

Next, the SiO ₂ film 8 and the side walls 11 as a mask, ion implantation is performed of Si ^+, reaching from the upper contact layer 1 sandwiched by Be ⁺ implanted region 9 in the base layer 3 Si ⁺
The implantation region 10 is formed separately from the Be ⁺ implantation region 9. At this time, the conductivity types of the contact layer 1 and the emitter layer 2 in the Si ⁺ implantation region 10 are n ^{+ type} and n type, respectively. Further, Si ⁺ passes through the base layer 3 and reaches the collector layer 4, but since the base layer 3 has a high concentration, it can maintain the p ^{+ type} (second
Figure (c)).

It should be noted that the implantation of Be ⁺ and Si ⁺ needs to be performed until the contact layer 1 has a high concentration in order to reduce the contact resistance value.

Then, by lamp annealing, the Be ⁺ implantation region 9 and the S
If the i ⁺ implantation region 10 is simultaneously activated and the emitter electrode 6 and the base electrode 7 are formed by the vapor deposition lift-off method,
The HBT with the structure shown in the figure is completed.

That is, in the HBT of the present invention, since the emitter size can be defined by the width of the Si ⁺ implantation region 10 formed by ion implantation, the emitter size can be easily reduced. Further, since it can be manufactured without adopting the etching process for the contact layer and the like, side etching and variations in the conventional etching process do not pose a problem, and the emitter size can be reduced stably. Further, the homojunction capacitance between the base and the emitter can be reduced, and the operating characteristics (especially high speed operation) are improved.

Further, since a complete planar structure can be realized, the surface unevenness is reduced.

Although the GaAs-based HBT is described in the above embodiment,
The present invention can be applied to other semiconductor material-based HBTs, for example, InP-based, and similar effects can be obtained.

Although Si ⁺ and Be ⁺ are used as the dopant, other dopants may be used.

〔The invention's effect〕

As described above, the present invention forms the collector layer, the base layer, the emitter layer, and the contact layer in this order,
Next, a resist pattern is formed on the contact layer,
Ion implantation using the resist pattern as a mask
After forming the first implantation region of the second conductivity type that extends from the contact layer into the base layer except the undoped region, and then form an oxide film on the first implantation region using the resist pattern as a mask. An undoped region is formed between the extrinsic base region of the first implantation region and the emitter region of the second implantation region by removing the resist pattern and then forming a film on the oxide film and the contact layer, and then, By selectively etching only this film, a sidewall is formed only on the inner side wall of the oxide film after the resist pattern is removed, and then the first implantation region is formed using this sidewall and the oxide film as a mask. A second implantation region of the first conductivity type that reaches the base layer from above the contact layer is separated from the first implantation region by ion implantation from above the semiconductor layer in the undoped region surrounded by Then, the base electrode is formed on the first implantation region and the emitter electrode is formed on the second implantation region, so that the emitter size can be reduced and the homo capacitance between the emitter and the base can be reduced. It becomes possible to realize a semiconductor device capable of reducing resistance.

[Brief description of drawings]

1 is a sectional view showing the structure of an embodiment of a semiconductor device of the present invention, FIG. 2 is a view for explaining an embodiment of a manufacturing method for obtaining a semiconductor device of the present invention, and FIG. It is sectional drawing which shows the structure of an example of the conventional semiconductor device. In the figure, 1 is a contact layer, 2 is an emitter layer, 3 is a base layer, 4 is a collector layer, 5 is a subcollector layer, 6 is an emitter electrode, 7 is a base electrode, 8 is a SiO ₂ film, and 9 is Be ^+.
Implant region, 10 Si ⁺ implant region, 11 sidewalls, 12
Is a resist pattern. The same reference numerals in each drawing indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A collector layer, a base layer, an emitter layer, and a contact layer are formed in this order, a resist pattern is then formed on the contact layer, and the resist pattern is used as a mask to perform ion implantation to form an undoped region. Except for forming a first implantation region of the second conductivity type that extends from the contact layer into the base layer, and then forms an oxide film on the first implantation region using the resist pattern as a mask. The resist pattern is removed from the above, then a film is formed on the oxide film and the contact layer, and then selective etching of only this film is performed to remove the inside of the oxide film after the resist pattern is removed. A sidewall is formed only on the sidewall portion, and then the undoped region surrounded by the first implantation region is formed using the sidewall and the oxide film as a mask. By implanting ions from above the semiconductor layer, the second implantation region of the first conductivity type that reaches the base layer from above the contact layer is formed separately from the first implantation region. An undoped region is formed between the external base region and the emitter region of the second implantation region, and then a base electrode is formed on the first implantation region and an emitter electrode is formed on the second implantation region. Device manufacturing method.