JPH07120722B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention is directed to a static random access memory (RAM) and an electrically rewritable nonvolatile memory (EEPRO).
M) in combination with a semiconductor memory device,
In particular, it is used as a static RAM that can hold memory semipermanently even without a power supply.

(Prior Art) In general, static RAM destroys stored data when the power is turned off. Therefore, if it is desired to retain the previous data, another backup power supply is used.

(Problems to be solved by the invention) In this case, since a separate backup power supply is required, in order to hold the stored data semipermanently even if there is no power supply, when considering the combination of static RAM and EEPROM, simply RAM Just adding EEPROM to requires an EEPROM with the same storage capacity as this, apart from RAM. Therefore, the size of the device using these memories as a component is correspondingly increased, and the manufacturing cost is also increased.

Therefore, an object of the present invention is to provide a semiconductor memory device which can be configured as a static RAM having the function of an EEPROM and which can hold stored data semipermanently even without a power supply.

(Means and Actions for Solving the Problem) The present invention provides a flip-flop circuit having a pair of load resistors and a pair of driver transistors, and a load resistor provided on each of the pair of load resistors through a tunnel insulating film. By applying a potential higher than the power supply to the pair of floating gates that change the value of the voltage by electric charge and the power supply terminal of the flip-flop circuit, the electric field strength generated by the potential difference between the data holding node and the electrode terminal of the flip-flop circuit is adjusted. And means for writing data by injecting charge into one of the pair of floating gates through a tunnel insulating film, and when charge is stored in the other of the pair of floating gates, When writing data, the other side of the floating gate A semiconductor memory device is characterized in that an electric field generated by a potential difference from a holding node discharges charges through a tunnel insulating film.

That is, the present invention has a form in which a floating gate is added to a resistance load type static RAM cell using a polysilicon high resistance element as a load, and the floating gate acts as a gate electrode of a MOSFET to obtain a load resistance value. Is changed so that the previous data is automatically obtained at each storage node of the flip-flop when the flip-flop is powered on.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. A circuit diagram of a normal resistance load type static RAM cell is shown in FIG. In this figure, 1a and 1b are load elements, 2a and 2b are driver transistors, A and B are data holding nodes, and these constitute a flip-flop. 2c and 2d are transfer elements for data transfer. In FIG. 4, when the data is held, one of the two data holding nodes A and B has a potential close to the power supply Vdd, and the other has a ground potential.

FIG. 5 shows a pattern plan view of a normal resistance load type static RAM cell using polysilicon high resistance elements for the load elements 1a and 1b, which is applied to the present invention. In this figure, the region 3 (including the diffusion layer regions 3a, 3a ', 3b and 3b') is an element region, and the other region F is an element isolation region.
Regions 4, 4a and 4b represent the first polysilicon electrodes. Area 5
(Including regions 5a, 5b and 5c) shows the second polysilicon film. Part of area 5 indicated by dotted diagonal lines (5a, 5b and 5c)
Is a region heavily doped with impurities and serves as a wiring, and the other part is a region not doped with impurities (or is lightly doped) and serves as a high resistance element. 6a and 6b are contacts that connect the first polysilicon electrode and the diffusion layer region, and 7a and 7b are contacts that connect the second polysilicon film and the first polysilicon electrode.

Corresponding to the circuit diagram shown in FIG. 4, for example, the transistor 2a is configured with the diffusion layer 3a as the source, 3a 'as the drain, and the first polysilicon electrode 4a as the gate. The data holding node A has a diffusion layer 3a 'and a first polysilicon electrode 4b.
And a second polysilicon electrode 5a. here,
The diffusion layer 3a 'and the electrode 4b are connected by a contact 6a, and the electrodes 4b and 5a are connected by a contact 7a. Transistor 2b
Is constituted by using the diffusion layer 3b as a source, 3b 'as a drain, and the electrode 4b as a gate. The data holding node B is composed of a diffusion layer 3b 'and electrodes 4a and 5b, which is symmetrical to A. The electrode 4 serves as a gate electrode of the transfer MOS elements 2c and 2d, and the wiring 5c is a portion connecting the resistors 1a and 1b.

FIG. 1 shows a cell of an embodiment of the present invention corresponding to FIG. This is obtained by adding tunnel insulating film regions 8a and 8b and floating gates 9a and 9b to the static RAM cell shown in FIG. A sectional view of the portion indicated by the line CC in FIG. 1 is shown in FIG.
The portion of a and the floating gate 9a also corresponds to FIG. In FIG. 2, the polysilicon film 1a (5) is, for example, a thin N-type (high resistance) layer having a very high impurity concentration. Further, 8 and 11 are insulating films, and 10 is a silicon substrate. Polysilicon film 1a, 5b, 5c, insulating film 8, floating gate 9b
The portion can be considered as a kind of MOSFET, and the resistance value of the polysilicon resistance film 1b can be increased or decreased depending on whether or not electrons are injected into the floating gate 9b. The same applies to the resistance film 1b.

The electrical operation will be described below with reference to FIGS. 1 and 2.
First, consider the case where the data holding node A is at the power supply Vdd potential. In this case, the data holding node B is at the ground potential. Therefore, the first polysilicon electrode 4a and the second polysilicon electrode 4a
The polysilicon electrode 5b is at ground potential. The power supply potential Vdd is applied to the second polysilicon electrode 5c. In this state, no electric charge is stored in the floating gate 9b. Now, when an appropriate potential higher than Vdd is applied to the electrode 5c, electrons are injected from the electrode 4a through the tunnel insulating film 8b, and the floating gate 9b is negatively charged. When this positive potential is applied to the electrode 5c, the electric field applied to the other tunnel insulating film 8a is small and electron injection does not occur. This is because the first polysilicon electrode 4b (that is, the node A) is at the Vdd potential, and the potential difference between both sides of the tunnel insulating film 8a is small. In this way, a potential at which a tunnel current flows in one tunnel insulating film and does not flow in the other tunnel insulating film is the "potential higher than the appropriate power supply Vdd". Based on the above principle, 1-bit information can be stored depending on which floating gate is charged.

Now, this information is read as follows. That is,
The power is turned off once to bring the nodes A and B into a state where no electric charge is stored (ground potential). Then, when the power is turned on, the conductance of the high resistance element differs depending on whether or not negative charges are stored in the floating gate below. Potential of the node rises faster than the potential of the other node. The node (A or B) whose potential rises faster becomes data "1", which means that information has been read. In the above read operation, the high resistance element is operated as a P-channel MOSFET. Therefore, the second polysilicon electrode 5c serving as the source electrode is P
It is desirable that the mold be doped.

When the write / read operation is performed (once), the data is inverted. The above write operation is the first write after the memory device is manufactured, and after the second time, if the opposite data is previously written, the same amount of negative charge is stored in both floating gates. And information is lost. Therefore, it is impossible to rewrite as it is. However, after injecting electrons into the required floating gate by the above method, the charge stored in the floating gate on the opposite side can be discharged.

This charge discharging method will be described with reference to FIG.

FIG. 3 shows a pair of floating gates 9a and 9b in the cell.
And their upper and lower electrodes are schematically shown. Now
The floating gate 9b has already been negatively charged by the above method (applying a potential higher than Vdd to the electrode 5).
Consider the state where Q is stored and the previously injected charge remains in the floating gate 9a. When an appropriate negative potential is applied to the electrode 5 in this state, a high electric field is applied to the tunnel insulating film 8a, a tunnel current flows, and negative charges (electrons) stored in the floating gate 9a are emitted. Such a high electric field is not applied to the film 8b, and the negative charge -Q of the floating gate 9b is stored.
At this time, the potential Vdd of the first polysilicon electrode 4b is maintained by the electric charge stored in the electrostatic capacitance attached to the data holding node A. Therefore, as the negative charges (electrons) of the floating gate 9a are discharged to the electrode 4b through the tunnel insulating film 8a, the potential of the electrode 4b decreases, but the positive charge stored in the data holding node is larger than Q. A sufficient amount of negative charges can be discharged from the floating gate 9b. In this way, rewriting is possible.

Next, a method of forming a main part of the storage device will be described. The first polysilicon electrode is formed by the conventional resistance load type static RAM (E / R SRAM) process technology using a polysilicon high resistance element as a load element. Next, an SiO ₂ film is deposited by, for example, 3000 Å by the CVD method, and holes having a pattern for the tunnel insulating films 8a and 8b shown in FIG. 1 are formed in the SiO ₂ film by using the photolithography technique. Next, for example, 50 Å is oxidized. As a result, the tunnel insulating film is formed. Next, a polysilicon film, for example, 700 Å is deposited, and the photolithography technique is used to leave the polysilicon film having the pattern to be the floating gates 9a and 9b in FIG. Next, the surface of the floating gate is oxidized by 205Å, for example. After that, the steps after the formation of the high resistance element are performed again by the conventional E / R type SRAM process technology.

[Effects of the Invention] As described above, according to the present invention, since the floating gate having the tunnel insulating film interposed is sandwiched between the electrode layer and the resistance layer, the conventional E / R static RAM is used.
A cell with the same area as the cell, and EEP for static RAM function
It is possible to realize a semiconductor memory device having a cell to which a ROM function is added.

[Brief description of drawings]

FIG. 1 is a pattern plan view showing an embodiment of the present invention, and FIG.
1 is a sectional view taken along the line CC of FIG. 1, FIG. 3 is a sectional structural view for explaining the operation of FIG. 1, FIG. 4 is a circuit diagram of a conventional static RAM cell, and FIG. 5 is the same. It is a pattern top view of a cell. 1a, 1b ... load element, 2a, 2b ... driver-transistor, 3 (including 3a, 3a ', 3b and 3b') ... element area, 3a, 3
a ', 3b, 3b' ... diffusion layer region, 4,4a, 4b ... first polysilicon electrode, 5 (including 5a, 5b and 5c) ... second polysilicon film, 5a, 5b, 5c ... ... Highly doped portion of the second polysilicon film, 6a, 6b ... Contacts connecting the first polysilicon electrode and the diffusion layer region, 7a, 7b ... Second polysilicon film and first polysilicon film Contact for connecting silicon electrode, 8 ... Insulating film, 8a, 8b ... Tunnel insulating film, 9
a, 9b: Floating gate, 10: Silicon substrate.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/105 29/788 29/792 G11C 17/00 307 D

Claims (3)

[Claims] 1. A flip-flop circuit having a pair of load resistors and a pair of driver transistors, and a pair of floating gates provided on the pair of load resistors respectively through a tunnel insulating film to change the value of the load resistor by electric charge. And a potential higher than that of a power source is applied to the power supply terminal of the flip-flop circuit, whereby one of the pair of floating gates is applied to one of the pair of floating gates according to the electric field strength generated by the potential difference between the data holding node of the flip-flop circuit and the power supply terminal. Means for writing data by injecting charges through the tunnel insulating film, and when charges are stored in the other of the pair of floating gates, the other of the floating gates is used when writing data by the means. Caused by the potential difference between the The semiconductor memory device, characterized in that to release the charges through the tunnel insulating film by field. 2. The tunnel insulating film is an insulating film for injecting charges into one of the pair of floating gates and discharging the charges from the other of the pair of floating gates by causing a tunnel current to flow therethrough. The semiconductor memory device according to claim 1, wherein: 3. The semiconductor memory device according to claim 1, wherein each of the pair of load resistors is made of high-resistance polysilicon and faces the pair of floating gates with the tunnel insulating film interposed therebetween.