JPH07120952B2 - CMI decoding circuit - Google Patents

Description

The present invention relates to a CMI decoding circuit for decoding a CMI code into an NRZ code.

[Conventional technology]

Generally, the CMI code is known as a self-timing system code that obtains a timing wave from a received CMI code sequence as a method of extracting timing information. Conventionally, this type of CMI decoding circuit performs timing extraction from the rising or falling information of a code with a CMI code rate of 2f _C , and when the data rate of the NRZ code is f _C , the rate synchronized with the CMI code is used. With the clock of f _C and its two inverted clocks
A method of dividing the CMI code into two sequences and decoding is used.

[Problems to be Solved by the Invention]

In the above-mentioned conventional CMI decoding circuit, when the received CMI code is identified and reproduced, it is necessary to perform identification and reproduction in two sequences with clocks of two phases of 1/2 of the CMI code rate. Separation of the decoding circuit is difficult, and there is a problem that a reception and identification reproduction circuit dedicated to CMI code is required.

An object of the present invention is to provide a CMI decoding circuit which enables decoding with a single clock and realizes simplification of the circuit.

[Means for Solving the Problems]

In the CMI decoding circuit of the present invention, the CMI coding rule is “0” of NRZ code.
To replace "10" with "10", and to replace "01" with "01", a means for detecting "10" from the CMI code, and CM
Based on the means for dividing the clock signal of the I code rate by 1/2, the means for outputting the divided clock and its inverted clock, and the signal of "01" or "10" detected by the detecting means. To output the respective pulses and to count the number of these output pulses, and compare the counted number of pulses to determine the decoding phase of the CMI code, and determine the phase of the divided clock according to the determined phase. And means for selecting, and synchronizing with the divided clock of this selected phase
The CMI code is used for decoding.

[Action]

In the above configuration, the CMI depends on the selected divided clock.
The code can be decoded, and decoding is possible with a single clock, which is the same speed as the CMI code speed.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In addition,
In this embodiment, for simplification, the CMI coding rule shows an example in which "0" of the NRZ code is converted to "01".

The CMI code input to the CMI code input terminal 1 is read into the flip-flops 3 and 4 by the 2f _C clock input to the 2f _C clock input terminal 2, respectively. Then, the Q output of the flip-flop 4 that has read the previous data (data having the same polarity as the read data) and the output of the flip-flop 3 that has read the subsequent data (the inverted output of the read data)
To the AND circuits 7 and 8, respectively.

The Q outputs of the flip-flops 3 and 4 are input to the exclusive OR circuit 9, and the output of the exclusive OR circuit 9 is read into the flip-flop 12. The flip-flop 12 operates with the output of the selector 10 described later as a clock and outputs the NRZ code to the NRZ output terminal 13.

On the other hand, to the AND circuits 7 and 8, clocks obtained by inverting the 2f _C clock by the inverting circuit 5 are input, respectively, and used as RZ pulses for removing glitches and the like. Further, the 2f _C clock is divided by the 1/2 divider circuit 6, one positive clock is input to the AND circuit 7, and its inverted clock is input to the AND circuit 8. The positive and negative f _C clocks are also input to the selector 10, which will be described later.

Further, the outputs of the AND circuits 7 and 8 are input to the pulse number detection circuit 11, where the side that outputs a large number of pulses is determined. The output of this determination result is input to the selector 10, which selects the 1/2 frequency-divided f _C clock input to this selector 10 to select the flip-flop 12 and the clock output terminal 14.
To output.

According to the above configuration, the signals a to g in each unit are shown in FIG.
As shown, the input CMI code a is read into the flip-flops 3 and 4 at the 2f _C clock b, and the outputs of the flip-flop 3 and the Q output of the flip-flop 4 are output to the AND circuits 7 and 8, respectively. Then, the AND circuits 7 and 8 pass the outputs from the flip-flops 3 and 4 at the timing of the positive polarity f _C clock e and the inverted f _C clock f, and output a pulse when "10" is detected. c is a pulse output from the AND circuit 8. This pulse is detected by the pulse number detection circuit 11, and the side from which many pulses are output is determined. Then, based on this judgment output, the selector 10 selects the f _C clock of the phase on the side with the larger number of pulses, and this is selected.
The flip-flop 12 is operated by the f _C clock.
As a result, the output d of the exclusive OR circuit 9 is the NRZ code g.
Will be output as.

Therefore, in this circuit, CMI decoding can be realized with only 2f _C clock, and the reception identification reproduction circuit and the like are unnecessary.

When converting "0" of the NRZ code to "10", the pulse number detection circuit 11 is configured so that the selector 10 selects the phase on the side where "01" is detected.

Further, the pulse number detection circuit 11 can be implemented by a competitive counter or a circuit that detects the side on which a large number of pulses are output by an analog integration circuit or the like in consideration of CMI code violation.

〔The invention's effect〕

As described above, the present invention detects the CMI code, selects the phase of the divided clock, and decodes the CMI code with this selected divided clock. Since the decoding can be performed with a single clock, there is an effect that the circuit can be simplified without requiring a special reception code identification and reproduction circuit. Further, the present invention determines the decoding phase of the CMI code by counting the number of pulses obtained by detecting “01” and “10” and then comparing them, so that there is a violation of the CMI code rule. Even if a sub-signal is multiplexed, even if a CMI code error occurs, the number of bits for pulse count judgment in the selection means can be increased to achieve the CMI phase synchronization and error detection. To be

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
It is a wave form diagram of each signal of a-g of the figure. 1 …… CMI code input end, 2 …… 2f _C clock input end, 3,4
...... Flip-flops, 5 ... Inversion circuits, 6 ... 1/2 divider circuits, 7,8 ... AND circuits, 9 ... Exclusive OR circuits, 10 ... Selectors, 11 ... Pulse number detection circuit , 12 ……
Flip-flop, 13 …… NRZ output, 13 …… f _C clock output.

Claims (1)

[Claims] 1. A means for detecting "01" from a CMI code when the CMI coding rule converts "0" of an NRZ code into "10", and when converting this into "01". And a means for dividing the clock signal of the CMI code rate into 1/2, a means for outputting the divided clock and its inverted clock, and a "01" or "10" signal detected by the detecting means. And a means for outputting each pulse based on the above, and counting the number of these output pulses, and comparing the counted number of pulses.
And a means for determining the decoding phase of the CMI code and selecting the phase of the divided clock according to the judged phase, and configured to decode the CMI code in synchronization with the divided clock of this selected phase. A CMI decoding circuit characterized by the above.