JPH07121109B2 - Image signal quantizer - Google Patents

Description

TECHNICAL FIELD The present invention relates to an analog-digital (hereinafter referred to as AD) conversion circuit of a television camera.

(Prior art and its problems) With the recent progress of digital signal processing technology, many image processing devices have been digitized with the aim of improving performance, function, and cost. Television cameras are also considered to have many merits by digitizing the signal processing circuit.

However, it is said that about 8 bits are sufficient for digitizing analog signals in ordinary video equipment, whereas cameras are required to have higher precision. To explain the reason, firstly, in the camera, in order to correct the non-linearity of the photoelectric conversion characteristic of the cathode ray tube, a process called gamma correction for increasing the gain of the low signal level part and compressing the high signal level in reverse is performed. . The input / output characteristics of the standard camera gamma correction circuit are as shown in FIG. 4, and as shown in FIG. 2, the video signal is digitized as shown in FIG. Then, the digital output after gamma correction with respect to the analog input before gamma correction is as shown in (B). It is clear that the former has a larger quantization error Δx when compared with the digitalized version (C) after gamma correction in analog.
In order to suppress this increase, it is necessary to increase the original quantization accuracy by about 2 bits.

In addition, as shown in Fig. 4, the normal camera performs an operation called white compression, without clipping the input signal from the rated (100%) level to the rated 400% level.
Push the output signal to the rated 100% to 110% level. Therefore, it is also necessary to keep the dynamic range of the signal sufficiently wide before performing these nonlinear processes. In other words, it is said that the camera needs to quantize a wide range of analog signals with high accuracy, and that an A-D conversion circuit of about 12 bits is usually required. However, it is very difficult to obtain an A / D converter with such a high bit number that works at a speed that can actually handle video signals (a sampling speed of 10 MHz or higher is required). It was a big obstacle to digitization.

(Object) An object of the present invention is to realize an A-D converter circuit having a wide dynamic range and effectively high quantum accuracy by using an A-D converter having a small number of bits and obtaining a linear output.

(Embodiment) FIG. 3 shows a block diagram of a color television camera in which a signal processing circuit is digitized. The video signal current 2 photoelectrically converted by the image pickup device 1 is converted into a voltage by the preamplifier 3. After the output 4 is converted into a digital signal by the A / D conversion circuit 5, the linear signal processing circuit 6 performs shading, flare correction, masking correction (hue correction), etc., and then the process circuit 7 performs the gamma correction described above. ，
Performs non-linear processing such as white compression. The signal 8 subjected to the correction is the other channel signal subjected to the same processing.
It is sent to the encoder circuit 9 together with 10, 11 and becomes a composite television signal 12.

As described above, since the camera performs linear signal processing in the preceding circuit, the output signal of the AD conversion circuit needs to be linear. However, as shown in FIG. Since the gain of is greatly compressed in the circuit in the subsequent stage, it is meaningless to quantize this part with the same accuracy as the low-level part.

The present invention realizes an A-D conversion circuit that is linear and has a variable quantization precision in consideration of the characteristics of the camera.

FIG. 1 shows a first embodiment of the present invention. The present invention is a non-linear quantization circuit 20, a level determination circuit 22, a bit shift circuit 24,
It is composed of a constant generation circuit 25 and a subtraction circuit 28.

The operation of the present invention will be described below. The analog signal 19 is linearly quantized by the non-linear quantization circuit 20 as in the example shown in FIG. In this figure, the horizontal axis is the analog input signal level, the vertical axis is the output digital signal in an analog image,
Both are described on a linear scale. (This specific method will be described later). At this time, the slope of the quantization (precision)
Is the digital output Ad, Bd,
The lower bits of ...... are 00 ... 0 (0010 ... 0,0100 ...
0,1010 ... 0, etc). In each section (hereinafter, analog input signal level 0 to Aa is section A, Aa to Ba is section B
It is called a section .... ), The quantization accuracy in …… is converted into decimal numbers, and 2 ⁿ¹ , 2 ⁿ² …… (n ₁ , n ₂ ……
Is an integer). (In the example of FIG. 6, A, B
Let each point be Ad ＝ 001 …… 0, Bd ＝ 010 …… 0, and n ₁
= −1, n ₂ = −2. ) Next, the level of the output 21 of the non-linear quantization circuit 20 is read by the determination circuit 22 to determine in which section the main quantization is performed (in the example of FIG. If bit is 00, it is A section, if 01, it is B section, and if it is 10 or 11, it is C section
It can be judged as a section. ), And instructs the bit shift circuit 24 and the binary constant generation circuit 25.

The bit shift circuit 24 and the binary constant generating circuit 25 perform the following operations based on this instruction.

i) In the case of A section instruction: Bit shift circuit 24 ... Outputs the input as it is.

Binary constant generator 25 …… 00… 0 is output.

ii) In the case of B section designation: Bit shift circuit 24 ... Input is arithmetically shifted to -n ₁ and bit left. (Shifted to the left by one bit in the example of FIG. 6) Binary constant generation circuit 25 ... Output. (In the example of FIG. 6, 0010 ... 0 is output).

iii) In the case of C section instruction: Bit shift circuit 24 ... Input is arithmetically shifted to the left by -n ₂ bits. (In the example of FIG. 6, it shifts to the left by 2 bits.) Binary constant generator 25 ... Output.

(1010 ... 0 is output in the example of FIG. 6).

iv) In the case of D section instruction: Bit shift circuit 24 ... Input is arithmetically shifted to the left by -n ₃ bits.

Binary constant generator 25 …… Output.

The same applies when there is an E section or less.

In this way, the subtraction circuit 28 outputs the output of the bit shift circuit 24.
If the output 27 of the binary constant generating circuit 25 is subtracted from 26, the output 29
As shown in FIG. 7, it is possible to obtain a linear digital output, although the quantization accuracy decreases as the analog input signal level increases.

FIG. 5 shows a second embodiment of the present invention. In this example, the output 21 of the nonlinear quantizer 20 is paralleled, i) the input is arithmetically shifted to the −n _1- bit expression, and Arithmetic circuit 30, ii) input arithmetically Shift left a bit Operation circuit 31, iii) The input is shifted left by -n ₃ bits. In addition to the operation circuit 32 for subtracting, the output 21 that does not perform any processing is selected by the circuit 33 that selects based on the instruction of the level determination circuit 22, and the form is different. However, the basic operation is exactly the same as that of the first embodiment, and the effect is also the same.

In the above description, the points A, B ... Are assumed to have the lower bits of the digital outputs Ad, Bd ... 0 .. 0, but in reality it is not possible to set them to other points. However, if the lower bits are 0 ... 0, the level judgment circuit and the constant generation circuit need only handle the upper few bits, and the circuit is greatly simplified.

Next, the non-linear quantization circuit 20 will be specifically described. The linear quantization as used in the present invention can be easily realized by the following method.

1) Reference resistance operation method As shown in FIG. 8, the parallel comparison type A / D converter has 2 ^m −1 (m is the number of bits) comparators 40, and the analog input signal 41 and positive / negative Resistor reference voltage V _RH , V _RL
Quantization is performed by comparing each of the voltages obtained by voltage division at 44 and the m-bit signal encoded by the encoder 42. Therefore, as shown by the dotted line in the figure, the intermediate point 45 of the resistor 44 connected in series (the usual parallel comparison type AD converter often has an intermediate tap terminal from such a point). .) And a negative reference voltage V _RL in parallel with a resistor 46 to perform broken line quantization. It should be noted that the resistance value Rx of the resistor 46 may be selected such that the potential at the midpoint is the positive reference voltage-the midpoint voltage: the midpoint voltage-the negative reference voltage = 1: 2 ⁿ (n: integer, n ≠ 1). .

2) A / D converter serial use As shown in FIG. 9, two m-bit A / D converters 50 and 51 are used.
Broken line quantization is also possible by connecting and using in series. In this case, the negative reference voltage terminal 53 of the first A-D converter 50 and the positive reference voltage terminal 54 of the second A-D converter 51 are connected, and the common reference voltage Ec is added thereto. In addition, the positive reference voltage terminal of the AD converter 50
A positive reference voltage E _H is applied to 52, and a negative reference voltage E _L is applied to the negative reference voltage terminal 55 of the A / D converter 51.
In this way, the analog input signal 56 is added in parallel to the analog signal input terminals 60 and 61 of both AD converters 50 and 51, and the reference voltages E _H , E _C , and E _L are set to E _H −E _C : E ^{_{C -E L = 1: 2 n}} : coding (n integer, n ≠ 1) and so as to select the m-bit digital output 62, 63 of both the a-D converter 50 and 51 to m + 1-bit signal at the encoder 64 If this is done, polygonal line quantization becomes possible as in 1).

The same can be achieved by setting n to 1 and making the number of bits of the two AD converters different from each other.

3) Analog signal non-linear system As shown in Fig. 10, the output 72 of the analog amplifier 71 is resistor
In addition to the circuit consisting of R ₁ , R ₂ , diode 73, and constant voltage source 74 connected in series, output 75 from the connection point of resistors R ₁ and R _2.
When the output 75 is taken out, the gain of this output 75 is determined by the DC voltage level of the analog input signal 70 being V _EE + V
It falls to R ₂ / R ₁ + R ₂ from the point where it exceeds _DS (V _EE : output voltage of constant voltage source 74, V _DS : threshold voltage of diode 73). Therefore, the resistors R ₁ and R ₂ are set to values such that R ₂ : R ₁ + R ₂ = 1: 2 ⁿ (n: integer, n> 1), and this output 75 is added to the AD converter 76. For example, broken line quantization becomes possible. As described above, it is advantageous to set V _EE + V _{DS so} that the lower bit of the digital output of the AD converter 76 for this voltage becomes 0 ... 0.

By combining the above 1) to 3), it is possible to perform non-linear quantization with several break points. Therefore, only the low signal level part that requires high quantization accuracy is quantized with high accuracy,
By lowering the accuracy as the signal level increases,
With an AD converter with a small number of bits, it is possible to effectively perform AD conversion with a wide dynamic range and high accuracy.
Quantization of a television camera signal, which was said to have a bit A / D converter, is performed by an 8 or 9 bit A / D converter 1.
~ 2 can be done.

(Effect) As described above, according to the present invention, the television camera signal can be quantized without significantly increasing the number of bits of the A / D converter, and the effect of reducing the cost, power, etc. is very high. Is very large.

[Brief description of drawings]

FIG. 4 is a diagram for explaining input / output characteristics of a gamma correction circuit of a television camera, FIG. 2 is a diagram for explaining an increase in quantization error when gamma correction is applied to a digitized video signal, and FIG. Is a block diagram of a television camera in which a video signal processing circuit is digitized, FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG. 5 is a block diagram of a second embodiment of the present invention. FIG. 7 is an input / output characteristic diagram of the non-linear quantization circuit according to the present invention, FIG. 7 is a diagram for explaining the input / output characteristic of the quantization circuit according to the present invention, and FIGS. FIG. 3 is a block diagram showing a specific configuration of a non-linear quantization circuit having non-linear characteristics. 20: Non-linear quantization circuit, 22: Level judgment circuit, 24: Bit shift circuit, 25: Binary constant generation circuit, 28: Subtraction circuit, 30 to 32: Arithmetic circuit, 33: Signal selection circuit, 40: Comparator , 42, 64: Digital encoder, 50, 51, 76: A-D converter.

Claims (1)

[Claims] 1. A linear analog-to-digital (hereinafter referred to as AD) conversion circuit that reduces the quantization accuracy at a constant rate each time the input analog signal level exceeds a fixed value, and a digital output level of the AD conversion circuit. Level determination means for determining
A bit shift means for arithmetically shifting the output of the A / D conversion circuit by a predetermined bit according to the output of the level determination means, and a predetermined numerical value from the output of the bit shift means according to the output of the level determination means. An image signal quantizing device having means for subtracting.