JPH07121114B2 - High efficiency encoder - Google Patents

Description

The present invention relates to a high-efficiency coding apparatus for compressing image data such as digital television signals.

[Outline of Invention]

The present invention, in a high-efficiency coding apparatus applied when transmitting image data such as a digital television signal, divides one screen into a large number of two-dimensional or three-dimensional blocks, and Since subsampling is performed at a rate adapted to the dynamic range narrowed by the correlation, the compression rate can be increased without degrading the quality of the restored image on the receiving side. In particular, in the present invention, as the subsampling rate, there are a state in which subsampling is not performed, a 1/2 subsampling in which the number of pixels is thinned to 1/2, and a 1/4 subsampling in which the number of pixels is thinned to 1/4. The sampling pattern of 1/4 sub-sampling is selectively performed, and is set to be effective for performing interpolation of thinned pixels on the receiving side.

[Conventional technology]

As a television signal encoding method, a method of lowering the sampling frequency for the purpose of narrowing the transmission band is known. For example, the image data is decimated to 1/2 by subsampling, and the position of the subsampling point and the subsampling point used at the time of interpolation are shown (that is, whether the data of the subsampling point above, below, or to the left or right of the interpolation point is used. Flag) is transmitted.

[Problems to be solved by the invention]

An encoding method that attempts to reduce the sampling frequency by using this sub-sampling has high redundancy at a place where the change in luminance level is small, but on the other hand, the sampling frequency becomes 1/2 at a place where the change in brightness is large. In addition, there was a fear that a folding distortion might occur.

Therefore, an object of the present invention is to achieve high efficiency coding capable of both reducing the amount of data to be transmitted and preventing the occurrence of aliasing distortion by varying the sub-sampling cycle in accordance with the dynamic range of each block. To provide a device.

On the receiving side, if the pixels (thinned pixels) thinned out for each block are interpolated using the received data (sub-sampled data), it is said that the thinned pixels are close to the boundaries between the blocks. , The surrounding sub-sampled data for interpolation is insufficient. As a result, the brightness of the interpolation becomes low, and block distortion may occur.

Therefore, another object of the present invention is to provide a high-efficiency coding apparatus capable of interpolating a thinned pixel of a block on which 1/4 sub-sampling is performed across a block boundary.

[Means for solving problems]

In the high-efficiency encoding device according to the present invention, a dynamic range detection circuit for obtaining a dynamic range DR of each block composed of regions belonging to the same field or a plurality of consecutive fields of a digital image signal, and a dynamic range DR for each block are associated with each other. At a minimum, a variable sub-sampling circuit 4 for sub-sampling pixel data of a block at any rate of transmission of all pixels, 1/2 sub-sampling, and 1/4 sub-sampling is provided. When paying attention to the block of, the configuration is such that three thinned pixels are interpolated by a predetermined number of sub-sample data surrounding arbitrary three horizontally thinned pixels in the block, and Subsample data that surrounds any thinned pixel around the subsampling block is Tsu regardless subsampling rate click, and the pattern of sub-sampling is defined as sub-sample data for interpolation are present.

[Action]

When the dynamic range DR of a block is large, the image of this block changes drastically and is not sub-sampled. Further, the smaller the dynamic range DR, the smaller the change in the image of the block, so the sub-sampling rate is lowered. As an example, one of two types of sub-sampling, 1/2, 1/4, is used according to the dynamic range DR. By this adaptive sub-sampling, the sampling frequency can be lowered on average without causing aliasing distortion. Further, if the quantization adapted to the dynamic range DR is applied to the sub-sampling output, the average number of bits per pixel can be reduced and the compression rate of data to be transmitted can be significantly increased.

In addition, the subsampling rate becomes low, and in the case of 1/4 subsampling, any 3 consecutive horizontal
The thinned-out pixels are interpolated by the upper and lower and left and right sub-sampled data. Since the sampling pattern of 1/4 sub-sampling is continuously repeated over other blocks, good interpolation is performed even with thinned pixels near the block boundary.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This invention is made in the following order of items.

a. Configuration on the transmission side b. Configuration on the reception side c. Block and blocking circuit d. Dynamic range detection circuit e. Variable sub-sampling circuit f. Quantization circuit g. Modified example a. Configuration on the transmission side The overall configuration of the transmitting side (recording side) of the present invention is shown. A digital television signal in which, for example, one sample is quantized into 8 bits is input to an input terminal indicated by 1. This digital television signal is supplied to the blocking circuit 2.

The blocking circuit 2 converts the input digital television signal into a continuous signal for each two-dimensional block which is a unit of coding. In this embodiment, one block is (4
The size is (line × 8 pixels = 32 pixels). The output signal of the blocking circuit 2 is supplied to the dynamic range detection circuit 3 and the variable sub-sampling circuit 4. The dynamic range detection circuit 3 detects the dynamic range DR and the minimum value MIN for each block. The pixel data PD from the variable sub-sampling circuit 4 is supplied to the subtraction circuit 5, and the subtraction circuit 5 forms pixel data PDI from which the minimum value MIN is removed.

Further, the detected dynamic range DR is supplied to the variable sub-sampling circuit 4. The variable sub-sampling circuit 4 performs sub-sampling at a cycle (rate of thinning) corresponding to the dynamic range DR. As an example, in the variable sub-sampling circuit 4, the thinning ratio (= the number of images in one block after sub-sampling / the number of pixels in one original block (3
2)) is defined.

The quantization circuit 6 subsamples the subtraction circuit 5
The pixel data PDI after removal of the minimum value and the dynamic range DR are supplied. The quantization circuit 6 quantizes the pixel data PDI. This quantization is a variable number of bits adapted to the dynamic range DR.

The code signal DT from the quantizing circuit 6 is supplied to the framing circuit 7. The framing circuit 7 has a dynamic range DR (8 bits) as an additional code for each block.
And a minimum value MIN (8 bits) is provided. The framing circuit 7 performs error correction coding processing on the code signal DT and the above-mentioned additional code, and also adds a synchronization signal. Transmission data is obtained at the output terminal 8 of the framing circuit 7, and this transmission data is sent to a transmission line such as a digital line.

As described above, the code signal DT has a variable number of bits for each block, but the bit length of the pixel data of the block is uniquely determined from the dynamic range DR in the additional code. Therefore, there is an advantage that it is not necessary to insert a redundant code indicating a data delimiter in the transmission data, despite the use of the variable length code.

b. Configuration on the receiving side FIG. 2 shows the configuration on the receiving (or reproducing) side. Input terminal
The received data from 11 is supplied to the frame decomposition circuit 12. The frame decomposition circuit 12 separates the code signal DT from the additional codes DR and MIN and performs error correction processing. The code signal DT is supplied to the decoding circuit 13, and the dynamic range DR is supplied to the decoding circuit 13 and the interpolation circuit 15.

The decoding circuit 13 performs a process reverse to the process of the quantizing circuit 6 on the transmitting side. That is, the data after removal of the 8-bit minimum level is decoded into a representative level, this data and the 8-bit minimum value MIN are added by the adder circuit 14, and the original pixel data is decoded. The output data of the adder circuit 14 is supplied to the interpolation circuit 15. In the interpolation circuit 15, the thinned pixel data is obtained by weighted averaging the surrounding pixel data. The output data of this interpolation circuit 15 is the block decomposition circuit 16
Is supplied to. The block decomposing circuit 16 is a circuit for converting the decoded data in the order of blocks into the same order as the scanning of the television signal, contrary to the blocking circuit 2 on the transmission side. The decoded television signal is obtained at the output terminal 17 of the block decomposition circuit 16.

c. Block and Blocking Circuit A block, which is a unit of coding, will be described with reference to FIG. In this example, by dividing the screen of one field, it is shown in FIG. 3 (4 lines × 8 pixels).
A large number of two-dimensional blocks are formed. In FIG.
The solid lines indicate the odd field lines, and the broken lines indicate the even field lines. Unlike this example, for example, 4
The present invention can also be applied to a three-dimensional block composed of four two-dimensional regions belonging to each frame.

The blocking circuit 2 will be described with reference to FIGS. 4, 5 and 6. For the sake of simplicity of explanation, it is assumed that the screen of one field has a configuration of (4 lines × 8 pixels) as shown in FIG. 5, and this screen is divided into two vertically and horizontally as shown by the broken line. A case will be described in which four blocks are divided into four to form eight blocks of (2 lines × 2 pixels).

In FIG. 4, as shown in FIG. 6A, the input data A consisting of four lines (Th _{0 to} Th ₃ ) is supplied to the input terminal 21 and synchronized with the input data A to the input terminal 22. The sampling clock B (FIG. 6B) is being supplied. The numbers (1 to 8) indicate the sample data of the line Th ₀ , the numbers (11 to 18) indicate the sample data of the line Th ₁ , and the numbers (21 to 28) indicate the sample data of the line Th ₂ . , And the numbers (31-38) are the line Th ₃
The sample data of each is shown. The input data A is supplied to the delay circuit 23 having a delay amount of Th and the delay circuit 24 having a delay amount of 2Ts (Ts: sampling period). Further, the sampling clock B is supplied to the 1/2 frequency dividing circuit 27.

The output signal C (FIG. 6C) of the delay circuit 24 is the switch circuit 25.
And 26, respectively, and the output signal D (FIG. 6D) of the delay circuit 23 is supplied to the other input terminals of the switch circuits 25 and 26, respectively. Switch circuit 25 is 1/2
Controlled by the output signal E (FIG. 6E) of the frequency dividing circuit 27,
The switch circuit 26 is controlled by the pulse signal obtained by inverting the pulse signal E by the inverter 28. The switch circuits 25 and 26 alternately input signals (C or D) every 2Ts.
Select. The output signal F from the switch circuit 25 is shown in FIG. 6F, and the output signal G from the switch circuit 26 is shown in FIG. 6G.

The output signal F of the switch circuit 25 is supplied to the first input terminal of the switch circuit 29 and the delay circuit 30 having a delay amount of 4Ts. The output signal G of the switch circuit 26 is supplied to the delay circuit 31 having a delay amount of 2Ts. Output signal H of delay circuit 30
(Fig. 6H) is supplied to the third input terminal of the switch circuit 29. The output signal I (FIG. 6I) of the delay circuit 31 is supplied to the second input terminal of the switch circuit 29 and the delay circuit 32 having a delay amount of 4Ts. Output signal J of delay circuit 32 (6th
J) is supplied to the fourth input terminal of the switch circuit 29.

The output signal of the 1/2 divider circuit 27 is supplied to the 1/2 divider circuit 33, and the output signal K (K in FIG. 6) is formed. This signal K
The switch circuit 29 is controlled by the 1st, 2nd, and 4Ts intervals.
The third and fourth input terminals are sequentially selected. Therefore, the signal L output from the switch circuit 29 to the output terminal 34 is
It becomes what is shown in FIG. 6L. In other words, the order of each field of data is the order of each block (for example, 1 → 2 → 11 → 1).
2) is converted. Of course, the actual number of pixels in one field is much larger than the example shown in FIG. 5, but by the scan conversion similar to that described above, it is converted into the order of each block shown in FIG.

d. Dynamic Range Detection Circuit FIG. 7 shows an example of the configuration of the dynamic range detection circuit 3. The blocking circuit 2 is connected to the input terminal indicated by 41.
Thus, as described above, the image data of the area that needs to be encoded is sequentially supplied for each block. The pixel data from the input terminal 41 is supplied to the selection circuit 42 and the selection circuit 43. One of the selection circuits 42 selects and outputs the one having a larger level between the pixel data of the input digital television signal and the output data of the latch 44. The other selection circuit 43 selects and outputs the smaller one of the pixel data of the input digital television signal and the output data of the latch 45.

The output data of the selection circuit 42 is supplied to the subtraction circuit 46 and is also captured by the latch 44. The output data of the selection circuit 43 is supplied to the subtraction circuit 46 and the latch 48, and at the same time, latched.
Captured by 45. A latch pulse is supplied from the control unit 49 to the latches 44 and 45. Timing signals such as a sampling clock and a synchronizing signal that are synchronized with the input digital television signal are supplied to the control unit 49 from the terminal 50. The control unit 49 supplies a latch pulse to the latches 44 and 45 and the latches 47 and 48 at a predetermined timing.

At the beginning of each block, the contents of latches 44 and 45 are initialized. All of the data of "0" is initialized to the latch 44, and all of the data of "1" is initialized to the latch 45. The maximum level is stored in the latch 44 among the pixel data of the same block that are sequentially supplied. In addition, the minimum level is stored in the latch 45 among the pixel data of the same block that is sequentially supplied.

When the detection of the maximum level and the minimum level is completed for one block, the maximum level of the block occurs at the output of the selection circuit 42. On the other hand, the minimum level of the block occurs at the output of the selection circuit 43. Latches 44 and 45 are reinitialized when the detection for one block is complete.

The output of the subtraction circuit 46 has the maximum level MA from the selection circuit 42.
The dynamic range DR of each block is obtained by subtracting the minimum level MIN from X and the selection circuit 43. These dynamic range DR and minimum level MIN are latched in the latches 47 and 48 by the latch pulse from the control block 49, respectively. The dynamic range DR of each block is obtained at the output terminal 51 of the latch 47, and the minimum value MIN of each block is obtained at the output terminal 52 of the latch 48.

e. Variable Subsampling Circuit FIG. 8 shows an example of the variable subsampling circuit 4 that performs subsampling adapted to the dynamic range DR.
Description will be made with reference to FIGS. 9, 10 and 11.

In FIG. 8, the blocking circuit 2 is provided at the input terminal indicated by 60.
Pixel data PD from is supplied. Further, the dynamic range DR from the dynamic range detection circuit 3 is supplied to the input terminal indicated by 61. Sub-sampling circuits 62 and 63 are connected to the input terminal 60.

The sub-sampling circuit 62, as shown in FIG.
Perform 1/2 sub-sampling by thinning out pixels in the block one by one. In FIG. 9, x indicates a pixel (thinned pixel) which is not sub-sampled and therefore is not transmitted,
White dots indicate pixels to be subsampled (subsampled pixels). The output data of the sub-sampling circuit 62 is half the original number of pixels.

The sub-sampling circuit 63, as shown in FIG.
1/4 sub-sampling is performed by thinning out three consecutive pixels in the block in the horizontal direction. In this case, the sub-sampling phase is
It is shifted by 1/2. The number of pixels of the output data of the sub-sampling circuit 63 is 1/4 of the original number of pixels.

Pixel data PD from input terminal 60 and sub sampling circuit
The output data of each of 62 and 63 is supplied to the selector 64. A control signal is supplied from the ROM 65 to the selector 64,
An output signal is obtained at the output terminal 66 of the selector 64. ROM65
, The dynamic range DR is supplied as an address signal, and the ROM 65 outputs a 2-bit control signal corresponding to the dynamic range DR. An example of the relationship between the dynamic range DR and the control signal is shown below.

i. When the dynamic range DR is small, for example (0 ≦ DR ≦
In the case of 17), the control signal becomes (01), and the output signal with the number of pixels reduced to 1/4 of the sub-sampling circuit 63 is selected.

ii. When the dynamic range DR is in the middle, for example (18 ≦ DR
When ≦ 35), the control signal becomes (10) and the output signal with the number of pixels reduced to 1/2 of the sub-sampling circuit 62 is selected.

iii. When the dynamic range DR is large, for example (36 ≦ D
In the case of R), the control signal becomes (11), sub-sampling is not performed, and all pixel data from the blocking circuit 2 is output.

The threshold level for determining the magnitude of the dynamic range DR described above matches the threshold level in variable-length coding adapted to the dynamic range described later. However, it is not necessary to match the threshold levels on both sides, and optimum values are used for each.

When 1/4 sub-sampling is performed, the receiving side
As shown in the figure, the surrounding four sub-sampling data
The thinned pixels Y1, Y2, Y3 are interpolated using X1, X2, X3, X4, respectively. In this interpolation, the data of the thinned pixels Y1, Y2, Y3 are approximated by the following equation.

Y1 = (X1 + X2 + 3X3 + X4) / 6 Y2 = (X1 + X2 + X3 + X4) / 4 Y3 = (X1 + X2 + X3 + 3X4) / 6 The sampling pattern of 1/4 subsampling shown in FIG. Regardless of which sampling pattern of / 4 sub-sampling is provided, the sampling pattern of 1/4 sub-sampling is repeated across the block boundary.

A block having a sampling pattern of 1/2 subsampling is located above and to the left of a block of interest having a sampling pattern of 1/4 subsampling,
When blocks having a sampling pattern of 1/4 subsampling are located below and to the right of the block of interest (see FIG. 11B), the relationship between the subsample pixels and the thinned pixels is as shown in FIG. 11A. Become. In addition, when a block having a sampling pattern of 1/4 subsampling is located above and to the left of the block of interest, and a block having a sampling pattern of 1/2 subsampling is located below and to the right of the block of interest (see In FIG. 11D), the relationship between the sub-sampled pixel and the thinned-out pixel is as shown in FIG. 11C.

As can be understood from FIGS. 11A and 11C,
The thinned-out pixels around the target block are surrounded by the four sub-sampled pixels including one sub-sampled pixel included in another block in the relationship shown in FIG. Therefore, the thinned pixels in the periphery are interpolated well.

The structure of an example of the sub-sampling circuit 62 is shown in FIG.
In FIG. 12, the input signal A (see FIG.
Figure A) is provided. The basic block formed by the blocking circuit 2 is (4 lines × 8 pixels), the input signal A is in the order of lines Th ₀ , Th ₁ , Th ₂ ,.
Eight pixel data (1-8), (11-1) in each line
8), (21-28) ... are included. In FIG. 12, a sampling clock B (FIG. 13B) synchronized with the input signal A is supplied to the input terminal indicated by 69.

The input signal A is supplied to the delay circuit 70 and the sample hold circuit 72 having the delay amount of the sampling cycle Ts. The output signal C of the delay circuit 70 (FIG. 13C) is supplied to the sample hold circuit 71. The sampling clock B is supplied to the frequency dividing circuit 73 having a frequency dividing ratio of 1/2, and the output signal D (FIG. 13D) of the frequency dividing circuit 73 is supplied to the inverter 74. The output signal E (FIG. 13E) of the inverter 74 is supplied to the sample hold circuits 71 and 72 as sampling pulses.

At the rising edge of the sampling pulse E, for example, the signals C and A are sampled and held. Therefore, the sample hold circuit 71 obtains the sampling output F shown in FIG. 13F, and the sample hold circuit 72 obtains the sampling output G shown in FIG. 13G. These sampling outputs F and G are supplied to the input terminals of the switch circuit 75, respectively.

The switch circuit 75 is controlled by the output signal H (FIG. 13H) of the frequency dividing circuit 76 having a frequency dividing ratio of 1/8, and alternately selects the output signals of the sample and hold circuits 71 and 72. Therefore, the output signal I output from the switch circuit 75 to the output terminal 77
As shown in FIG. 13I, the data is decimated to 1/2, and the subsampling phase is shifted by one sampling period between adjacent lines.

The sub-sampling circuit 63 can be configured similarly to the sub-sampling circuit 62 described above.

f. Quantization circuit The quantization circuit 6 performs variable-length coding adapted to the dynamic range DR. FIG. 14 shows an example of the quantization circuit 6. In FIG. 14, the ROM indicated by 55 stores a data conversion table for converting the pixel data PDI (8 bits) after the minimum value removal into a compressed bit number.
Dynamic range D from input terminal 56 for ROM55
R and the pixel data PDI from the input terminal 57 are supplied as an address signal.

In the ROM 55, the data conversion table is selected according to the size of the dynamic range DR, and the 5-bit encoded data DT is taken out to the output terminal 58. Depending on the dynamic range DR, the number of bits of the encoded data DT changes in the range of 0 bit to 5 bits. Therefore, the effective bit length changes in the code output from the ROM 55. In the framing circuit 7, valid bits are selected.

FIG. 15 is used to explain the variable bit length coding adapted to the dynamic range, which is performed by the quantizing circuit 6 described above. This encoding is a process of converting the minimum value to the representative level of the pixel data PDI. The allowable maximum value of the quantization distortion (referred to as maximum distortion) that occurs during this quantization is set to a predetermined value, for example 4.

FIG. 15A shows the case where the dynamic range DR is 8.
In the case of (DR = 8), the central level 4 is the representative level L0.
And (maximum strain E = 4). That is, (0 ≦ DR ≦
In the case of 8), the central level of the dynamic range is set as the representative level, and it is not necessary to transmit the quantized data. Therefore, the required bit length is 0. On the receiving side, the minimum value MIN of the block and the dynamic range D
Decoding is performed from R using the representative level L0 as the restored value.

FIG. 15B shows the case of (DR = 17), the representative level is set to (L0 = 4) (L1 = 13), and the maximum distortion E is 4. Since there are two representative levels L0 and L1, the bit length is 1. In the case of (9 ≦ DR ≦ 17), the bit length is 1. The maximum distortion E becomes smaller as the dynamic range DR is narrower.

FIG. 15C shows the case of (DR = 35), and the representative levels are defined as (L0 = 4) (L1 = 13) (L2 = 22) (L3 = 31), respectively, and (E = 4) is there. Since there are four representative levels L0 to L3, the bit length is 2. In the case of (18 ≦ DR ≦ 35), the bit length is 2.

In the case of (36 ≦ DR ≦ 71), 8 representative levels (L0 to L
7) is used. FIG. 15D shows the case of (DR = 71), and the representative levels are (L0 = 4) (L1 = 13) (L2 = 22) (L3
= 31) (L4 = 40) (L5 = 49) (L6 = 58) (L7 = 67). The required bit length is 3 in order to distinguish the eight representative levels L0 to L7.

In the case of (72 ≤ DR ≤ 143), 16 representative levels (L0 to L
15) is used. FIG. 15E shows the case of (DR = 143), and the representative level is (L8 = 76) (L9 = 85) (L10 = 94).
(L11 = 103) (L12 = 112) (L13 = 121) (L14 = 130)
(L15 = 139) (L0 to L7 are the same as the above values). 4 to distinguish 16 representative levels (L0 to L15)
Need a bit.

In the case of (144 ≦ DR ≦ 287), 32 representative levels (L0 ~
L31) is used. FIG. 15F shows the case of (DR = 287), and the representative level is (L16 = 148) (L17 = 157) (L18 = 1
66) (L19 = 175) ・ ・ ・ ・ ・ (L27 = 247) (L28 = 256)
(L29 = 265) (L30 = 274) (L31 = 283) (L0 to L15 are
Same as above value). 32 representative levels (L0
~ L31) requires 5 bits. Actually, since the input pixel data is quantized by 8 bits, the maximum value of the dynamic range DR is 255, and it is not quantized to the representative level (L28 to L31).

Since the television signals in one block have a three-dimensional correlation in the horizontal and vertical two-dimensional directions and in the time direction, in the steady part, the variation range of the level of the pixel data included in the same block. Is small. Therefore, even if the dynamic range of the data DTI after removing the minimum level MIN shared by the pixel data in the block is quantized with a quantization bit number smaller than the original quantization bit number, quantization distortion hardly occurs. . By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original transmission bandwidth.

g. Modified example When performing coding adapted to the dynamic range, for example, when the dynamic range is divided into four and quantized into four representative levels, as shown in FIG. A value that matches the value MAX may be used. Further, in the case of variable length encoding, the representative level may be a fixed value for each bit length. Further, dynamic range adaptive coding with a fixed bit length may be used. Furthermore, in the present invention, a high efficiency coding method other than the dynamic range adaptive coding method may be combined.

〔The invention's effect〕

According to the present invention, in the stationary part where the change width of the brightness level is small,
The sub-sampling decimation rate is increased, while the sub-sampling decimation rate is reduced in the part where the change range of the luminance level is large, so that the quality of the data to be transmitted can be reduced without causing deterioration in image quality such as aliasing distortion. The amount is sufficiently reduced as compared with the original data, and the transmission band can be narrowed.

Further, in the present invention, since the sampling pattern of 1/4 sub-sampling is formed across the boundary of the block, interpolation of thinned pixels around the block can be easily and favorably performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a receiving side, and FIG. 3 is a schematic diagram used for explaining a block which is a unit of encoding processing. 5, FIG. 5 and FIG. 6 are examples of the constitution of the blocking circuit, schematic diagrams and timing charts for explaining the same, FIG. 7 is a block diagram of an example of the dynamic range detection circuit, and FIG. Block diagram of an example of a sampling circuit, No. 9
FIGS. 10, 10 and 11 are schematic diagrams for explaining the operation of the variable subsampling circuit, FIGS. 12 and 13 are block diagrams of an example of the subsampling circuit, and timing charts for explaining the operation, 14 and 15 are a block diagram of an example of a quantization circuit and a schematic diagram for explaining the operation thereof,
FIG. 16 is a schematic diagram used to explain another example of quantization. Description of main symbols in the drawings 1: Input terminal of digital television signal, 2: Blocking circuit, 3: Dynamic range detection circuit, 4: Variable sub-sampling circuit, 6: Quantization circuit, 7: Framed circuit.

Claims (1)

[Claims] 1. A means for obtaining a dynamic range of each block consisting of regions belonging to the same field or a plurality of consecutive fields of a digital image signal, and at least transmission of all pixels corresponding to the dynamic range of each block. , A sub-sampling rate of 1/4 sub-sampling, and means for sub-sampling the pixel data of the block at any one of the rates, when focusing on the block of the 1/4 sub-sampling, the block In the horizontal direction, the three thinned pixels are interpolated by a predetermined number of subsampled data surrounding three arbitrarily thinned pixels, and the 1/4 subsampling block The sub-sampled data that surrounds any thinned-out pixels in the surroundings will be Razz, high-efficiency encoding apparatus characterized by patterns of sub-sampling is defined as the sub-sample data exists for the interpolation.