JPH0712148B2 - Method of receiving data from successive approximation A / D converter - Google Patents

Description

The present invention relates to a data receiving method for receiving conversion data of a successive approximation A / D converter by a serial reception interrupt.

[Conventional technology]

When the A / D conversion start command is issued from the CPU and the successive approximation type A / D converter (hereinafter abbreviated as ADC) that receives the command outputs the conversion data serially, a predetermined number of bits is output to the serial reception register on the CPU side. Serial interrupt is applied to the CPU when the conversion data of is acquired. The CPU takes in the conversion data with this interrupt and completes one A / D conversion.

FIG. 3 is a block diagram of this type of system, in which 1 is a CPU, 2 is a successive approximation ADC, 3 is a serial data line, and 4 is a serial reception register. An analog input CH (channel) selection signal, an AD start signal, and a clock signal are output from the CPU1 to the ADC2. The ADC2 holds the 3-bit CH selection signal in the address latch 21, and the corresponding analog input (CH0
~ CH7) is selected by the multiplexer 22. When the successive approximation register (SAR) 23 receives the AD start signal, it first applies 1/2 of the maximum reference voltage REF to the D / A converter (DAC) 24,
The analog conversion value is compared with the analog input by the comparator 25. Then, when the comparison result (1,0 depending on the size) of the corresponding channel is input to the SAR23 through the multiplexer 22, the SAR23 gives the next comparison value 2 ^-2 REF to the DAC24,
The following 2 ^-3 whenever the clock is input REF, 2 ^-4 REF, to change the comparison value with .... Then, when the comparison result for the final comparison value 2 ^-8 REF is obtained, the start bit and the stop bit are added to the 8-bit A / D conversion data for 2 ^-1 REF to 2 ^-8 REF to add the data from the shift register 26. It is sent serially to line 3 and transferred to serial reception register 4 on the CPU side.

FIG. 4 is a time chart when an analog input is AD-converted into 8 bits with a clock frequency of 250 KHz. 1
Since the clock cycle is 4 μs, 8 × 4 μs = 32 μs is required for 8-bit AD conversion, and (8 + 2) × to add 1 bit for each of start and stop for data transmission.
4 μs = 40 μs is required. Therefore, after a certain time T (= 72 μs) from the rise of the AD start signal, the CPU 1 receives a reception interrupt.

FIG. 5A shows the relationship between the clock and the serial transfer data. In this example, the serial reception register 4 can take in the data at the falling edge of the clock.

[Problems to be solved by the invention]

By the way, in an electronic control device for controlling an internal combustion engine, there is a demand for higher speed A / D conversion as the control content becomes more complicated, and the number of cases in which the successive approximation type ADC as described above is used is increasing. However, since serial reception as described with reference to FIG. 3 is vulnerable to noise, there is a strong possibility that incorrect data will be received. For example, as shown in FIG. 5 (b), when noise (especially ignition noise) is mixed in the data line 3 and the level of the data line 3 temporarily changes even when the A / D conversion data is not transmitted, As a result of being read as the start bit, erroneous data due to noise is received.

In general, the ADC2 side takes a protective measure to pull up the data line 3 so that the output does not change when the AD start signal is not received. From the viewpoint that the conversion data will not be sent unless the CPU 1 also issues AD start, it is always ready to accept the reception interrupt. Therefore, the fifth
In the case shown in FIG. 6B, all 1's are erroneously received.

In order to improve this point, conventionally, a filter is provided on the receiving end side of the data line 3 to remove the noise. However, if a filter is used, high-speed transmission cannot be performed due to its time constant, and there is a drawback that the control response cannot be sufficiently improved. Further, a filter using an analog circuit is not preferable because it increases the amount of hardware.

The present invention seeks to reduce the probability of such erroneous reception without using a filter.

[Means for Solving Problems] The present invention outputs a conversion start command from a CPU to a successive approximation A / D converter, and the converter receiving the command sequentially compares an analog input with a reference value. A method of receiving data from a successive approximation A / D converter that converts a digital data of a predetermined number of bits, and then transfers the data by serial communication to the serial reception register on the CPU side, which causes a reception interrupt to the CPU. ,
It is characterized in that only the data obtained by the reception interrupt generated within a certain period after the conversion start command is transmitted is treated as normal data.

[Action]

If only the data generated by the reception interrupt within a certain period after the conversion start command is sent out of the data obtained by the reception interrupt is treated as normal, even if the reception interrupt occurs due to noise in other periods, that data Is negligible, the probability of malfunction due to abnormal data due to noise is significantly reduced. Since this method does not prohibit the reception interrupt itself, the processing time will be long if there is a lot of noise, but since it is simple as a noise countermeasure process (no separate processing for time management is required), the memory used by adding a program There is an advantage that the area is small. Moreover, since a filter or the like is not used, a decrease in baud rate can be avoided.

〔Example〕

FIG. 1 is a flow chart showing an embodiment of the present invention and shows a part of the processing of the CPU 1 in FIG. COMP1 is an interrupt routine that occurs every 2ms. "Conversion CH set" is shown in Fig. 3.
Sending a CH selection signal, "AD conversion start" corresponds to sending an AD start signal. In this example, the data due to the reception interrupt before 72 μs and after the passage of 200 μs from this AD start (conversion start command) is ignored, and the data due to the reception interrupt during that period is made normal. FIG. 2 is this time chart.

As shown in FIG. 4, when the transmission of the converted data is completed 72 μs after the start of conversion, a serial reception interrupt occurs at that time. In the serial reception interrupt routine shown in FIG. 1, it is judged whether the interrupt has occurred 72 μs after AD start and 200 μs before AD conversion result processing, and if yes (Y), the processing is executed. If no (N), the process is not performed.

〔The invention's effect〕

As described above, according to the present invention, when the conversion data of the successive conversion type ADC is received by serial communication, the normality of the data obtained by the reception interrupt is a time zone based on the A / D conversion start time point. Since the distinction is made by the above, the probability of erroneous reception due to noise can be reduced without reducing the baud rate.

[Brief description of drawings]

FIG. 1 is a flow chart showing an embodiment of the present invention, FIG. 2 is an operation explanatory diagram thereof, FIG. 3 is a block diagram of a system for receiving data from a successive approximation A / D converter, and FIG. 4 is an A / D. A time chart of the conversion operation, and FIG. 5 is an explanatory diagram of A / D conversion data. In the figure, 1 is a CPU, 2 is a successive approximation A / D converter, 3 is a serial data line, and 4 is a serial reception register.

Claims (1)

[Claims] 1. A conversion start command is issued from a CPU to a successive approximation A / D converter, and the converter which receives the command sequentially compares an analog input with a reference value and converts the analog input into digital data of a predetermined number of bits. In the method of receiving data from the successive approximation type A / D converter in which a reception interrupt is given to the CPU when the data is further transferred to the serial reception register on the CPU side by serial communication, after the conversion start command is transmitted, a constant value is obtained. A method of receiving data from a successive approximation type A / D converter characterized in that only the data obtained by the reception interrupt that occurred within the period is treated as normal data.