JPH0712234B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suitable for a time switch memory (TSW) relating to multiplex communication such as a passageway of a telephone exchange. The purpose is to reduce the load on the operation speed of the time switch memory by dividing the processing operation into several cycle times and performing pipeline processing without completing within the cycle. , First latch means for latching the second address in synchronization with the clock signal, second latch means for latching the output of the second latch means in synchronization with the clock signal, and the second latch means. A first memory portion to which write data and a first address output from the latch means are provided; and write data and a first memory portion to which the write data and the first address are output from the second latch means. A second memory portion to which an address of 2 is given, third latch means for latching the data output from the first and second memory portions in synchronization with the clock signal, and the third latch means. And a write enable signal is output to one of the first memory unit and the second memory unit to write the output, and the other is read. And a control unit for setting the state.

[Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suitable for a time switch memory (TSW) relating to multiplex communication such as a communication path of a telephone exchange.

[Prior Art] FIG. 3 is an explanatory diagram according to a prior art.

FIG. 3A is a diagram for explaining the function of the time switch memory (TSW). In the figure, TSW is, for example, a data string Di input in the order of d → a → e → c → b ...
n is stored in the time switch memory 1 and data a → b →
It has a function of outputting a data string Dout whose order is rearranged in the order of c → d → e ....

FIG. 1B is a diagram showing an example in which the time switch memory 1 is provided in a communication path of a telephone exchange to perform multiplex communication, in which 1 is a time switch memory (TSW),
2 is a multiplexer (multiplexer) having a multiplex communication function for multiplexing communication data of, for example, n = 1024 lines (the number of subscriber telephones), 31 to 3n are 1 line of analog voice signals S _{1 to} Sn of n lines of users. An A / D converter that performs pulse code modulation (PCM) for each and converts it into digital signal data, 4 is a demultiplexer (demultiplexing device), and 5 and 6 are transmission lines.

In FIG. 3, the audio signal is sampled at a sampling rate of 8 kHz and digitally coded by an A / D converter.

The digital outputs of the A / D converters 31 to 3n are multiplexed by the multiplexer 2, and the multiplexed data string is stored in TSW1 via the transmission line 5. In TSW1, the data sequence rearranged in a desired order is transmitted via the transmission line 6 to the demultiplexer 4
Entered in. The demultiplexer separates the input data string for each line.

[Problems to be Solved by the Invention] By the way, when rearranging a data string that is input at random, as the number of lines increases, a high-speed and large-capacity memory is generally required. However, there is a problem that as the memory capacity increases, a higher processing operation speed is required.

That is, the relationship between the memory capacity of the time switch memory for the multiplicity n and the processing operation speed (writing speed and reading speed) is n = 1024 lines and the sampling rate = 8 kHz, the required memory capacity is 1024wo.
rd × m bit, processing speed is 122 [ns], and when n = 2048 lines, the required memory capacity is 2048 × m bi
t, the processing operation speed is 61 [ns], and in the case of n = 4096 lines, the required memory is 4096 × m bit and the processing operation speed is 30 [ns].

Here, m is the number of quantized bits when an analog signal such as voice is digitized, and generally m = 8 is selected.

Therefore, each time the multiplicity n is doubled, the required processing operation speed is doubled, and there is a problem that high-speed processing is forced on the operation cycle time of the time switch memory.

The present invention was created in view of the problems of the conventional example, and by performing the pipeline processing by dividing the processing operation into several cycle times without completing the writing and reading processing operations within one cycle, An object of the present invention is to provide a semiconductor memory device that can reduce the load on the operating speed of the time switch memory.

[Means for Solving Problems] A semiconductor memory device of the present invention includes a first latch means for latching write data, a first address, and a second address in synchronization with a clock signal, and the second latch means. Second latch means for latching the output of the latch means in synchronization with the clock signal; a first memory section to which write data and a first address output from the second latch means are applied; A second memory unit to which write data and a second address output from the second latch unit are given; and a second memory unit that latches the data output from the first and second memory units in synchronization with the clock signal. 3 latch means, 4th latch means for latching the output of the 3rd latch means in synchronization with the clock signal, and write enable for one of the first memory section or the second memory section. The above-mentioned object is achieved by providing a control means for outputting a read signal to put it in a written state and the other into a read state.

[Operation] According to the present invention, the pipeline operation is performed by the first to fourth latch means, and the random access and the sequential access are simultaneously performed to the first and second memory sections. That is, the write data by the first latch means,
While the first and second addresses are being fetched, the write data and the first and second addresses fetched in the previous cycle are given to the first and second memory sections by the second latch means. On the other hand, the first
Alternatively, while the data from the second memory section is being latched in the third latch means, the data read in the previous cycle is output from the fourth latch means.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a time switch memory according to an embodiment of the present invention.

In the figure, 23 is the first latch means,
D-type flip-flop circuit (DFF) 23a that latches Din (8 bits) in synchronization with the rising edge of clock signal CLK and outputs data DIN, and input random address ra (10 bits)
Is latched in synchronization with the clock signal CLK and outputs a random address RA, which is composed of DFF23b. Counter 23c
Outputs a sequential address SA by counting the clock signal CLK. fc is a signal that clears the counter when the sequential address SA is counted up from 0 to 1023 when the multiplicity n = 1024 lines.

When the sequential address SA is input from the outside, a D-type flip circuit similar to the DFF 23b is provided instead of the counter 23c.

Reference numerals 27 and 28 are selectors that select the random address RA or the sequential address SA latched in the DFF 23b in response to the control signal (c) from the control circuit 34. Reference numerals 35 and 36 are predecoders for predecoding the random address RA and the sequential address SA. That is, in the embodiment of the present invention, the address is decoded in two stages, and the RAM is
# 1 and 2 further decode the predecoded address. Further, 24 is a second latch means,
DFF24a that latches DIN in synchronization with the clock signal CLK,
The predecoded random address RA or the sequential address SA is latched in synchronization with the clock signal CLK, and the address input terminal A (# 1) or A of the RAM # 1 or # 2 is latched.
It is composed of DFFs 24b and 24c output to (# 2).

Reference numerals 29 and 30 denote random access memory units (RAM) # 1 and # 2 for inputting the data DIN and the random address RA to perform a write process and to perform a read process according to the sequential address SA. IN # 1 and IN # 2 are data input terminals, A # 1 and A # 2 are address input terminals, and WE is a write enable signal input terminal.

Reference numeral 25 denotes a third addressing means, which is a read data D (#
1) Also, D (# 2) is composed of DFFs 25a and 25b which latch in synchronization with the clock signal CLK.

Reference numeral 31 is a third selection means, which is read data D (# 1)
Alternatively, it is a selector for selecting D (# 2) in response to the control signals c ₃ , c ₄ from the control circuit 34. Reference numeral 32 is an auxiliary selector used for tests and the like. 26 is a fourth latching means,
The read data D (# 1) or D (# 2) is latched in synchronization with the clock signal CLK, and the DFF26a that outputs the read data dout and the DFF2 that outputs the auxiliary read data dout '
It is composed of 6b and.

Further, 37 is a parity generation circuit for generating a paridi bit corresponding to the input data DIN, 38 is a parity checker for checking whether or not DIN is correctly written and correctly read, 39 is a parity error detection signal ( err) is a D-type flip-flop circuit (DFF) that latches in synchronization with the clock signal CLK.

33 is each DFF 23a, 23b, 23c, 24a, 24b, 25a, 25b, 26a, 26b and 39
Is a clock generation circuit for supplying the clock signal CLK to the latch circuit of the above and the write enable signals ▲ ▼ and ▲ ▼ to the RAMs # 1 and # 2.

Note that ▲ ▼ and ▲ ▼ may be input from the outside. However, from the clock generation circuit 33 ▲ ▼, ▲
When ▼ is supplied, ▲ ▼ is disabled when ▲ ▼ is enabled.

Reference numeral 34 is a control circuit for controlling which of the two systems of inputs to each selector 27, 28, 31 and 32 is connected to the selector output via a control line (not shown). The time switch memory is configured by these components.

FIG. 2 is a time chart showing an example of the operation according to the embodiment of the present invention, showing a case where the RAM # 1 is sequentially read and the RAM # 2 is randomly written.

In the figure, CLK is a clock signal, ra is an input random address, RA is a latched random address, fc is a clear signal, SA is a sequential address generated by a counter 23c, Din is input data, and DIN is a first latch circuit. The input data latched by 23, IN is the input data latched by the second latch circuit 24, and A (# 1) is
For example, a sequential address from 0 to 1023, A
(# 2) is a random address, D (# 1) is read data, dout is read data latched by the fourth latch circuit 26, ▲ ▼ and ▲ ▼ are write enable signals, and ▲ ▼ is a parity error signal. Shows.

Referring to FIG. 2, a case will be described in which the first RAM (# 1) 29 is sequentially read and the second RAM (# 2) 30 is randomly written.
In this case, the selector 27 selects the sequential address SA from the counter 23c, and the selector 28 selects the random address RA from the DFF 23b. On the other hand, the selector 31
Data D # 1 from DFF25a is selected.

First, at the rising edge of the clock signal CLK, the input random address ra is latched in DFF23b, and the input data Din is DFF23.
Latched to a. The content "a" of the random address RA is output from DFF23b, and the input data DIN is input from DFF23a.
The content “α” is output. On the other hand, the sequential address SA of the counter 23c is cleared by the clear signal fc and "0" is output.

The next rising edge of the clock signal CLK causes the input random address ra “b” and the content “β” of the input data Din to be D
It is latched by FFF23b and DFF23a. At the same time, data obtained by adding a parity bit to "a" is latched by the DFF 24a, and its output DIN 'is input to IN # 1 of RAM # 1 and IN # 2 of RAM # 2. However, since only WE2 is enabled, R
Data “α” is written only to AM # 1.

Further, the sequential address “0” predecoded by the predecoder 35 is latched in the DFF 24b, and the random address “a” predecoded by the predecoder 36 is
Latch to DFF24c. Therefore, the content "a" of the RAM # 2 is selected by applying the content "a" of the random address RA which was latched in the previous cycle to the data "α", and the content "α" of the DIN is stored in the address. Written.
On the other hand, the first RAM # 1 has a sequential address SA
"0" is applied to select the address 0, and the stored information at the address is read. The counter 23c counts up at this time and outputs the sequential address SA "1".

At the next rising edge of the clock signal CLK, the input random address ra “c” and the input data Din “γ” are transferred to the DFF23b,
Latched by DFF23a. Further, the counter 23c counts up and outputs "2".

At this point, the content “β” of the data DIN is written into the second RAM 30 at the address “b” designated by the random address RA. Reading is performed from the address "1" designated by the sequential address SA from the first RAM 29. Further, the content “0” of the read data D (# 1) is latched by the fourth latch circuit 26.

Next, at the rising edge of the clock signal CLK, the input random address ra “d” and the content “δ” of the input data Din.
Is latched by DFF23b, 23a. On the other hand, the counter 23c counts up and outputs "3" designated by the sequential address SA. At this point, the second RAM3
The content “γ” of DIN is written in the address designated by the random address RA for 0. Reading is performed from the address "2" designated by the sequential address SA from the first RAM 29. Further, the content “1” of the read data D (# 1) is latched by the fourth latch circuit 26. On the other hand, at this time point, the content “0” of the read data D (# 1)
Is the output data dout.

Next, when the clock signal CLK rises, the input random address ra “e” and the input data Din “ε” become DFF.
It outputs "e" which is latched by 23a and 23b and which is designated by the random address RA and the content "ε" of the input data DIN. Meanwhile, the content “4” of the sequential address SA is latched. At this point, the data DI is stored in the "d" address designated by the random address RA to the second RAM 30.
The content “δ” of N is written. The first RAM 29 is read from the address "3" designated by the sequential address SA. Further, the content “2” of the read data D (# 1) is latched by the fourth latch circuit 26. On the other hand, at this point, the content “1” of the read data D (# 1)
Is the output data dout.

The err signal has a solid line as shown in the figure when the parity is normal. For example, when a parity error occurs in the read data at the address "0", it is output via the parity check circuit 38 as shown by the broken line.

Normally, after the end of the frame, that is, when all the data in the RAM 29 is read, the selector 27 sets the random address.
RA, selector 28 controls switching so as to select sequential address SA. That is, ▲ ▼ is periodically fixed to the low level and ▲ ▼ is fixed to the high level, and the random write is performed to the RAM # 1 and the sequential read is performed from the RAM # 2.

In this way, the input random address RA and the sequential address SA are selected via the control circuit 34.
Second selecting means 27, 28, first and second RAMs 29, 30 for writing or reading the data at any time to make a desired transmission order,
Control circuit for the read data D (# 1) or D (# 2)
By providing the third selection circuit 31 that selects via the 34, the information of the input data Din, the input random address ra and the sequential address SA, and the clear signal fc are fetched, and the sequential read is performed via the first RAM 29, for example. Then, it becomes possible to perform a random write via the second RAM 30, allocate the processing of the data for each unit cycle, and perform a pipeline operation.

In the embodiment, the case where the sequential read and the random write are performed has been described, but it is also possible to perform the sequential write and the random read conversely.

[Effects of the Invention] According to the present invention as described above, data processing can be divided into several cycle times to be performed.
The load on the RAM access speed can be reduced and proper processing can be performed. In addition, by dividing the RAM into # 1 and # 2 and performing double buffer processing, the order of data can be interchanged without interruption.

This doubles the multiplicity of the communication paths of telephone exchanges.
It becomes possible to cope with the speeding up of the processing operation regarding the transmission of M.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a time chart explaining an operation according to the embodiment of the present invention, and FIG. 3 is an explanatory diagram according to a conventional example. is there. (Description of symbols) 1 ... Time switch memory (semiconductor memory device), 2 ... Multiplexer, 31 to 3n ... A / D converter, 4 ... Demultiplexer, 5,6 ... Transmission line, S ₁ to Sn ... Analog audio signal, 11,23,12,24,13,25, and 26,14 ... Latch means of the first, second, third and fourth, 15,16,19 ... First, second and third Selection means, 17,18 ... first and second RAMs (random write / read memories), 21 ... clock generation means, 22 ... control means, 23a, 23b, 23c, 24a, 24b, 24c, 25a, 25b , 26a, 26b and 39 ……
D-type flip-flop circuit (DFF), 27,28,31,32 ... Selector, 29,30 ... Random access memory block (RAM # 1, RAM # 2), 33 ... Clock generation circuit, 34 ... Control Circuit, 35,36 …… Predecoder, 37 …… Parity generation circuit, 38 …… Parity detection circuit, fc …… Clear signal, CLK …… Clock signal, C _{1 to} C ₄ … Control signal, ▲ ▼, ▲ ▼ …… Write enable signal, RA …… Random address, SA …… Sequential address, A (# 1), A (# 2) …… Random or sequential address, D (# 1), D (# 2) …… Read data, Dout, dout …… Read output data, dout´ …… Auxiliary read output data.

Claims (2)

[Claims] 1. A first latch means for latching write data, a first address, and a second address in synchronization with a clock signal, and an output of the second latch means for latching in synchronization with the clock signal. Second latch means, a first memory section to which write data and a first address output from the second latch means are given, and write data and a second output from the second latch means. Of the third latch means for latching the data output from the first and second memory parts in synchronization with the clock signal, Fourth latch means for latching an output in synchronization with the clock signal, and a write enable signal for outputting a write enable signal to one of the first memory section or the second memory section to read the other. The semiconductor device characterized by comprising a control means for the to state. 2. The first latch means includes a first latch circuit for latching the write data, a second latch circuit for latching the first address, and a second latch circuit for counting the clock signal. Generate the address of
The semiconductor memory device according to claim 1, further comprising a counter that holds a predetermined period.