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JPH07123188B2 - Method for detecting misalignment of multilayer printed circuit board - Google Patents
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JPH07123188B2 - Method for detecting misalignment of multilayer printed circuit board - Google Patents

Method for detecting misalignment of multilayer printed circuit board

Info

Publication number
JPH07123188B2
JPH07123188B2 JP62025272A JP2527287A JPH07123188B2 JP H07123188 B2 JPH07123188 B2 JP H07123188B2 JP 62025272 A JP62025272 A JP 62025272A JP 2527287 A JP2527287 A JP 2527287A JP H07123188 B2 JPH07123188 B2 JP H07123188B2
Authority
JP
Japan
Prior art keywords
holes
circuit board
misalignment
printed circuit
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62025272A
Other languages
Japanese (ja)
Other versions
JPS63192298A (en
Inventor
秀吉 小林
高明 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP62025272A priority Critical patent/JPH07123188B2/en
Publication of JPS63192298A publication Critical patent/JPS63192298A/en
Publication of JPH07123188B2 publication Critical patent/JPH07123188B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は多層プリント基板の整合ずれを検出する方法
に関する。
The present invention relates to a method for detecting misalignment of a multilayer printed circuit board.

「従来技術の説明」 電気部品をプリント基板に高密度に実装するために、3
層以上の導体層間に絶縁体を介して一体化した多層プリ
ント基板が用いられる。この多層プリント基板は、製造
工程中に導体層が設計された位置からずれてくる場合が
ある。導体層が設計された位置からずれているか否かを
調べる方法として、次の方法がある。
"Explanation of the prior art" To mount electrical parts on a printed circuit board with high density, 3
A multilayer printed circuit board is used in which conductor layers of more than one layer are integrated via an insulator. The multilayer printed circuit board may be displaced from the designed position of the conductor layer during the manufacturing process. There are the following methods for checking whether or not the conductor layer is displaced from the designed position.

複数の導体層を絶縁体を介して一体化してから、各層間
の導体又は多層プリント基板に実装される電気部品とを
電気的に接続するためのスルー・ホールを形成する穴を
開ける。所定の穴に形成されるスルー・ホールを通じて
他の層の導体等と電気的に接続される導体は、この穴の
内面に表出しているはずである。そこで例えば実体顕微
鏡を用いて、各穴の内面に他の層の導体或いは電気部品
と電気的接続されるべき導体が表出しているか否かを穴
を開けた直後に調べることにより、整合ずれを起こして
いるか否かを判断している。しかしある導体が広い領域
に渡って分布している場合、この導体が設定された位置
から大きくずれていてもその整合ずれが許容値以内であ
るかどうか検出できないという問題がある。
A plurality of conductor layers are integrated with each other through an insulator, and then a hole is formed to form a through hole for electrically connecting a conductor between each layer or an electric component mounted on the multilayer printed board. A conductor that is electrically connected to a conductor of another layer or the like through a through hole formed in a predetermined hole should be exposed on the inner surface of this hole. Therefore, for example, by using a stereoscopic microscope, it is possible to check the misalignment by immediately checking whether or not the conductor of another layer or the conductor to be electrically connected to the electric component is exposed on the inner surface of each hole immediately after the hole is formed. It is determined whether or not it is happening. However, when a conductor is distributed over a wide area, there is a problem that it is not possible to detect whether or not the misalignment is within an allowable value even if the conductor largely deviates from the set position.

また穴を開けた後、穴の周辺にX線を照射して導体がど
のように分布しているか調べる方法もある。しかしこの
場合は、多層になればなる程コントラストが弱くなり、
整合ずれを起こしているか否かの判断がむずかしくな
る。
There is also a method of irradiating X-rays around the holes after making the holes to examine how the conductors are distributed. However, in this case, the more layers, the weaker the contrast,
It becomes difficult to judge whether or not there is a misalignment.

更に第3図に示すように、多層プリント基板1の製品外
周部2にクーポン3、4を設けて、整合ずれを起こして
いるか否かを調べる方法もある。
Further, as shown in FIG. 3, there is also a method in which coupons 3 and 4 are provided on the product outer peripheral portion 2 of the multilayer printed circuit board 1 to check whether or not there is a misalignment.

これは回路パターン用の導体の他に、各層毎にクーポン
用の導体を例えばクーポン3、4の実線で示される位置
に配置して絶縁体を介して一体化した後、点線で示す方
向に製品外周部2を切断する。この時切断面は第4図に
示すようになる。ここで整合ずれの大きい導体層3′が
存在する時、このプリント基板を不良品とする。この方
法は、一体化した後にクーポン部分をいちいち切断しな
ければならず、非常に時間がかかるという問題がある。
In this case, in addition to the conductor for the circuit pattern, the conductor for the coupon for each layer is arranged at the position indicated by the solid line of the coupons 3 and 4 and integrated through the insulator, and then the product is moved in the direction indicated by the dotted line. The outer peripheral portion 2 is cut. At this time, the cut surface is as shown in FIG. If there is a conductor layer 3'having a large misalignment, this printed circuit board is regarded as a defective product. This method has a problem that it takes much time to cut the coupon part after each integration.

「問題点を解決するための手段」 この発明による整合ずれ検出方法は、多層プリント基板
の材料収縮又は加工誤差の大きい部分に整合ずれ検出用
パターンを設ける。これは2つのスルー・ホールと、各
々の層に設けられ、一方のスルー・ホールとは電気的に
接続すると共に、他方のスルー・ホールとは許容値xだ
け離れるように設計されている導体とにより構成され
る。従って整合ずれが許容値xより小さい時は2つのス
ルー・ホールは絶縁されているが、許容値xより大きく
なると導通する。このように一対のスルー・ホールが絶
縁されているか否かを調べるだけで良いので、比較的簡
単に許容値x以上の整合ずれを検出できる。
"Means for Solving Problems" In the alignment deviation detection method according to the present invention, the alignment deviation detection pattern is provided in a portion of the multilayer printed circuit board where material shrinkage or processing error is large. This includes two through holes and a conductor that is provided in each layer and is designed to electrically connect one through hole and to separate the other through hole by a tolerance value x. It is composed of Therefore, when the misalignment is smaller than the allowable value x, the two through holes are insulated, but when the misalignment is larger than the allowable value x, the two through holes are electrically connected. Since it is only necessary to check whether or not the pair of through holes are insulated in this way, it is possible to relatively easily detect the misalignment of the allowable value x or more.

「実施例」 第1図に整合ずれ検出用パターンを設けた多層プリント
基板1の上面図を示す。これは材料収縮及び加工誤差の
大きい製品外周部2に8つの整合ずれ検出用パターン5
を設けたものである。各々の整合ずれ検出用パターンは
一対のスルー・ホール6、7を含む。これらのスルー・
ホール6、7は外層部において各々導体8で囲まれてい
るが、互いに絶縁されている。第2図に内層部における
整合ずれ検出用パターン5の設計例を示す。内層部にお
いて、導体9は一方のスルー・ホール7と電気的に接続
するが、他方のスルー・ホール6とは許容値xだけ離れ
るように設計されている。従って設計通りに多層プリン
ト基板が製造された時は、2つのスルー・ホール6と7
は絶縁される。
[Example] Fig. 1 shows a top view of a multilayer printed circuit board 1 provided with a pattern for detecting a misalignment. This consists of eight alignment deviation detection patterns 5 on the outer peripheral portion 2 of the product, which have large material shrinkage and processing errors.
Is provided. Each of the misalignment detection patterns includes a pair of through holes 6 and 7. Through these
The holes 6 and 7 are surrounded by conductors 8 in the outer layer, but are insulated from each other. FIG. 2 shows a design example of the alignment deviation detecting pattern 5 in the inner layer portion. In the inner layer portion, the conductor 9 is designed to be electrically connected to one through hole 7 but separated from the other through hole 6 by an allowable value x. Therefore, when a multilayer printed circuit board is manufactured as designed, two through holes 6 and 7 are formed.
Is insulated.

導体8及び9は、回路パターンの導体と共に絶縁体を介
して一体化される。そして各整合ずれ検出用パターンの
スルー・ホール6及び7に対応する位置に穴を開け、そ
の内面を金属メッキしてスルー・ホール6、7を形成す
る。このスルー・ホール6、7が絶縁されているか否か
を調べることにより、許容値x以上の整合ずれがあるか
否かを調べることができる。即ち、許容値x以上の整合
ずれを起こしている領域がある場合、その部分の整合ず
れ検出用パターン5の一方のスルー・ホール7と電気的
に接続している導体9は、許容値x以上ずれて、他方の
スルー・ホール6とも電気的に接続する。従ってスルー
・ホール6、7が導通して、整合ずれが生じていること
がわかる。
The conductors 8 and 9 are integrated with the conductor of the circuit pattern via an insulator. Then, holes are formed at positions corresponding to the through holes 6 and 7 of each alignment deviation detection pattern, and the inner surfaces of the holes are metal-plated to form the through holes 6 and 7. By checking whether or not the through holes 6 and 7 are insulated, it is possible to check whether or not there is a misalignment of the allowable value x or more. That is, when there is a region where the misalignment of the allowable value x or more occurs, the conductor 9 electrically connected to one of the through holes 7 of the misalignment detecting pattern 5 at that portion has the allowable value x or more. It shifts and is also electrically connected to the other through hole 6. Therefore, it can be seen that the through holes 6 and 7 are brought into conduction and a misalignment occurs.

第1図及び第2図では、外層部において一方のスルー・
ホール6を電気的に共通接続すると共に、内層部におい
て他方のスルー・ホール7を電気的に共通接続してい
る。従って1箇所で許容値x以上の整合ずれが生じた場
合、全ての整合ずれ検出用パターン5において2つのス
ルー・ホール6、7が電気的に接続される。即ち、いず
れか1つの整合ずれ検出用パターンのスルー・ホール
6、7の絶縁状態を測定することにより、多層プリント
基板全体に整合ずれが生じているか否かを判断すること
ができる。
In Fig. 1 and Fig. 2, one through
The holes 6 are electrically commonly connected, and the other through hole 7 is electrically commonly connected in the inner layer portion. Therefore, when the misalignment of the allowable value x or more occurs at one location, the two through holes 6 and 7 are electrically connected in all the misalignment detection patterns 5. That is, by measuring the insulation state of the through holes 6 and 7 of any one of the misalignment detection patterns, it is possible to determine whether the misalignment has occurred in the entire multilayer printed circuit board.

「発明の効果」 以上説明したようにこの発明では、一対のスルー・ホー
ルと、各々の層において上記一対のスルー・ホールの内
一方のスルー・ホールと電気的に接続すると共に、他方
のスルー・ホールとは許容値だけ離れるほうに設計され
た導体とから成る整合ずれ検出用パターンを、多層プリ
ント基板の作成と並行して作成する。そして上記一対の
スルー・ホールの絶縁状態を調べることにより、整合ず
れが生じているか否かを判断しているので、比較的簡単
な方法で確実に整合ずれを検出することができる。
As described above, in the present invention, the pair of through holes and one of the pair of through holes in each layer are electrically connected and the other through hole is formed. A misalignment detection pattern composed of a conductor designed to be separated from the hole by an allowable value is created in parallel with the creation of the multilayer printed board. Then, by checking the insulation state of the pair of through holes to determine whether or not the misalignment occurs, it is possible to reliably detect the misalignment by a relatively simple method.

【図面の簡単な説明】[Brief description of drawings]

第1図はこの発明の一実施例を示す整合ずれ検出用パタ
ーンを設けた多層プリント基板の上面図、第2図は上記
の多層プリント基板の内層部における整合ずれ検出用パ
ターンを構成している導体の配置例を示す断面図、第3
図はクーポンを設けた多層プリント基板の上面図、第4
図は第3図に示した多層プリント基板のクーポンの部分
を破壊した時の一例を示す断面図である。
FIG. 1 is a top view of a multilayer printed circuit board provided with an alignment deviation detection pattern showing an embodiment of the present invention, and FIG. 2 constitutes an alignment deviation detection pattern in an inner layer portion of the multilayer printed board. Sectional view showing an example of arrangement of conductors, third
The figure shows a top view of a multilayer printed circuit board with coupons, 4th
The drawing is a cross-sectional view showing an example when the coupon portion of the multilayer printed circuit board shown in FIG. 3 is broken.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】A.各々の対における一方のスルー・ホール
は全て電気的に接続され、他方のスルー・ホールは上記
一方のスルー・ホールから電気的に絶縁されている、複
数対のスルー・ホールと、 B.各々の層間に配設され、上記各他方のスルー・ホール
と電気的に接続すると共に、上記各一方のスルー・ホー
ルとは整合ずれ許容値だけ離れるよう構成され、且つ電
気的に一体化された導体と、 から成る整合ずれ検出用パターンを多層プリント基板の
作成と並行して作成し、上記複数対のスルー・ホールの
うちのいずれかの上記一方のスルー・ホールと上記他方
のスルー・ホールが絶縁されているか否かを調べること
により、整合ずれを検出するようにしたことを特徴とす
る多層プリント基板の整合ずれ検出方法。
1. A. Multiple pairs of through holes, wherein one through hole in each pair is all electrically connected and the other through hole is electrically isolated from said one through hole. B. is arranged between the respective layers, and is electrically connected to each of the other through holes, and is configured to be separated from the one of the through holes by an alignment deviation allowable value and electrically. And a matching deviation detecting pattern consisting of a conductor integrated with the conductor are formed in parallel with the formation of the multilayer printed circuit board, and one of the plurality of pairs of through holes and one of the above through holes and the other of the above through holes are formed. A misalignment detection method for a multilayer printed circuit board, characterized in that the misalignment is detected by checking whether or not the through-holes are insulated.
JP62025272A 1987-02-05 1987-02-05 Method for detecting misalignment of multilayer printed circuit board Expired - Lifetime JPH07123188B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62025272A JPH07123188B2 (en) 1987-02-05 1987-02-05 Method for detecting misalignment of multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62025272A JPH07123188B2 (en) 1987-02-05 1987-02-05 Method for detecting misalignment of multilayer printed circuit board

Publications (2)

Publication Number Publication Date
JPS63192298A JPS63192298A (en) 1988-08-09
JPH07123188B2 true JPH07123188B2 (en) 1995-12-25

Family

ID=12161393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62025272A Expired - Lifetime JPH07123188B2 (en) 1987-02-05 1987-02-05 Method for detecting misalignment of multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPH07123188B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6215636B2 (en) * 2013-10-01 2017-10-18 京セラ株式会社 Multiple wiring board

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55102300A (en) * 1980-01-21 1980-08-05 Hitachi Ltd Method of detecting inner layer pattern position for multilayer printed board
JPS5933898A (en) * 1982-08-20 1984-02-23 沖電気工業株式会社 Method of testng multilayer printed circuit board

Also Published As

Publication number Publication date
JPS63192298A (en) 1988-08-09

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