JPH0714003B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0714003B2 JPH0714003B2 JP61034659A JP3465986A JPH0714003B2 JP H0714003 B2 JPH0714003 B2 JP H0714003B2 JP 61034659 A JP61034659 A JP 61034659A JP 3465986 A JP3465986 A JP 3465986A JP H0714003 B2 JPH0714003 B2 JP H0714003B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter region
- semiconductor device
- region
- darlington
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/641—Combinations of only vertical BJTs
- H10D84/642—Combinations of non-inverted vertical BJTs of the same conductivity type having different characteristics, e.g. Darlington transistors
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置、詳しくは、ダーリントン結合の
複数トランジスタの構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a structure of a plurality of Darlington-coupled transistors.
従来の技術 従来、オーディオ用ダーリントン・トランジスタは、縦
電流を少なくするために、PNP/NPNトランジスタの電流
増幅率を同じ値のものにする方式が取られていた。2. Description of the Related Art Conventionally, in audio Darlington transistors, a method has been adopted in which the current amplification factor of the PNP / NPN transistor is set to the same value in order to reduce the vertical current.
発明が解決しようとする問題点 しかし上述の方式では、ダーリントン・トランジスタの
ため、PNPトランジスタとNPNトランジスタの電流増幅率
を大きく、しかも同じ値にすることが、困難であり、ま
た同じ電流増幅率でも周波数が高くなると、第２図の特
性図のように、実動作のクロスオーバー時に、縦電流が
増加するという問題点があった。Problems to be Solved by the Invention However, in the above method, since the Darlington transistor is used, it is difficult to make the current amplification factors of the PNP transistor and the NPN transistor large, and it is difficult to obtain the same value. As the frequency increases, there is a problem that the vertical current increases at the crossover of the actual operation as shown in the characteristic diagram of FIG.
本発明は、上述の従来例にみられた問題点で解消をはか
る半導体装置を実現するものである。The present invention realizes a semiconductor device that solves the problems found in the above-mentioned conventional example.
問題点を解決するための手段 本発明は、ダーリントン結合された複数トランジスタの
うち、前段トランジスタにそのエミッタ領域を囲んで、
同エミッタ領域と同導電型の分離領域を有し、この分離
領域が前記前段トランジスタのベース電極に結線された
ものである。Means for Solving the Problems The present invention relates to a plurality of Darlington-coupled transistors, in which the emitter region is surrounded by a preceding transistor,
The emitter region and the isolation region of the same conductivity type are provided, and the isolation region is connected to the base electrode of the preceding stage transistor.
作用 本発明によると、ダーリントン・トランジスタの前段ト
ランジスタにおいては、エミッタ領域を囲むように、形
成された分離領域をベース電極と結線したことにより、
前段トランジスタは、スイッチング時間の一部である蓄
積時間tsが短くなる。この特性により、オーディオの実
動作時に周波数が変化しても、蓄積時間tsが短いため、
クロスオーバ時の縦電流が少なく押えられる。またPNP/
NPNの電流増幅率の差が大きい場合も、蓄積時間tsが短
かいため、縦電流は小さく押える事が可能であり、電流
増幅率の許容範囲を大きくすることができる。Action According to the present invention, in the preceding stage transistor of the Darlington transistor, by connecting the formed isolation region to the base electrode so as to surround the emitter region,
The pre-stage transistor has a shorter storage time ts which is a part of the switching time. Due to this characteristic, the accumulation time ts is short even if the frequency changes during the actual operation of the audio.
Holds down the vertical current at crossover. Also PNP /
Even when the difference in the current amplification factor of the NPN is large, since the accumulation time ts is short, the vertical current can be suppressed small, and the allowable range of the current amplification factor can be increased.
実施例 つぎに本発明を実施例により詳しく述べる。EXAMPLES Next, the present invention will be described in more detail with reference to Examples.
第１図は本発明実施例半導体装置の断面図である。コレ
クタ領域となるＮ型シリコン基板上にＰ型ベース領域２
を形成する、次にエミッタ領域３を形成するに際し、エ
ミッタ領域３を囲むように分離領域（以後分離エミッタ
領域と記す）4,5を同時に形成する。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. A P-type base region 2 on the N-type silicon substrate which becomes the collector region
When the emitter region 3 is formed next, isolation regions (hereinafter referred to as isolation emitter regions) 4 and 5 are simultaneously formed so as to surround the emitter region 3.
その後エミッタ電極6,ベース電極7,コレクタ電極8,内部
電極配線９を形成する。またこの際にベース電極７は、
分離エミッタ領域５と結線する。なお、表面には絶縁膜
10を設けている。After that, the emitter electrode 6, the base electrode 7, the collector electrode 8 and the internal electrode wiring 9 are formed. At this time, the base electrode 7 is
It is connected to the separate emitter region 5. An insulating film is formed on the surface.
10 are provided.
この実施例構造によると、ダーリントン・トランジスタ
の蓄積時間tsを短かくすることができる。これは、分離
エミッタ５をベース電極７と結線することにより、分離
エミッタ領域５、ベース領域２、およびシリコン基板１
で構成される寄生トランジスタが部分的に動作し、スイ
ッチングオフ時に寄生トランジスタを介して電流が流れ
るため、蓄積時間が短かくなるという利点がある。また
後段トランジスタ内の分離エミッタ領域４は同トランジ
スタ破壊耐量の向上にのみ動作する。後段トランジスタ
は回路構成上、蓄積時間は存在しないので、分離エミッ
タ領域５と同様な結線にする必要はない。According to the structure of this embodiment, the storage time ts of the Darlington transistor can be shortened. This is because by connecting the separation emitter 5 to the base electrode 7, the separation emitter region 5, the base region 2, and the silicon substrate 1 are connected.
Since the parasitic transistor composed of 1 operates partially and a current flows through the parasitic transistor at the time of switching off, there is an advantage that the accumulation time becomes short. Further, the separation emitter region 4 in the latter stage transistor operates only for improving the breakdown resistance of the same transistor. Since the latter stage transistor has no storage time in terms of the circuit configuration, it is not necessary to make the same connection as that of the separation emitter region 5.
本発明は、上記実施例半導体装置に限られるものではな
く、種々の変形あるいは応用が可能である。たとえば実
施例ではNPNダーリントン・トランジスタについて説明
したが、PNPダーリントン・トランジスタにも適用可能
である。The present invention is not limited to the semiconductor device of the above embodiment, but various modifications and applications are possible. For example, although the NPN Darlington transistor has been described in the embodiment, it can be applied to a PNP Darlington transistor.
発明の効果 本発明によれば、オーディオ用ダーリントン・トランジ
スタの前段トランジスタの蓄積時間が短かくなり、これ
により実動作のクロスオーバ時に発生する縦電流を少な
くでき、トランジスタの発熱を押えるとともに、破壊耐
量の向上が可能となる。EFFECTS OF THE INVENTION According to the present invention, the storage time of the preceding stage transistor of the audio Darlington transistor is shortened, and thus the vertical current generated at the crossover of the actual operation can be reduced, the heat generation of the transistor can be suppressed, and the breakdown resistance can be reduced. Can be improved.
第１図は本発明の一実施例半導体装置の断面図、第２図
は実動作のクロスオーバ時における縦電流波形を示す波
形図である。 １……Ｎ型シリコン基板、２……Ｐ型ベース領域、３…
…Ｎ型エミッタ領域、４……Ｎ型分離エミッタ領域、５
……Ｎ型分離エミッタ領域、６……エミッタ電極、７…
…ベース電極、８……コレクタ電極、９……内部電極配
線、10……絶縁物。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram showing a vertical current waveform at a crossover of an actual operation. 1 ... N-type silicon substrate, 2 ... P-type base region, 3 ...
... N-type emitter region, 4 ... N-type separation emitter region, 5
... N-type separation emitter region, 6 ... Emitter electrode, 7 ...
... base electrode, 8 ... collector electrode, 9 ... internal electrode wiring, 10 ... insulator.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/73 (72)発明者 大濱 泰造 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (56)参考文献 特開 昭54−104780（ＪＰ，Ａ)─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 6 Identification number Internal reference number FI Technical indication location H01L 29/73 (72) Inventor Taizo Ohama 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-54-104780 (JP, A)
Claims (1)
のうちの前段トランジスタに、そのエミッタ領域を囲ん
で、同エミッタ領域と同導電型の分離領域を有し、この
分離領域が前記前段トランジスタのベース電極に結線さ
れた半導体装置。1. A pre-stage transistor of a plurality of Darlington-coupled transistors has an isolation region surrounding the emitter region and having the same conductivity type as the emitter region, and the isolation region serves as a base electrode of the pre-stage transistor. Connected semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61034659A JPH0714003B2 (en) | 1986-02-18 | 1986-02-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61034659A JPH0714003B2 (en) | 1986-02-18 | 1986-02-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62190861A JPS62190861A (en) | 1987-08-21 |
| JPH0714003B2 true JPH0714003B2 (en) | 1995-02-15 |
Family
ID=12420567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61034659A Expired - Lifetime JPH0714003B2 (en) | 1986-02-18 | 1986-02-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0714003B2 (en) |
-
1986
- 1986-02-18 JP JP61034659A patent/JPH0714003B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62190861A (en) | 1987-08-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |