JPH0714038B2 - Semiconductor memory device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor memory device, and more particularly to a random access memory using a bipolar transistor.

[Conventional technology]

FIG. 2 is a structural cross-sectional view of a part of a semiconductor memory device composed of a bipolar transistor according to the prior art.

In FIG. 2, S indicated by a dotted line is a transistor in the peripheral circuit portion, M is a memory cell portion, and these are formed on the same substrate. An equivalent circuit of the memory cell section M is shown in FIG.

In FIG. 2, an N ⁺ -type buried layer 2 is formed on a P ⁻ -type substrate 1, and an N ⁻ -type epitaxial layer 3 is formed on the N ⁺ -type buried layer 2.
And the P ⁺ type base diffusion region 4 is formed on the N ⁻ type epitaxial layer 3, and the N ⁺ type emitter regions 5a, 5b, 5c are formed in the P ⁺ type base diffusion region 4. Has been done. 6a to 6h are Al wirings, 6a and 6f are connected to the collector, 6c and 6h are connected to the base, 6b, 6d and 6g are connected to the emitter, and 6e is connected to the positive word line. Reference numerals 7 and 8 are oxide films, and the peripheral circuit portion S and the memory cell portion M are separated by the oxide film 8. Further, 9 is a Schottky barrier diode, and 10 is a resistance which becomes a load of the memory cell. Reference numeral 18 denotes a guard ring formed by a P ⁺ type diffusion layer formed around the contact portion of the Schottky barrier diode 9.

FIG. 3 shows a diode clamp type memory cell, which is a multi-emitter transistor 11a for reading / writing stored information,
Load resistors 10a and 10b, Schottky barrier diodes 9a and 9b, and pn junction diodes 18a and 18b formed by a guard ring are connected in parallel to respective collectors of 11b to form a flip-flop. 6 is the positive word line, 12
Is a negative-side word line, which is connected to a constant current source (not shown) for memory retention and draws a constant current from each memory cell. Bits 13a and 13b are connected to one of the emitters of the multi-emitter transistors 11a and 11b. Also, 14a and 14b are Schottky barrier diodes 9
The sum of the connection capacitance C _SBD of a and 9b and the junction capacitance C _PN of the PN junction diodes 18a and 18b, and 15a and 15b are multi-emitter transistors 11
Base-collector junction capacitance C _{TC of} a and 11b, 16a and 16b are base-emitter junction capacitance C _TE of multi-emitter transistors 11a and 11b, and 17a and 17b are multi-emitter transistor 11a and
11b is a junction capacitance (hereinafter referred to as "collector substrate junction capacitance") C _TS between the collector and the substrate 1.

Now referring to FIG. 3, the multi-emitter transistor 11a
Is off and 11b is on. At this time, the potential of the collector node N of the multi-emitter transistor 11a is changed to
The potential of V _N and the collector node M of the multi-emitter transistor 11b is V _M, and this is the first storage state. Normally, the potential difference between the collector nodes N and M (hereinafter referred to as the hold voltage V _{H of} the memory cell) is about V _N −V _M = 0.3 V, and V _N and V _M are voltage drops due to the load resistors 10a and 10b, respectively. It is a value determined by.

When α rays pass through the semiconductor in this state, electron-hole pairs are generated, but the electron-hole pairs generated in the depletion layer instantaneously flow into the P-type region and electrons into the N-type region, It becomes a noise current. Assuming that the charge generated by the entry of α rays is Q, the potential levels of the collector nodes N and M are instantly Q
And a voltage determined by the capacitance C applied to the collector nodes N and M. The hold voltage V _H ′ at this moment is However, C = C _TS + C _SBD + 4C _TC + 2C _TE + C _PN . In this case V _H '<0 become the magnitude relationship between the potential of the collector node N and M is V _N> would be inverted from the V _M to V _N <V _M, that is, the storage state of the memory cell is inverted. In order to keep V _H ′> 0 even if α rays enter and generate electric charge, V _H · C
It may be> Q. That is, the hold voltage V _H may be increased and the capacitance C may be increased within the range of power consumption.

In the prior art, as shown in FIG. 2, the area of the Schottky barrier diode is reduced by forming the guard ring of the P ⁺ type diffusion layer 18 around the contact of the Schottky barrier diode 9, so that the PN junction diode is reduced. Are inserted in parallel, the forward voltage of the Schottky barrier diode is increased and the hold voltage V _H of the memory cell is increased. In addition, the PN junction formed by the guard ring increases the parasitic capacitances 14a and 14b shown in FIG. The PN junction capacitance increases as the P-type impurity concentration of the guard ring increases.

Further, as shown in FIG. 2, by making the thickness of the N ⁻ type epitaxial layer 3 of the memory cell portion M smaller than that of the peripheral circuit portion S, the collector at the base-collector junction of only the memory cell portion M is formed. The N-type impurity concentration on the side is increased to increase the base-collector junction capacitance C _TC .

In the prior art, the method described above makes it difficult to cause the information inversion of the memory cell due to the entry of α rays.

[Problems to be solved by the invention]

As described above, in the conventional semiconductor memory device, the thickness of the N ⁻ type epitaxial layer of the memory cell portion M is made smaller than that of the peripheral circuit portion, so that the N type impurity on the collector side at the base-collector junction is formed. Although increasing the concentration to increase the junction capacitance C _TC , if the impurity concentration in the PN junction increases, the width of the depletion layer between the base and collector narrows, and the electric field applied to the depletion layer during reverse bias increases. There is a drawback that the electrical breakdown voltage in the reverse direction is reduced.

The present invention has been made to solve the above problems, and provides a semiconductor memory device in which information inversion due to α-rays or the like does not easily occur without lowering the reverse electrical breakdown voltage between the base and collector. Is intended.

[Means for solving problems]

A semiconductor memory device according to the present invention includes a semiconductor substrate of a first conductivity type and a first substrate on which a peripheral circuit portion of the semiconductor substrate is to be formed.
A first epitaxial growth layer of a second conductivity type formed in the active region of the second conductivity type, and a peripheral circuit composed of a first bipolar transistor having the first epitaxial growth layer of the second conductivity type as a collector layer; Of semiconductor substrate,
A second conductive type second epitaxial growth layer formed in a second active region in which a memory cell portion other than the peripheral circuit portion is to be formed, and a part of which has a thickness smaller than that of the first epitaxial growth layer; A second bipolar transistor having the second conductivity type second epitaxial growth layer as a collector layer and the first conductivity type diffusion region formed in the collector layer as a base layer; and the second epitaxial growth layer comprising: A plurality of memory cells each having a Schottky barrier diode formed in a portion having a small thickness and having a Schottky junction formed with the second epitaxial growth layer; and an external base region of the second bipolar transistor. A thin thickness of the second epitaxial growth layer, which constitutes a guard ring surrounding the Schottky junction. It is obtained so as to provide a diffusion layer of the first conductivity type formed in a portion having a.

Further, in the semiconductor memory device according to the present invention, a buried layer of the second conductivity type is formed between the second epitaxial growth layer of the second conductivity type and the semiconductor substrate of the first conductivity type. The part of the epitaxial growth layer having a small thickness is configured such that the bottom surface of the diffusion layer of the first conductivity type is in contact with the buried layer of the second conductivity type.

[Action]

Since the semiconductor memory device of the present invention has the above-mentioned configuration, it is possible to increase the junction capacitance of the guard ring portion without lowering the reverse electrical breakdown voltage between the base and collector of the transistor portion, and to use the guard ring. The forward voltage of the Schottky barrier diode can be increased to increase the hold voltage of the memory cell, high-speed operation can be performed, and a strong resistance to information inversion due to α rays or the like can be obtained.

Further, in the semiconductor memory device of the present invention, because of the above-mentioned configuration, the decrease in the breakdown voltage between the base and collector of the bipolar transistor in the memory cell portion is prevented, and the second conductivity type second transistor of the bipolar transistor portion is prevented. The decrease in capacitance due to the thicker epitaxial growth layer is compensated for.

Example of Invention

An embodiment of the semiconductor memory device according to the present invention is shown in FIG. In FIG. 1, S indicated by a dotted line indicates a transistor in the peripheral circuit portion and M indicates a memory cell portion, which are formed on the same substrate. The equivalent circuit of the memory cell section M is as shown in FIG. In FIG. 1, P ^- type substrate 1 on which is N ⁺ -type buried layer 2 is formed, N on the N ⁺ -type buried layer 2 ^- -type epitaxial layer 3 is formed, N ^-
A P ⁺ type base diffusion region 4 is formed on the type epitaxial layer 3, and N ⁺ type emitter regions 5a, 5b, 5c are formed in the P ⁺ type base diffusion region 4. 6a to 6h are Al wiring,
6a and 6f are connected to the collector, 6c and 6h are connected to the base, 6b, 6d and 6g are connected to the emitter, and 6e is connected to the positive side word line. Reference numerals 7 and 8 are oxide films, and the peripheral circuit portion S and the memory cell portion M are separated by the oxide film 8. Further, 9 is a Schottky barrier diode, and 10 is a resistance which becomes a load of the memory cell. Reference numeral 18 is a guard ring formed of a P ⁺ type diffusion layer formed around the contact portion of the Schottky barrier diode 9, and 3a is an N ⁻ type epitaxial layer of the guard ring portion.

In the device of this embodiment shown in FIG. 1, the memory cell unit M
Since the N ⁻ type epitaxial layer 3a of the P ⁺ type guard ring 18 portion in the inside is made thinner than the transistor portion, the P ⁺ type diffusion layer 18 of the guard ring portion is the N ⁺ type buried layer 2 of high impurity concentration. Since a junction is formed with, the junction capacitance increases. However,
Since the thickness of the N ⁻ type epitaxial layer 3 of the transistor portion is the same as that of the peripheral circuit portion S, the reverse electric breakdown voltage between the base and collector does not decrease. However, by making the thickness of the N ⁻ -type epitaxial layer 3 of the transistor section thinner than that of the peripheral circuit section S to the extent that the reverse electric breakdown voltage between the base and collector does not fall below the allowable range, It is effective to increase the junction capacitance C _TC between the collectors.

Further, the effect that the area of the Schottky barrier diode 9 is reduced by the guard ring 18 and the forward voltage is increased, and the hold voltage V _H of the memory cell is increased, the guard ring is provided around the Schottky barrier diode. It is similar to the prior art.

As described above, in the device of the present embodiment, the junction capacitance can be increased and the hold voltage of the memory cell can be increased without lowering the reverse electrical breakdown voltage between the base and collector of the transistor in the memory cell. It is possible to obtain a highly reliable semiconductor memory device in which information inversion due to lines or the like is unlikely to occur.

Needless to say, any method may be used to reduce the thickness of the N ⁻ type epitaxial layer in the guard ring 18 portion as compared with the transistor portion.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, the semiconductor substrate of the first conductivity type and the second semiconductor substrate formed in the first active region where the peripheral circuit portion is to be formed.
A first epitaxial growth layer of conductivity type and a first epitaxial growth layer of second conductivity type as a collector layer
And a peripheral circuit formed by the bipolar transistor and a part of the semiconductor substrate, which is thinner than the first epitaxial growth layer, in a second active region where a memory cell part other than the peripheral circuit part is to be formed. A second conductive type second epitaxial growth layer having a thickness, and the second conductive type second epitaxial growth layer as a collector layer,
And a second bipolar transistor having the first conductivity type diffusion region formed in the collector layer as a base layer, and the second epitaxial growth layer formed on a part of the second epitaxial growth layer having a small thickness. A plurality of memory cells each having a Schottky barrier diode formed by forming a Schottky junction, an external base region of the second bipolar transistor, and a guard ring surrounding the Schottky junction.
Since the diffusion layer of the first conductivity type formed on a part of the second epitaxial growth layer having a small thickness is provided, the base-collector junction capacitance of the memory cell portion is larger than that of the peripheral circuit portion. It is possible to simultaneously satisfy the contradictory requirements of increasing resistance to inversion of information and speeding up the operation, and by using the high impurity concentration first conductivity type guard ring provided around the Schottky barrier diode. Since the hold voltage of the memory cell can be further increased and the base-collector junction capacitance can be further increased, it is possible to obtain a semiconductor memory device that operates at high speed and has high reliability. .

Also, according to the semiconductor memory device of the present invention, a buried layer of the second conductivity type is formed between the second epitaxial growth layer of the second conductivity type and the semiconductor substrate of the first conductivity type, Since a part of the second epitaxial growth layer having a small thickness is configured such that the bottom surface of the first conductivity type diffusion layer is in contact with the second conductivity type buried layer, the memory cell portion is formed. The effect of preventing a decrease in the base-collector withstand voltage of the bipolar transistor can be compensated for, and a decrease in the capacitance due to the thickening of the second conductivity type second epitaxial growth layer in the bipolar transistor portion can be compensated.

[Brief description of drawings]

1 is a sectional view showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a sectional view showing a conventional semiconductor memory device,
FIG. 3 is a circuit diagram showing a diode clamp type memory cell. M ... Memory cell part, S ... Peripheral circuit part, 1 ... P ^- type substrate, 2
... N ⁺ type buried layer, 3 ... N ^- type epitaxial layer, 4 ... P ⁺ type base diffusion region, 5a to 5c ... N ⁺ type emitter region, 6a to 6h ... Al
Wiring, 7, 8 ... Oxide film, 9 ... Schottky barrier diode, 10 ... Resistor, 18 ... P ⁺ type diffusion layer for guard ring.

Claims (2)

[Claims] 1. A first conductivity type semiconductor substrate, a second conductivity type first epitaxial growth layer formed in a first active region of the semiconductor substrate where a peripheral circuit portion is to be formed, and A peripheral circuit constituted by a first bipolar transistor having a collector layer of the first epitaxial growth layer of two conductivity type, and a second active region of the semiconductor substrate where a memory cell portion other than the peripheral circuit portion is to be formed. A second part which is formed in the first part and has a thickness smaller than that of the first epitaxial growth layer.
A second epitaxial growth layer of conductivity type, a second epitaxial growth layer of second conductivity type as a collector layer, and a second diffusion layer of the first conductivity type formed in the collector layer as a base layer. A bipolar transistor and a plurality of memory cells each having a Schottky barrier diode formed in a part of the second epitaxial growth layer having a small thickness and forming a Schottky junction with the second epitaxial growth layer; A diffusion layer of the first conductivity type formed in a thin portion of the second epitaxial growth layer, which constitutes an external base region of the second bipolar transistor and constitutes a guard ring surrounding the Schottky junction. A semiconductor memory device comprising: 2. A buried layer of the second conductivity type is formed between the second epitaxial growth layer of the second conductivity type and the semiconductor substrate of the first conductivity type, and the second epitaxial growth layer is thin. 2. The semiconductor according to claim 1, wherein a part of the thickness is such that the bottom surface of the diffusion layer of the first conductivity type is in contact with the buried layer of the second conductivity type. Storage device.