JPH0714060B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an ultrafine complementary type capable of forming a well ground electrode in a self-aligned manner in relation to the gate electrode of a transistor in a well. The present invention relates to a method for manufacturing a semiconductor device capable of easily manufacturing an insulated gate field effect transistor, an ultrafine non-volatile memory transistor using a well, or the like.

[Background of the Invention]

Conventional complementary insulated gate field effect transistor (hereafter CM
It is called an OS transistor. ) Has a high-concentration diffusion region having the same conductivity type as that of the well for taking out the well ground electrode, and a source and drain of a transistor formed in the well having a conductivity type opposite to the well. , Were formed independently of each other. That is, FIG. 1 is a sectional view showing a part of a conventional CMOS transistor, where 1 is an n-type silicon substrate and 2 is a p-type well region. In the well 2, there are a p-type high-concentration impurity diffusion region 4 formed by using a thick film oxide film 3 for element isolation as a mask, and a source region 5 and a drain region 6 of a transistor composed of an n-type high-impurity diffusion region. Has been formed. The source diffusion region 5 and the drain diffusion region 6 are formed by masking the gate oxide film 7 and the gate electrode 8. 9
Is a surface stabilizing insulating film. The p-type high-concentration impurity diffusion region 4 and the n-type source diffusion region 5 are connected by the metal electrode 10 and fixed to the ground potential. The drain diffusion region 6 is CMOS
It is connected to the drain diffusion layer of the p-channel transistor that constitutes the transistor by the metal electrode 11 and serves as the output terminal of the CMOS transistor. In the CMOS transistor of the conventional structure as shown in the partial cross-sectional view of FIG. 1, the diffusion region 4 for giving the well potential is formed independently of the source diffusion region 5. That is, in order to form the p-type high impurity concentration diffusion region 4 that gives the well potential, the existence of the field region 3 of the oxide film for isolation from the n-type source region 5 is indispensable, which is a drawback in miniaturization. . If the number of the high-concentration diffusion regions 4 providing the well potential is reduced (for example, the high-concentration diffusion region 4 provided for each transistor in one well is replaced with one high-concentration diffusion region per well). The treatment of (1) is reduced. However, in this case, the distance from the p-type diffusion region 4 varies depending on the position of the transistor in the well 2, so that the threshold voltage value of each transistor varies due to the effect of the well resistance.

In the CMOS transistor of the conventional structure, the p-type diffusion region 4 and n
The same potential (ground potential) is applied to the mold source region 5, but holes are separately formed and the wiring electrodes are connected to each other, so that other drawbacks occur. That is, in order to provide each opening at a desired position, it is necessary to secure a margin for positional displacement, which leads to an increase in area. Further, if the area of the opening is reduced to aim at the area reduction, the defective processing of the opening is increased and the probability of connection failure is increased.

[Object of the Invention]

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to dramatically reduce the area occupied by each diffusion region having different conductivity types in the well and to which the same potential is applied. is there. Still another object of the present invention is to provide a method of manufacturing a semiconductor device which can reduce the number of electrode connection openings and the occupied area including the alignment margin thereof, and can form CMOS transistors and the like extremely finely. To do.

[Outline of Invention]

In order to achieve the above object, the present invention configures the diffusion region 4 of the same conductivity type as that of the well to which the well potential is applied in a self-aligned relationship with the source diffusion region 5 of the in-well transistor. That is, the conventional well-known self-aligned gate transistor has the source diffusion region 5 and the drain diffusion region 6 in a self-aligned relationship with the end of the gate electrode 8, but in the present invention, the diffusion region 4 which gives a well potential. Also has a self-aligned relationship with the end of the gate electrode 8.

That is, the diffusion region 4 is formed so as to be separated from the gate electrode 8 by the insulating film thickness provided on the gate electrode 8. In order to realize the above self-aligned structure, in the present invention, after forming the gate electrode and its sidewall insulating film, a diffusion blocking film such as a silicon nitride film is self-aligned with the sidewall insulating film and formed. Leave it selectively. The selective remaining of the diffusion blocking film is left on the sidewall portion of the gate electrode and the gate sidewall insulating film by controlling the film thickness of the thin film such as silicon deposited on the diffusion blocking film and controlling the anisotropic etching amount thereof. The thin film thickness of silicon or the like may be controlled. That is, if the remaining silicon thin film is used as a mask for processing, the diffusion blocking film can be selectively left in a self-aligned manner with the gate electrode.

The gas forming the diffusion regions 4 and 5 before and after the selective remaining of the diffusion blocking film is diffused to give a well potential if the diffusion regions 4 and 5 are formed before and after the removal of the selectively left diffusion blocking film. The region 4 is also formed in self alignment with the gate electrode 8. After forming the two diffusion regions having different conductivity types as described above, metal wiring may be directly applied to the surface of each diffusion region, or each diffusion region surface may be silicidized and electrically connected. In the structure of the present invention, the two diffusion regions 4 and 5 having different conductivity types are in contact with each other, but in the case of a semiconductor device which gives an equal potential to both such as a CMOS transistor, no trouble occurs. Further, in forming diffusion layers having different conductivity types, the formation of one diffusion layer acts to compensate or eliminate the other diffusion layer formation region, but the diffusion coefficient of impurities forming each diffusion layer If the impurity material is selected and the manufacturing conditions are set in consideration of the difference and the implantation energy condition of the impurity ion implantation, no problem occurs.

Hereinafter, the present invention will be described in more detail with reference to Examples. For convenience of explanation, the description will be made with reference to the drawings, but attention must be paid because the main part is shown enlarged.

Example of Invention

Embodiment 1 FIGS. 2 to 4 are views showing an embodiment of a semiconductor device according to the present invention. First, the p-type well region 2, the n-type well region 12, and the element isolation insulating film 3 were formed on the highly-intrinsic high-resistance silicon substrate 1'using a known technique. Although the element isolation insulating film 3 is formed by the buried insulating film method, it may be formed by a normal selective oxidation method (LOCOS method). After forming the well regions 2 and 12, etc., a gate oxide film 7 having a thickness of 15 nm, a gate electrode 8 made of tungsten (W), and a gate made of a silicon oxide film to which phosphorus is slightly added are formed according to a known MOS transistor manufacturing method. The protective insulating film 15 was formed. The gate protection insulating film 15 was simultaneously processed by the same mask when the gate electrode 8 was etched. After processing the gate electrode 8 and the gate protection insulating film 15, a silicon oxide film 16 with a slight addition of phosphorus was deposited on the entire surface to a thickness of 0.2 μm. Then, etching is advanced in a direction perpendicular to the surface of the silicon substrate by reactive sputtering to remove the silicon oxide film 16 deposited on the flat portion, and the silicon oxide film 16 is left only on the side wall of the gate electrode 8. Next, the n-type well region 12 is covered with a photoresist film, and the p-type well region 12 is formed.
Arsenic (As) was implanted by ion implantation only in. Although the above-mentioned implantation is performed through the gate oxide film 7, the gate electrode 8 serves as a mask for ion implantation, and As ions are not implanted into the silicon substrate portion immediately below. After the above ion implantation, the photoresist film was removed, and the activation heat treatment was performed to form the n-type source diffusion layer region 5 and the drain diffusion layer region 6. A p-type source diffusion layer region 14 and a drain diffusion layer region 13 were formed in the n-type well region 12 by the same manufacturing method by ion implantation of boron (B). Then, a silicon nitride film (Si ₃ N ₄ ) 17 having a thickness of 0.15 μm, and
A 0.3 μm thick silicon thin film 18 was continuously deposited on the entire surface (FIG. 2).

Next, etching is advanced again only in the direction perpendicular to the surface of the silicon substrate by the reactive sputtering method to remove the silicon thin film 18 deposited on the flat portion, so that only the side wall of the silicon oxide film 16 on the side wall of the gate electrode 8 is covered with silicon. Thin film 18
Was left behind. The exposed silicon nitride film 17 was removed by hot phosphoric acid (H ₃ PO ₄ ) using the silicon thin film 18 left in this state as a mask (FIG. 3).

Then, the remaining silicon thin film 18 was entirely removed by a hydrazine (N ₂ H ₂ ) solution. In the above state, the silicon nitride film 17 is the silicon oxide film on the side wall of the gate electrode 8.
A width of about 0.3 μm from the end of 16 is left in self-alignment with the silicon oxide film 16 and the gate electrode 17. Next, the p-type well region 2 is covered with a photoresist film, and the n-type well region is formed.
Phosphorus (P) is ion-implanted only in 12. In the above ion implantation, the silicon substrate below the remaining silicon nitride film 17 is not implanted, and the junction depth is already formed in the silicon substrate in the region where the silicon nitride film does not exist. The implantation energy is set so as to become deeper than the junction depth of the p-type drain diffusion layer 14. After the above ion implantation, the photoresist film was removed, and heat treatment for activating the implanted ions was performed to form the high concentration n-type diffusion layer 19. B ion implantation was also performed on the p-type well region 2 in accordance with the above-described manufacturing process to form the high-concentration p-type diffusion region 4. After that, the gate oxide film 7 exposed on the surface of the silicon substrate 1 was removed, and an aluminum (Al) film was deposited on the entire surface. The Al film was processed according to the desired circuit configuration. Here, the ground electrode 10 'is connected to the n-type drain diffusion region 6 and the p-type high-concentration diffusion region 4 and the n-type source diffusion region 5 so as to connect the respective surfaces thereof.
Type output electrode 11 '
, P-type source diffusion region 14 and n-type high-concentration diffusion region
The power supply electrode 20 was constructed so that 19 was connected. After that, the surface stabilizing insulating film 9 is deposited and a hole is formed at a desired position by using a known technique, the Al film of the second layer is vapor-deposited, and the wiring is processed according to the desired circuit configuration. , 22, and 2
3 was formed (Fig. 4).

A CMOS transistor having a gate length of 1.0 μm was manufactured by the above manufacturing process, but the size from the end of the p-type high-concentration diffusion region 4 to the end of the n-type high-concentration diffusion region 19 was the same as the conventional structure.
It is about 1/3 smaller than that of CMOS transistors. The reduction in the element size is based on the fact that the high-concentration diffusion region 4 or 19 for applying the well potential and the source diffusion region 5 or 14 are formed in a self-aligned relationship with the gate electrode 8. In the above structure, it is not necessary to have the field oxide film 3 interposed between the diffusion layers 4 and 5 or 14 and 19 in the conventional CMOS transistor structure, which contributes to the size reduction. Further, since the connection between the diffusion layers can be performed by the common hole, the size required for the alignment allowance of each hole in the conventional structure can be reduced. In the CMOS transistor according to this example, the number of openings was reduced by half along with the reduction of the element size, and the contact failure rate between the diffusion layer and the electrode due to the processing failure of the openings was significantly reduced.

In the present embodiment, an example of a two-layer wiring structure using Al wiring is described, but the effect of this embodiment will not be impaired even if it is configured with one-layer wiring or three-layer wiring or more.

Embodiment 2 FIGS. 5 to 8 are views showing another embodiment of the present invention. In the first embodiment, the silicon nitride film 17 and the silicon thin film are omitted by omitting the respective ion implantation steps for forming the source diffusion layers 5 and 14 and the drain diffusion layers 6 and 13.
The steps of depositing 18, reactive sputtering of the silicon thin film 18, and selective etching of the silicon nitride film 17 using the silicon thin film left adjacent to the gate sidewall as a mask were carried out. Then, the p-type well region 2 and the region where the p-type drain diffusion layer is to be formed are covered with a photoresist film, and the n-type well region 12 is exposed through the gate oxide film 7 exposed on the n-type well region 12. A high concentration of phosphorus was ion-implanted therein. In the above ion implantation, a photoresist film,
Phosphorus ions are not implanted into the well region 12 below the region covered with the silicon nitride film 17 and the gate protection insulating film.
After the above-mentioned ion implantation, the remaining photoresist film was removed, and heat treatment for activating the implanted ions was performed to form the n-type high-concentration diffusion region 19. Next again, the photoresist film 24
Then, the n-type well region 12 and the region where the n-type drain diffusion layer is to be formed are covered, and boron is ion-implanted (FIG. 5).
Boron ion implantation was also performed through the exposed gate oxide film 7, but the silicon nitride film 17 and the photoresist film
No boron is implanted into the p-type well region 2 below 24. After the boron ion implantation, the remaining photoresist film 24 is left.
Was removed, and a heat treatment for activating the implanted ions was performed to form the p-type high concentration diffusion region 4 in the p-type well 2. After the above heat treatment, the silicon nitride film 17 left adjacent to the sidewall of the gate electrode 8 is removed by hot phosphoric acid solution, and then the exposed gate oxide film 7 is also removed to expose the surface of the silicon substrate. Let In this state, a silicon film having a thickness of 50 nm was formed on the entire surface, and then a predetermined portion was selectively removed. In the above,
The remaining silicon thin films 25, 26, and 27 are configured to cover at least the exposed surface of the silicon substrate. The silicon thin films 25, 26, and 27 may be formed by a so-called selective deposition method, that is, a method of selectively depositing a silicon thin film only on the exposed silicon substrate surface. After forming the silicon thin films 25, 26, 27, n
The type well region 12 is covered with a photoresist film 28 (sixth).
Figure). Using the photoresist film 28 as a mask, arsenic is ion-implanted into a partial region of the silicon thin films 25 and 26, the photoresist film 28 is removed, and an n-type source diffusion region 5 and an n-type source region are formed by activation heat treatment. The drain diffusion region 6 was formed. In the formation of the diffusion region described above, the junction depth of the source diffusion region 5 in the p-type well region was about 0.2 μm, but the junction depth formed by the n-type impurity in the p-type high concentration diffusion region 4. It was less than 30 nm. After the formation of the n-type source 5 and drain diffusion regions 6, a photoresist film is selectively left on the p-type well region 2 and p-type is implanted into the n-type well region by boron ion implantation in accordance with the above-mentioned manufacturing method.
A drain diffusion region 13 and a source diffusion region 14 of the mold were formed. After forming the p-type drain 13 and the source diffusion region 14, a palladium (Pd) film is vapor-deposited on the entire surface, heat-treated at about 250 ° C., and 0.1 μm due to the reaction between Pd and the silicon thin films 25, 26, 27.
Thick palladium silicide (Pd ₂ Si) layers 29, 30 and 31 were formed. In the above Pd ₂ Si layer formation, the underlying silicon thin film 2
5, 26, and 27 were completely consumed by forming the Pd ₂ Si layer, and the underlying silicon substrate was also consumed by about 50 nm from the surface. That is, the extremely shallow n-type layer region on the p-type high-concentration diffusion region 4 and the extremely shallow p-type layer region on the n-type high-concentration diffusion region 19 disappear due to the formation of the Pd ₂ Si layers 29 and 31. Ivy. Note that Pd did not react with the silicon oxide film 15, and the Pd ₂ Si layer 29,
After the formation of 30,31, the unreacted Pd film is removed with an aqueous solution of iodine (I ₂ ) and ammonium iodide (NH ₄ I) to remove the silicon thin film 2.
The Pd ₂ Si layer was selectively left only in the regions where 5, 26, and 27 were present (FIG. 7).

After forming the Pd ₂ Si layers 29, 30, and 31, heat treatment for reducing the resistance of Pd ₂ Si was performed at 500 ° C. After that, the surface stabilizing insulating film 9 was deposited and holes were formed at desired positions. Tungsten (W) was vapor-deposited while leaving the photoresist film used for the opening, and the W film on the photoresist film was removed simultaneously with the removal of the photoresist. As a result, the W film 32 was left only in the openings. Then, vapor deposition of an Al film and wiring processing according to a desired circuit configuration were performed to form Al wirings 20, 22, and 23 (FIG. 8).

The size of the CMOS transistor manufactured through the above manufacturing process can be reduced to about 1/3 of that of the CMOS transistor of the conventional structure, as in the first embodiment. Further, in the CMOS transistor according to this embodiment, the extremely shallow junctions (tunnel junctions) formed on the surfaces of the high-concentration diffusion regions 4 and 19 of the same type as the wells 2 and 12 are well controlled by forming the silicide layers 29 and 31. Can disappear. Therefore, as compared with the CMOS transistor according to the first embodiment, the voltage can be applied to the wells 2 and 12 with better ohmic characteristics. The CMOS transistor according to the present embodiment has all the features according to the first embodiment, but further features are the source diffusion layers 5 and 1.
4. The junction depth of the drain diffusion layers 6 and 13 can be made shallower than that of the first embodiment. That is, according to the present embodiment, the silicon consumed when forming the silicide can be compensated by the deposition of the silicon thin films 25, 26, 27. Furthermore, the silicide layer is less reactive with the substrate silicon than a metal film such as Al unless it is subjected to high temperature heat treatment after formation. Therefore, it is more stable than the structure in which the surface of each diffusion layer is directly covered with the metal film as in the first embodiment, and the junction depths of the diffusion layers 5, 14 and 6 and 13 of the source / drain are bonded to each other. The structure can be made extremely shallow without causing failure in destruction.

In this embodiment, the silicon thin films 25, 26, and 27 are deposited in order to compensate the silicon consumed when forming the silicide, but the above deposition may be omitted if desired. Further, in this embodiment, the diffusion layers 5, 14 and 6, 13 of the source / drain
Was formed before the formation of the silicide layers 29, 30, and 31. After the formation of the silicide layer, ions are implanted in the silicide layer to utilize the impurity precipitation phenomenon during the heat treatment for reducing the resistance of the silicide layer to form the source / drain. A diffusion layer may be formed. In this case, an extremely shallow junction of about 10 nm, which is even shallower than the source / drain junction formation according to the present embodiment, can be obtained.

〔The invention's effect〕

According to the present invention, the diffusion region to which the well potential is applied can be configured by self-alignment with the gate electrode of the in-well transistor, so that the element size can be significantly reduced as compared with the conventional structure. The reduction ratio is 1/3 or less of the conventional structure under the condition that the gate length is 1.0 μm.

Another feature of the present invention is that the source diffusion layer can be directly connected to the diffusion region that provides the well potential, so that the number of connection openings can be reduced by half, and therefore, there is also an effect of reducing conduction defects and the like due to the opening step by half. .

The present invention is most suitable for ultra-miniaturization of CMOS transistors, but its application is not limited to CMOS transistors. That is, it can be applied to a semiconductor device having a well structure, for example, an electrically rewritable nonvolatile semiconductor memory device.
Further, the present invention can be applied not only to the semiconductor device composed of two kinds of wells as stored in each of the above-mentioned embodiments but also to the semiconductor device composed of one kind of well.

Although the case where Pd ₂ Si is used as the silicide layer is described in the embodiments of the present invention, other silicide layers, that is, Ti, Zr,
Hf, V, Nb, Ta, Cr, Mo, W, Co, Ni, and Pt and other refractory metals, or transition metal silicide layers, or even those metal films themselves, the effect of the present invention Unchanged. In this case, since the silicon film thickness consumed when forming each silicide is different for each metal, the film thickness of the silicon thin film to be compensated may be controlled as desired.

[Brief description of drawings]

FIG. 1 is a partial sectional view of a conventional CMOS transistor, FIGS. 2 to 4 are sectional views showing a manufacturing process of a first embodiment of the present invention in process order, and FIGS. 5 to 8 are sectional views of the present invention. It is sectional drawing which shows the manufacturing process of another Example in process order. 1,1 '... substrate, 2,12 ... well region, 3 ... insulating film,
4 ... Same conductivity type impurity region, 5, 6 ... Impurity region, 7
... gate insulating film, 8 ... gate electrode, 9 ... insulating film,
10,11 ...... electrode, 13,14 ...... impurity region, 15 ...... gate protection insulating film, 16 …… insulating film, 17 …… insulating film, 18 …… silicon thin film, 19 …… same conductivity type impurity region, 20 …… Electrode, 2
1,22,23 …… wiring, 24 …… photoresist, 25,26,27…
… Silicon thin film, 28 …… Photoresist, 29, 30, 31 ……
Palladium silicide layer, 32 ... Tungsten film.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/092

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device including the following steps. Forming an insulating film on the main surface of a semiconductor substrate having the first conductivity type; forming a gate electrode and a gate protective insulating film having a predetermined shape on the insulating film; forming a second insulating film; Is formed over the entire surface, and then is anisotropically etched over the entire surface to form the first sidewall insulating film while leaving the second insulating film on the side portions of the gate electrode and the gate protective insulating film. A step of ion-implanting an impurity having a second conductivity type opposite to the first conductivity type into the semiconductor substrate to form a first high-concentration impurity region, and laminating a third insulating film and a silicon film on the entire surface. Then, the entire surface is anisotropically etched to leave the silicon film in a portion of the silicon film formed on the first sidewall insulating film with the third insulating film interposed therebetween, and to leave it on another region. Forming a sidewall silicon film by removing the portion formed in the above step, removing the exposed portion of the third insulating film, and then removing the sidewall silicon film to form a second sidewall insulating film. The second side wall insulating film adjacent to the first high-concentration impurity region is formed by ion-implanting an impurity having the first conductivity type into the surface region of the semiconductor substrate using the second sidewall insulating film as a mask.
Forming a high concentration impurity region, and forming an electrode directly connected to the surfaces of the first and second high concentration impurity regions after removing the second sidewall insulating film. 2. A method of manufacturing a semiconductor device including the following steps. A step of forming an insulating film on the main surface of a semiconductor substrate having a first conductivity type; a step of stacking and forming a gate electrode and a gate protective insulating film having a predetermined shape on the insulating film; a second insulating film Forming a first side wall insulating film by leaving the second insulating film on the side portions of the gate electrode and the gate protective insulating film by performing anisotropic anisotropic etching on the entire surface after forming the first side wall insulating film. After the third insulating film and the silicon film are laminated and formed on the entire surface, anisotropic etching is performed on the entire surface to interpose the third insulating film on the first sidewall insulating film of the silicon film. To form a sidewall silicon film by removing the exposed portion of the third insulating film, and then removing the exposed portion of the third insulating film. Are removed to form a second sidewall insulating film Step, using the second sidewall insulating film as a mask, impurities having the first conductivity type are ion-implanted to form a high impurity concentration region at a position apart from the gate electrode in the surface region of the semiconductor substrate. A step of removing the exposed portion of the insulating film to expose the surface of the semiconductor substrate after removing the second sidewall insulating film, forming a thin silicon film on the entire surface, and then removing a predetermined portion A step of removing, by implanting an impurity having a second conductivity type opposite to the first conductivity type, contacting an end of the surface region of the semiconductor substrate on the gate electrode side, and lower than the high impurity concentration region. A step of forming a source diffusion region and a drain diffusion region of the second conductivity type having a high concentration, a metal film is formed on the entire surface, and then heat treatment is performed to cause the metal film and the thin silicon film to react with each other to form a silicide. Forming a removal of the unreacted metal film, thereby leaving only the silicide films.