JPH06101475B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more specifically, it enables formation of fine source / drain regions and electrode connection to the source / drain regions. The present invention relates to a method for manufacturing a MOS semiconductor device, which can be performed with high accuracy.

[Background of the Invention]

Element dimensions such as a gate length, a gate oxide film thickness, and a junction depth in a MOS field effect transistor or an insulated gate field effect transistor (hereinafter simply referred to as a transistor) are miniaturized based on a known reduction rule. The trend continues. However, the source / drain diffusion layer area is not miniaturized in proportion to the dimensions such as the gate length. This is because in the conventional structure transistor, the contact hole on the source / drain diffusion layer is not self-aligned with the end of the diffusion layer and the end of the gate electrode. That is, in the conventional structure transistor, it is necessary to secure the alignment allowance of the contact hole. Even if a contact hole having a size of 0.5 μm is formed by using the latest technology such as electron beam drawing method, it is necessary to secure an alignment margin of 0.5 μm each around the contact hole. That is, the conventional structure transistor has a drawback that the source / drain width cannot be reduced to 1.5 μm or less.

A self-aligned contact structure as shown in FIG. 1 has been considered for the purpose of eliminating the above drawbacks. In FIG. 1, 1 is P
Conductive silicon substrate, 2 is a thick film oxide film for element isolation, 3 is a gate oxide film, 4 is a gate electrode, 5 is an insulating film provided so as to cover the gate electrode, and 6 and 7 are source / drain, respectively. Diffusion layer, 8 and 9 are silicon thin film wiring in which impurities are diffused in high concentration, 10 is a surface protective insulating film,
11 and 12 are source and drain metal electrodes, respectively. In the conventionally known transistor including the self-aligned contact structure represented by FIG. 1, the gate electrode 4 is not self-aligned with the field oxide film 2. Therefore, in the conventional ultra-fine transistor, it is difficult to realize the source diffusion layer 6 and the drain diffusion layer 7 having a desired width due to the misalignment of the gate electrodes.
That is, the variation in the area of the source and drain diffusion layers causes the diffusion layer capacitance to fluctuate, so that the desired input / output speed cannot be realized. Further, the film oxide film 2 is usually
It is formed by the selective oxidation method called LOCOS, but because the oxide film grows in the lateral direction called Birds beak, the source / drain regions are almost the same distance as the film thickness of the film. Are eroded by. Therefore, in the extreme case of the ultra-fine transistor having the conventional structure as shown in FIG. 1, a fatal defect that the source or drain region disappears may occur.

The self-aligned contact structure of FIG.
Although 9 and 9 have a structure in which they are directly connected to the source diffusion layer 6 and the drain diffusion layer 7, other drawbacks occur in the ultrafine transistor having the above structure. That is, the silicon thin film wirings 8 and 9 and the surface protection insulating film 10 are doped with impurities at a high concentration. Therefore, the surface protection insulation film 10
There is a drawback that impurity diffusion occurs during high temperature heat treatment such as heat treatment for flattening, and the junction depths of the source 6 and drain diffusion layers 7 which are to be made extremely shallow are uneven and deep. Further, in the conventionally known self-aligned contact hole structure as shown in FIG. 1, it is necessary to align the silicon thin film wirings 8 and 9 with the source 6 and the drain diffusion layer 7. Therefore, there is a drawback that the contact area and the distance between the gate electrode and the contact change due to the alignment error. In an ultra-fine transistor having an extremely shallow junction, the source / drain diffusion resistance is high, and the effect of the alignment error is represented by a series resistance variation, that is, a current amount variation.

Further, in the self-aligned contact transistor shown in FIG. 1, some of the silicon thin film wirings 8 and 9 must be constructed so as to be connected to at least a part of the source diffusion layer 6 or the drain diffusion layer 7, respectively. I won't. However, when the source / drain diffusion layer area is also miniaturized in a transistor having a gate length of 1 μm or less, the silicon thin film wirings 8 and 9 are aligned with the source diffusion layer 6 or the drain diffusion layer 7. Will be difficult. That is, in an extreme case, when a part of the source-side silicon thin film wiring 8 crosses over the gate electrode 4 and connects to the drain diffusion layer, there is a possibility that misalignment may occur. Therefore, in the conventional structure transistor, the source / drain diffusion layer area could not be miniaturized regardless of the miniaturization of the gate length. That is, in the conventional structure transistor,
Since the area of the drain diffusion layer cannot be miniaturized to the utmost limit, it is difficult to reduce the capacitance of the source / drain diffusion layer, which hinders high-speed operation.

[Object of the Invention]

The object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to configure a source / drain diffusion layer having a constant area and being extremely narrow in a self-aligned manner with respect to a gate electrode, thereby reducing the input / output capacitance and a transistor. It is to provide a structure that enables miniaturization of dimensions.

According to the present invention, it is also possible to provide a self-aligned contact structure in which the input / output resistance is increased due to the alignment error and the fluctuation range thereof is reduced, and the source / drain junction depth is not affected.

Further, according to the present invention, the drawbacks of the above-mentioned conventional techniques are eliminated,
It is also possible to provide a source / drain lead-out wiring structure capable of connecting in a self-aligned manner even to an ultra-miniaturized source / drain diffusion layer. Further, according to the present invention, it is possible to provide a transistor structure in which the source / drain diffusion layer area can be made extremely fine and the diffusion layer capacitance can be reduced to improve the operation speed.

[Summary of the Invention] The present invention is, in the formation of a semiconductor device, only in the main steps, if necessary, in other steps, the position specified by the main steps in the other steps, or from that position,
For example, a semiconductor device is formed by a so-called self-alignment technique in which a predetermined region is formed at a position separated by a certain distance determined by another process, such as a film thickness of a film formed by oxidation or deposition.

That is, when the present invention is applied to a so-called single MOS type semiconductor device, it is possible to form a MOS transistor by using a photomask only when forming a gate electrode and otherwise not using it. However, in an actual semiconductor device, a mask that roughly covers a part is often used. This is an actual application problem, not a problem when applying the present invention.

In the present invention, in order to form a source / drain diffusion layer that is extremely narrow in a self-aligning relationship with the gate electrode with good controllability, a silicon nitride film is formed after forming a gate protective insulating film that is self-aligning with the gate electrode. The film and the silicon thin film are selectively left only on the side wall of the gate electrode through the gate protection insulating film. Using the silicon thin film as a mask, the silicon nitride film other than the gate electrode side wall is completely removed, and then the silicon thin film is also completely removed. The silicon nitride film is left only on the side wall of the gate electrode by the thickness of the silicon thin film, but the exposed silicon substrate surface is selectively oxidized using the silicon nitride film as a mask, and if the silicon nitride film is removed, the silicon nitride film becomes almost silicon. Only an extremely narrow silicon substrate surface having a width corresponding to the thickness of the thin film is exposed only on the side wall of the gate in a self-aligned relationship with the gate electrode. A source / drain diffusion layer is formed on the exposed portion, and its width can be controlled within a range of about 0.1 to 0.3 μm determined by the thickness of the silicon thin film.
The above is 1/10 or more narrower than the minimum width of the conventionally known source or drain diffusion layer, and the junction capacitance can be sufficiently reduced.

The contact formation to the extremely narrow source / drain diffusion layer is based on the self-aligned contact structure. Here,
A silicide layer is formed on the surface of the source / drain diffusion layer in self-alignment with the source / drain diffusion layer by refractory metal or transition metal in order to reduce the influence of the variation of the contact position and its area due to the alignment error of the connection wiring. The diffusion layer resistance is reduced. After silicidation, the refractory metal or transition metal film left unreacted on the silicon oxide film is processed into wiring. In forming the wiring, the silicide layer is not etched by the etching solution for the metal layer. Therefore, the metal wiring connected to the source / drain diffusion layer in self-alignment is formed. Since the main silicide layer has a resistance lower than that of the normal diffusion layer by one digit or more, the influence of the wiring metal alignment error can be reduced to a negligible level.

The silicide formation may erode the silicon substrate and destroy an extremely shallow junction. Therefore, in order to compensate the erosion and maintain the shallow junction, it is desirable to selectively deposit the silicon thin film only on the exposed silicon substrate and then perform silicidation.

According to the present invention described above, a transistor structure having an ultrafine source / drain diffusion layer having a diffusion layer width of 0.3 μm or less can be realized. The above structure configures both ends of the source / drain diffusion layer in a self-aligned manner with the gate electrode. However, in an ultrafine transistor with a gate electrode length of 0.5 μm or less, the shape of the source / drain lead electrode is The use of the conventional technique causes a problem in securing the alignment margin. The present invention solves the above problem by forming one end of the source / drain lead-out wiring in self-alignment with the gate electrode. In order to realize the above structure, the present invention focuses on the phenomenon that a refractory metal, for example, a silicon compound (silicide) of titanium (Ti) is removed by aqua regia, whereas a silicon thin film is not removed. That is, in the gate electrode processing, the gate electrode protection insulating film and the Ti thin film are simultaneously processed by the same mask, and then the gate electrode is protected by the gate electrode sidewall insulating film. After that, a silicon thin film is deposited on the entire surface, and the exposed refractory metal is reacted with the silicon thin film to form a silicide only on the electrode. Etching the above structure with aqua regia removes only the silicide,
A structure in which the silicon thin film does not exist only on the gate electrode can be obtained. The source / drain lead-out electrodes are composed of the above-mentioned silicon thin film, but the lead-out electrode ends other than the gate electrode end may be etched into a desired shape.

The connection opening between the source / drain extraction electrode and the metal wiring can also be formed in self-alignment with the extraction electrode by using the fourth and fifth structures of the present invention. In the present invention, the electron beam exposure depends on the weight of the base in order to form the above-mentioned connecting holes in a self-aligned manner, and the exposure sensitivity of the electron beam resist film is extremely increased in the region where a substance having a large mass is present. To utilize the phenomenon. That is, after forming the source / drain lead-out electrodes made of a silicon thin film, a refractory metal, for example, a tungsten (W) film having a mass sufficiently larger than that of silicon is deposited, and the lead-out electrodes are silicidized. The unreacted refractory metal film is formed of hydrogen peroxide (H ₂
It can be selectively removed with an aqueous solution of O ₂ ). Next, a wiring interlayer insulating film is deposited, an electron beam exposure resist is applied for forming wiring connection holes, and electron beam irradiation is performed. In this case, the electron beam irradiation area is self-aligned with the source / drain extraction electrodes because the light contact sensitivity is high on the source / drain extraction electrode silicided by the refractory metal with a large mass even if the area is enlarged by the planned opening area. The resist film in the aperture area is exposed to light, and the aperture can be opened.

When the gate electrode is made of a material having a large mass such as W, there is a possibility that an opening may be formed even on the gate electrode by the above method. In order to overcome the above-mentioned drawbacks, in the present invention, the film thickness of the wiring interlayer insulating film on the gate electrode which is not opened is made thicker than the film thickness of the insulating film on the source / drain lead-out electrodes. In the above structure, the exposure sensitivity on the gate electrode is not increased because the insulating film thickness is large, and the holes are formed only on the source / drain extraction electrodes in a self-aligned manner. A method for selectively forming a thick interlayer insulating film on a gate electrode which does not require an opening will be described in detail in Examples. However, in an ultrafine transistor having a gate electrode length of 0.5 μm or less, before the interlayer insulating film is deposited. If the above gate electrode is formed in a concave shape, it is extremely easy to deposit thickly only on the gate electrode. That is, the interlayer insulating film having a thickness sufficient to fill the concave shape may be deposited on the entire surface.

Example of Invention

Hereinafter, the present invention will be described in more detail with reference to Examples.
For convenience of explanation, the description will be made with reference to the drawings, but attention must be paid because the main part is shown enlarged.

Embodiment 1 FIGS. 2 to 6 show an embodiment of a semiconductor device according to the present invention, in which 1 is a silicon substrate having a p-conductivity type specific resistance of 1 .OMEGA.-cm. A groove was formed in a silicon substrate 1 by a known element isolation technique, and a film oxide film 2 having a structure in which the groove was filled with a silicon oxide film was formed. The film insulating film 2 may be formed by a conventional selective oxidation method or a so-called U-type insulating method in which an insulating film is formed on the wall surface of the groove and a silicon film is embedded inside. After the film insulating film 2 is formed, the surface of the silicon substrate 1 in the active region is exposed and a 10 nm clean gate oxide film 3 is formed. Then, a tungsten thin film 4 having a thickness of about 0.3 μm and a silicon oxide film 13 containing a slight amount of phosphorus are deposited. Then, the tungsten thin film 4 and the silicon oxide film are formed by the photo-etching method.
13 is etched at the same time, and the gate electrode 4 and the gate protection insulating film 13
Were formed with the same dimensions. Then again by chemical vapor reaction to 0.
A 1 μm silicon oxide film 14 was deposited on the entire surface. The silicon oxide film 14 was etched in a direction perpendicular to the surface of the silicon substrate 1 by reactive sputtering, and the silicon oxide film 14 deposited on the flat portion was selectively removed. As a result of the etching, the deposited silicon oxide film 14 is selectively left only on the side wall of the gate electrode 4, and the gate electrode 4 is covered with the silicon oxide films 13 and 14. After that, about 20 nm
A thick silicon nitride film 15 and a 0.35 μm thick silicon thin film 16 were sequentially deposited by chemical vapor reaction (FIG. 2). Next, by etching the silicon thin film 16 in the direction perpendicular to the surface of the silicon substrate 1 again by the reactive sputtering method, the silicon thin film 16 deposited on the flat portion is removed and the gate electrode 14 is removed.
Is selectively left only on the side wall of the gate via the gate side wall silicon oxide film 14. In this state, the exposed silicon nitride film 15 was removed by heating phosphoric acid (H ₃ PO ₄ ) using the silicon thin film 16 as a mask (FIG. 3). Next, the silicon thin film 16 left on the side wall of the gate electrode 4 is removed with a mixed solution of hydrofluoric acid (HF) and nitric acid (HNO ₃ ), and the silicon nitride film 15 left selectively under the silicon thin film 16 is removed. Remains unetched. Next, the exposed gate oxide film 3 is removed using the remaining silicon nitride film 15 as a mask, and the exposed surface of the silicon substrate 1 is oxidized by a thermal oxidation method to about 0.15.
A second film insulating film 17 made of a silicon oxide film of μm was formed. Before forming the second film insulating film 17, boron (B) may be implanted into the exposed silicon substrate 1 by ion implantation if desired. The second film insulating film 17 has a thickness of about 0.15 from the end of the remaining silicon nitride film 15.
It was formed by penetrating under the μm silicon nitride film 15. After forming the second film insulating film 17, the remaining silicon nitride film 15 was removed using a phosphoric acid solution heated again. Subsequently, arsenic (As) having a dose of 1 × 10 ¹⁵ cm ^-2 is ion-implanted through the exposed gate insulating film 3, and the subsequent activation heat treatment is performed at a temperature of 900 ° C. to perform the source diffusion layer 6 and the drain diffusion layer. Formed 7. In the present embodiment, the depth is about 0.15 μm, but in the present invention, the source / drain regions should be sufficiently close to the channel formed by the gate, so that the depth may be changed variously. Absent. Then, the exposed gate oxide film 3 is removed to remove the silicon substrate 1.
The surface was exposed (Fig. 4). In this state, a 0.1 μm-thick palladium (Pd) film 20 is vapor-deposited on the entire surface, and then low-temperature heat treatment at 250 ° C. is performed. By the above heat treatment, 50 nm thick palladium silicide (Pd ₂ Si) layers 18 and 19 were formed on the source diffusion layer 6 and the drain diffusion layer 7, respectively. The Pd film 20 does not react with the silicon oxide film and is selectively Pd ₂ Si only on the source diffusion layer 6 and the drain diffusion layer 7 where the silicon is exposed.
Layers 18 and 19 are formed. (Fig. 5). Next, an unreacted Pd film 20 was formed in an aqueous solution of ammonium iodide (NH ₄ I) and iodine (I ₂ ).
After removing, the heat treatment for reducing the resistance of the Pd ₂ Si layers 18 and 19 was performed at 600 ° C. After the heat treatment for reducing the resistance, a 20 nm thick titanium (Ti) film and a 0.2 μm Pd film were sequentially formed by vapor deposition to form a double metal wiring film 20 '. Next, the above-mentioned double metal wiring 20 'was processed according to the desired circuit configuration. Etching was by dry etching with I ₂ . In the above etching, the Pd ₂ Si layers 18 and 19 do not erode. Therefore, double metal wiring film 20 '
Even if some misalignment occurs in the etching process, the source / drain diffusion layer resistance is sufficiently low and fluctuates as long as the double metal wiring film 20 'and the Pd ₂ Si layers 18 and 19 are locally in contact with each other. The width can be kept small. The above is because the entire surfaces of the source diffusion layer 6 and the drain diffusion layer 7 are covered with the low resistance Pd ₂ Si layers 18 and 19 in a self-aligned manner.
Wiring with a quintuple metal wiring film 20 ', and Pd ₂ Si layers 18 and 19
After the connection step with, a surface protection insulating film 10 made of a silicon oxide film to which phosphorus was added was deposited by a known method. Then, a hole was formed in the surface protective insulating film 16 at the desired connection point. A TiW film was deposited on the entire surface while leaving the photoresist film used for the opening. When the photoresist film was removed in this state, TiWs 21 and 22 were selectively left only in the regions corresponding to the openings. The formation of the TiW film is carried out by the vapor deposition of the double metal wiring film 20 'not by the above method, but by forming the triple metal wiring film by further depositing the TiW film, and performing the wiring process by the desired circuit method. Is also good. After selectively leaving TiW21 and 22 in the opening, aluminum (A
l) was vapor-deposited on the entire surface, and the source electrode 11 and the drain electrode 15 and further wiring were formed according to a desired circuit configuration by a known wiring process (FIG. 6).

In the transistor manufactured through the above manufacturing process, both the source diffusion layer 6 and the drain diffusion layer 7 have a width of 0.2 μm.
m, which is 15 times narrower than the minimum width of 3 μm in the conventional structure transistor, and shows good transistor characteristics. Further, the input / output capacitance of the transistor according to the present embodiment has been reduced to about half that of the conventional structure, and the input / output speed has been increased by more than double. Regarding the transistor having a gate length of 0.8 μm, comparing the areas of the activation regions consisting of the source / drain and the gate, the one according to this embodiment is reduced to about 1/5 of the conventional structure, and the input / output is reduced. The resistance was low and the transfer conductance was improved. It is considered that the above is an effect because the distance from the channel end to the source or drain contact hole in the conventional structure is shortened to both ends in the structure of this embodiment and the diffusion resistance is reduced by silicidation.

Embodiment 2 FIGS. 7 to 8 are views showing another embodiment of the present invention. In the first embodiment, the second film insulating film
After removing the silicon nitride film 15 used for selective formation of 17 and the gate oxide film 3 thereunder, dichlorosilane (Si
Chemical vapor phase reaction of H ₂ Cl ₂ ) and hydrochloric acid (HCl) is performed at a temperature of 775 ° C. to selectively form 0.2 μm thick polycrystalline or amorphous silicon thin films 23 and 24 on the exposed silicon substrate. Deposited. SiH ₂ Cl ₂ 200cc, H
The condition is Cl60cc and the deposition rate is 10 nm / min. Under the above conditions, unless the silicon nitride film is present on the surface, the silicon thin films 23 and 24 are selectively deposited only on the silicon substrate, and are also referred to as fusets at the boundary with the silicon oxide film 14 on the side wall. No concave shape occurs. On the second film insulating film 17, about 0.1 μm from the edge of the film insulating film 17.
The silicon thin films 23 and 24 were deposited as they were raised by about m (FIG. 7). After selectively depositing the silicon thin films 23 and 24, As ions were implanted into the silicon deposited films 23 and 24. The injection amount is 7 × 10 ¹³ cm ^-2 . Next, short-time heat treatment was performed at 1100 ° C. for 30 seconds to activate the implanted ions to form the source diffusion region 6 and the drain diffusion region 7. The diffusion coefficient of impurities in the silicon thin films 23 and 24 composed of polycrystalline or amorphous is 10 to 20 times larger than that in single crystal silicon.
Therefore, the impurity distribution in the silicon thin films 23 and 24 was almost uniform by the above short-time heat treatment, and the diffusion into the underlying silicon substrate could be controlled to a junction depth of about 35 nm, which is extremely shallow. After forming the source diffusion layer 6 and the drain diffusion layer 7 (depth of about 0.1 μm), the Pd ₂ Si layers 18 and 19 are formed according to the first embodiment, and the subsequent steps are also performed according to the embodiment. Was produced (Fig. 8).

In the transistor manufactured through the above manufacturing process,
Since the Pd ₂ Si layers 18 and 19 are formed on the silicon thin films 23 and 24, if the thicknesses of the silicon thin films 23 and 24 are set in advance so as to compensate the thickness of the silicon layers consumed when forming the silicide, junction breakdown due to silicidation Can be prevented. That is, based on this embodiment, a transistor having an extremely shallow junction of 35 nm could be realized without losing any of the characteristics of the transistor according to the first embodiment. Furthermore, the high breakdown voltage structure of the ultra-fine transistor described in Japanese Patent Application No. 58-76119 is about 1/5 based on this embodiment.
The device area could be reduced. The impurity concentration on the surface of the source / drain diffusion layer of the transistor according to this example was finally set to a low value of 5 × 10 ¹⁸ cm ⁻³ . By forming a low-concentration drain diffusion layer, a high breakdown voltage between the source and drain is realized, and in a transistor having a gate length of 0.2 μm, the breakdown voltage between the source and drain is 8 V, and the above-mentioned Japanese Patent Application No. 58-76119. The same value as that of the transistor of was obtained. The breakdown voltage is 2 to 3 times the value of the conventional structure transistor.

Reference Example 1 FIGS. 9 to 12 show a reference example 1 of a semiconductor device according to the present invention.
In the figure, 1 is a silicon substrate of p conductivity type and specific resistance of 1 Ω _- cm. After a thick 0.5 μm thick oxide film 2 is selectively formed on the silicon substrate 1 by using a known element isolation technique, the silicon surface in the active region is exposed to a film thickness of 10 nm.
To form a clean gate oxide film 3. After that, 0.35μ
m W film, 0.3 μm slightly phosphorus-added silicon oxide film, and 0.2 μm Ti film were sequentially deposited. The above-mentioned three-layer film was simultaneously etched by a photo-etching method, and processed so as to be aligned with the gate electrode 4, the gate protective oxide film 13, and the gate electrode 4.
A Ti film 31 was formed. The width of the gate electrode 4 after the photolithography, that is, the gate length was 0.5 μm. Then monosilane (SiH ₄₎ was deposited on the entire surface of the silicon oxide film 5 'having a thickness comprised 0.3μm by chemical vapor reaction using a (Figure 9). WAS by introducing a small amount of Fuosufuin (PH ₃₎ at the time of chemical vapor phase reaction to the silicon oxide film 5 'is phosphorus is added to. When the silicon oxide film 5'is etched in a direction perpendicular to the surface of the silicon substrate by reactive etching, and the silicon oxide film deposited on the flat portion is removed, the silicon oxide film (gate The side wall oxide film 5) is left. In this state, a 0.35 μm silicon thin film 32 was deposited on the entire surface by thermal decomposition of SiH ₄ . Although the thermal decomposition temperature was about 720 ° C., in the above deposition, the silicon thin film deposited on the Ti film 31 reacted with the Ti film 31, and the titanium silicide (TiSi ₂ ) film 3 was formed.
1'is formed (Fig. 10). In the above silicidation reaction, the Ti film 31 has a thin film thickness of 0.2 μm,
All the silicon thin films deposited on the film 31 reacted and were silicidized. It is considered that a large ratio of silicon is eroded in forming the disilicide. After selectively forming the TiSi ₂ layer 31 ', TiSi ₂ film by aqua regia
31 'was removed. In the above etching, silicon thin film
Since 32 is not removed, a structure in which the silicon thin film 32 does not exist on the gate electrode 4 is obtained in self-alignment with the end of the gate electrode 4. In this state, the remaining silicon thin film 32 was etched into a desired shape to form a source extraction electrode 8 '(32) and a drain extraction electrode 9' (32). Then, arsenic (As) is applied to the source extraction electrode 8'and the drain extraction electrode 9 '.
Was implanted by ion implantation under the conditions of an acceleration energy of 70 KeV and a dose of 5 × 10 ¹⁵ cm ^-2 . After the above-described ion implantation, activation of implanted ions and heat treatment for extending the diffusion layer to the silicon substrate are performed at 1000 ° C. to reduce the resistance of the source extraction electrode 8 ′ and the drain extraction electrode 9 ′ and the source diffusion layer 6,
A drain diffusion layer 7 was formed (FIG. 11). Thereafter, a surface protection insulating film 10 was deposited by a known technique, and a hole was formed in the surface protection insulating film 10 on the source extraction electrode 8'and the drain extraction electrode 9'by a known photographic etching method. Subsequently, the wiring including the wirings 11 and 12 to be connected to the source extraction electrode 8'and the drain extraction electrode 9'was formed according to a desired circuit system (FIG. 12).

In the transistor manufactured through the above manufacturing process, although the source / drain diffusion layer regions 6 and 7 are formed by the known selective diffusion method, the ends of the source / drain extraction electrodes 8'and 9'are formed. Since the portion can be configured by self-alignment with the end portion of the gate electrode 4, no alignment margin is required between the source / drain extraction electrode and the source / drain diffusion layer. Therefore, the width of the source / drain diffusion layer was reduced to 1 μm, which is about 1/3 of the conventional structure transistor. Since the area of the source / drain diffusion layer is miniaturized to 1/3 of the conventional structure transistor, the input / output capacitance is reduced, and the operating speed of the transistor according to the present invention is about 20% compared to the conventional structure transistor. I was able to improve.

Embodiment 3 FIGS. 13 to 19 are views showing another embodiment of the present invention. In the first embodiment, the element isolation field oxide film 2 is formed by a known buried oxidation method. After forming the film oxide film 2, the gate oxide film 3, the W film, and the gate protective oxide film were sequentially formed according to the first embodiment. Each of the W film and the gate protection oxide film had a thickness of 0.15 μm. Subsequently, a second W film having a film thickness of 0.15 μm and a second gate protection oxide film having a film thickness of 50 nm were deposited. The first above
The second W film 34 which is processed in a self-aligned manner with the gate electrode 4 by simultaneously etching the second W film and the four-layered superposed film including the first and second gate protective oxide films by the photoetching method , And the
1, second gate protection oxide films 13 and 33 were formed. Then, the gate sidewall oxide film 5 was formed according to the first embodiment. Next, a silicon nitride film 15 having a thickness of about 20 nm and a silicon thin film 16 having a thickness of 0.35 μm are sequentially deposited by chemical vapor reaction (13th embodiment).
Figure).

Next, when the silicon thin film 16 is etched again in the direction perpendicular to the surface of the silicon substrate 1 by the reactive sputtering method, the silicon thin film 16 deposited on the flat portion is removed and only the side wall of the gate side wall oxide film 5 is selectively etched. Left behind.
In this state, the exposed silicon nitride film 15 was removed by heated phosphoric acid (H ₃ Po ₄ ) using the silicon thin film 16 as a mask (FIG. 14).

Next, the silicon thin film 16 selectively left on the side wall of the gate side wall oxide film 5 is removed by a mixed solution of hydrofluoric acid (HF) and nitric acid (HNO ₃ ).
Only the lower silicon nitride film 15 is left. Then, the exposed gate oxide film 3 is removed by using the remaining silicon nitride film 15 as a mask, and the exposed surface of the silicon substrate 1 is oxidized by a thermal oxidation method to form a silicon oxide film having a thickness of about 0.15 μm. A film oxide film 17 of No. 2 was formed. The second film oxide film was formed by penetrating under the silicon nitride film 15 by about 0.15 μm from the end of the remaining silicon nitride film 15. After the formation of the second film oxide film 17, the remaining silicon nitride film 15 was removed again by the heated phosphoric acid solution, and then the exposed gate oxide film 3 was also removed (FIG. 15).

Next, after applying the electron beam resist solution RE5000P (trade name) on the entire surface and then irradiating the electron beam with an irradiation amount of 10 μC / cm ² on the entire surface and developing, only the resist film on the second W film 34 was selectively formed. The resist film 37 on the other region was left as it was. By utilizing the selective residual film effect of the resist film 37, only the second gate protective oxide film 33 on the second W film 34 is selectively removed (FIG. 16). The selective residual film effect of the resist film by electron beam irradiation is based on the characteristics shown in FIG. 19. Curve 23 is the case where a substance with a large mass such as W exists under the silicon oxide film, and curve 24 is the silicon oxide film. Below is the resist residual film rate after electron beam irradiation and development in the case of a silicon substrate. That is, when electron beam irradiation is performed under the condition of 10 μC / cm ² , the resist film is completely removed on the W film, but about 50% of the resist film remains on the silicon substrate. By utilizing this development, the resist film on a substance having a large mass such as W can be selectively removed. The above-mentioned development is based on the development in which the reflection amount of the electron beam depends on the mass difference of the base material, and in order to prevent the development, the distance to the base material, that is, the oxide film thickness on the W film is compared with other development. It may be thickened or the like. Second W
After selectively exposing the surface of the film 34, depositing a silicon thin film having a thickness of 0.3 μm and removing the tungsten silicide film formed in the second W film 34 by aqua regia in accordance with Reference Example 1 above. A structure in which the silicon thin film was not selectively present only on the W film 4 of No. 1 was obtained. From this state, according to the first reference example, the source extraction electrode 8 ', the drain extraction electrode 9',
The source diffusion layer 6 and the drain diffusion layer 7 were formed. After that, Ti is deposited on the entire surface, and a silicidation heat treatment at 720 ° C. and selective removal of the unreacted Ti film are performed to form titanium silicide electrodes on the source extraction electrode 8 ′ and the drain extraction electrode, respectively.
Formed 35 and 36. A mixed aqueous solution of hydrogen peroxide solution and ammonia water was used to remove the unreacted Ti film, but the titanium silicide film was not removed by the above mixed solution, and the source / drain formed by self-alignment with the gate electrode 4 was used. The silicide layer was left only on the extraction electrode (Fig. 17). Thereafter, the wiring process including the formation of the surface protective insulating film, the opening to the desired portion, and the connection to the source / drain lead-out electrodes was carried out based on the first embodiment (FIG. 18).

In the transistor manufactured through the above manufacturing process, the source / drain diffusion layers 6 and 7 can be formed extremely fine with a width of 0.2 μm, and wiring short circuit and contact failure to the ultrafine diffusion layer. It was possible to form the extraction electrode in a self-aligned manner without causing the above. Further, since the above-mentioned lead electrode is silicided, the series resistance of the source / drain can be made 1/10 the wiring resistance as compared with the conventional wiring in which the lead electrode is formed of a silicon thin film.
By reducing the wiring resistance and making the source / drain diffusion layers ultra-fine, the operating speed of the transistor according to the present embodiment could be improved to about twice that of the conventional structure.

Embodiment 4 FIG. 20 is a view showing another embodiment of the present invention. In this embodiment, the silicide layers (35, 36) provided on the extraction electrodes are used to provide holes for providing the electrodes 11, 12 in a self-aligned manner.

That is, the fact that only the photoresist on the silicide layers (35, 36) can be removed is used.

According to the second embodiment, TiSi ₂ layers 35 and 36 are formed on the source extraction electrode 8'and the drain extraction electrode 9'in a self-aligned manner. The length of the gate electrode 4 is 0.3 μm
The distance between the source / drain extraction electrodes was also 0.3 μm. In addition, the second gate protection insulating film 33
Had a film thickness of 0.15 μm. 0.5 after formation of TiSi ₂ layers 35, 36
A surface protective insulating film 10 having a thickness of μm was deposited on the entire surface, but the insulating film thickness on the gate electrode 4 was the same as the gate protective oxide film 13.
It was about 1 μm including that. In this state, application of an electron beam resist and electron irradiation under the condition that the irradiation amount was 10 μC / cm ² were selectively applied to the source extraction electrode and drain extraction electrode portions. In the above, on the TiSi ₂ layer having a large mass number, the amount of reflection of the irradiation electron beam was large and the resist film did not remain after the development, and the opening was formed. However, on the gate electrode 4, the residual film ratio of the resist film was about 1/2 and no opening was formed because the film thickness of the underlying insulating film was about twice that on the TiSi ₂ layer. The resist residual film rate on the silicon substrate was also about 1/2. Despite the coarse alignment accuracy of the electron beam irradiation area, the opening of the connection hole between the source / drain extraction electrode and the external wiring is self-aligned only to the silicided source / drain extraction electrodes 35 and 36. Formed. In this case, even if the alignment is very misaligned, the holes for the electrodes 11 and 12 are
0 It is not formed except the portion (upper part of the silicide 35, 36) corresponding to the portion A in FIG. Of the surface protective insulating film 10, only the portion which is irradiated with the electron beam and is formed under the resist film formed in the above-mentioned portion A is removed.

After removing the surface protective insulating film in the opening of the resist film, the aluminum wiring was connected according to the desired circuit configuration (FIG. 20).

In the transistor manufactured through the above manufacturing process, the widths of the source / drain diffusion layers 6 and 7 can be extremely fine as 0.2 μm as in the case of the second embodiment.
The same ultra-fine and high-speed operation characteristics as those of the transistor in the second embodiment could be realized without causing connection failure. Furthermore, since the wiring connection holes for the source / drain lead-out electrodes can be formed by self-alignment, the alignment margin for the connection holes and the so-called dockbone for forming a region wider than the normal wiring width can be provided. Could be disused. As a result of the above, it was possible to significantly reduce the wiring area. The drastic reduction of the wiring occupation area according to the present invention is particularly effective in the logic circuit MOSLSI.

In this embodiment, it is desirable that the insulating film thickness ratio on the source / drain extraction electrode and the gate electrode is 1.5 to 2 times or more. Under the above conditions, as described in this embodiment, Only the resist film on the source / drain extraction electrodes can be developed and removed in a self-aligned manner by electron beam irradiation.

〔The invention's effect〕

According to the present invention, an extremely narrow source of 0.2 to 0.3 μm
Since the drain diffusion layer can be formed in a self-aligned manner with the gate electrode, the area occupied by the source / drain diffusion layer can be reduced to 1/15 or less compared to the conventional structure. In the above transistor, the source / drain junction capacitance is reduced by one digit or more as compared with the conventional structure, so that the input / output speed can be improved more than twice. Further, according to the present invention, since the wiring can be connected in a self-aligned manner with the narrow silicided source / drain diffusion layer, it is possible to reduce the diffusion layer resistance, the series resistance, and the variation width thereof. . Therefore, there is an effect that the transfer conductance is improved. The present invention can also be applied to a high breakdown voltage / ultrafine transistor having a gate length of about 0.2 μm. Therefore, according to the present invention, the source / drain breakdown voltage of 8 V is 0.2
A μm gate length transistor can be configured with an occupied area of 1/5 or less compared to the conventional structure.

As is apparent from the first and second embodiments, the semiconductor device according to the present invention is based on the manufacturing method of forming the second field insulating film after forming the gate electrode. Therefore, it is not necessary to install the first film insulating film 2 in the region in the series direction with the second film insulating film 17 and the gate electrode 4 as shown in FIGS. It suffices to just install it so that it contacts the second field insulating film 17 in the width direction of the channel.

In the first and second embodiments, the source diffusion layer 6
If the same impurity region as that of the drain diffusion layer 7 is provided in regions other than those shown in FIGS. 4 to 8, a mask is selectively placed on the desired region for photo-etching in the state of FIG. Etching the silicon thin film 16 and then the first
Alternatively, it may be manufactured based on the second embodiment.

In the first and second embodiments, for convenience of description, the case where the silicide layers 18 and 19 are Pd ₂ Si is described, but the silicide layers are Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Ni,
It may be a silicide layer of another refractory metal such as Pt or a transition metal. The double metal wiring film 20 'is also made of Ti and Pd.
It is not limited to superposed membranes. In addition to Ti, the first layer metal film that requires good adhesion with the silicon oxide film is TiW, Mo, Z
It may be another metal such as r, Al, Ta, Cr or a mixed film thereof. Further, the second metal film corresponding to the Pd film is Au, C
Further, it may be various refractory metals or transition metals mentioned above. Further, instead of the double metal wiring 20 ', the wiring layer may be composed of the first layer metal alone.

According to the third and fourth embodiments of the present invention, since the extraction electrode from the source / drain diffusion layer can be configured by self-alignment with the gate electrode, the source / drain diffusion layer does not cause a defect such as a short circuit between wirings. The area can be extremely reduced. Therefore, there is an effect of significantly reducing the diffusion layer capacitance. Further, according to the present invention, since the opening for connection to the source / drain lead-out electrode can be formed by self-alignment, the opening alignment margin can be made unnecessary and the wiring occupying area can be effectively reduced. . Further, according to the present invention, since the source / drain extraction electrode is silicidized,
The effect of reducing the drain series resistance can also be used, and high gain and high speed operation are possible.

In the third and fourth embodiments described above, WSi ₂ or TiSi _{2 is used} as the silicide layer film 31 ′ formed in a self-aligned manner on the gate electrode 4 through the gate protection oxide film 13 for convenience of explanation.
Although the case has been described, the silicon thin film may be a silicide film of another refractory metal or transition metal that is removed by an etching liquid that is not etched. Further, the liquid for removing these is not limited to aqua regia. Furthermore, the fourth
The silicidation of the source / drain lead-out electrodes described in the fifth embodiment is not limited to TiSi _2, and the refractory metal (or transition metal) Mo, Ta, W, which has a larger mass number than Si, can be used.
Any silicide such as Zr, Hf, V, Cr, Ni, Pt, Pd may be used.

In each of the above-mentioned embodiments, for convenience of explanation, a p-conductivity type substrate is provided with n.
Although the so-called n-channel transistor which constitutes the source / drain region by the p-type impurity is shown, the semiconductor device according to the present invention is also applicable to the so-called p-channel transistor constituted by the n-conductivity type substrate and the p-type impurity by the source / drain region. Applicable. Further, the present invention is not limited to the single transistor as described above, but can be applied to complementary transistors and semiconductor integrated circuit devices.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a conventional structure MOS type field effect transistor for making a self-aligned connection to a source / drain diffusion layer, and FIGS. 2 to 6 are cross-sectional views showing a first embodiment of the present invention. 7 to 8 are sectional views showing a second embodiment of the present invention, FIGS. 9 to 12 are sectional views showing a reference example 1 of the present invention, and FIGS. 13 to 18 are present inventions. FIG. 19 is a cross-sectional view showing the third embodiment of the present invention, and FIG. 19 is a view showing the dependency of the electron beam irradiation condition of the positive type electron beam resist on the underlying material as a parameter. FIG. 20 is a view for explaining the self-aligning opening technology in the embodiment of FIG. 20, and FIG. 20 is a sectional view showing the fourth embodiment of the present invention. 1 ... Semiconductor substrate, 2 ... Separation insulating film, 3 ... Gate insulating film, 4 ... Gate electrode, 5 ... Insulating film, 6,7 ... Source and drain regions, 8,9,8 ', 9 '... Extractor electrode, 1
0 …… Surface protection insulation film, 11,12 …… Electrode, 13,14 …… Insulation film, 15 …… Silicon nitride film, 16 …… Silicon layer, 17 ……
Silicon oxide film, 18,19 …… Silicide layer, 20,20 ′ ……
Extraction electrode, 21,22 …… TiW film, 23,24 …… Silicon layer, 3
1 …… Ti film, 31 ′ …… titanium silicide film, 32 …… silicon thin film, 33 …… insulating film, 34 …… W film, 35,36 …… titanium silicide film, 37 …… photoresist.

Claims (3)

[Claims] 1. A step of forming a gate electrode having a predetermined shape on a main surface of a semiconductor substrate having a first conductivity type surrounded by an insulating film for element isolation through a first insulating film. A step of forming a second insulating film on the side wall of the gate electrode, a step of laminating and forming a silicon nitride film and a polycrystalline silicon film on the entire surface, and an anisotropic etching of the polycrystalline silicon film, Leaving a portion formed on the side wall of the gate electrode and removing a portion formed on another region; etching the exposed portion of the silicon nitride film to remove; A step of removing the polycrystalline silicon film, a step of oxidizing the surface of the semiconductor substrate with the silicon nitride film as a mask to form a third insulating film, a step of removing the silicon nitride film, 1 insulating film, 2nd An impurity having a second conductivity type opposite to the first conductivity type is doped into the surface region of the semiconductor substrate through the opening defined by the insulating film and the third insulating film to form a source and a drain. And a step of forming a source lead-out electrode and a drain lead-out electrode which are respectively connected to the source and the drain through the opening, and a method of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the source extraction electrode and the drain extraction electrode is performed after the step of forming the source and the drain. . 3. The manufacturing of a semiconductor device according to claim 1, wherein the step of forming the source extraction electrode and the drain extraction electrode is performed before the step of forming the source and the drain. Method.