JPH0714142B2 - Pulse generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention relates to an improvement of a pulse generation circuit for generating serial pulses at regular intervals for giving a position command to a feedback control system of a motor.

<Prior Art> Conventionally, as such a pulse generation circuit, there is one described in the specification of Japanese Patent Application No. 63-182536 by the present applicant.

This specification describes a pulse generation circuit provided with one preset buffer for presetting the pulse number and the pulse rate of the output pulse in the next sampling period during the present sampling period. In this pulse generation circuit, the number of pulses and the pulse rate can be set in advance by a microprocessor (hereinafter referred to as μP), so that there is a merit that the delay of the setting timing does not affect the output pulse. is there.

<Problems to be Solved by the Invention> However, even with such an improved pulse generation circuit, μ
Since there is a slight error between the sampling period used to calculate the number of pulses and the pulse rate at P and the sampling period of the actual output pulse, when the number of pulses calculated at the calculated pulse rate is generated, The point of completion of pulse generation may be delayed. Therefore, when a new sampling period is entered, the time at which the μP can preset new data in the preset buffer is also delayed. When pulses are output continuously, if this delay is integrated, as a result, pulses will not be output for one cycle.

The present invention has been made in order to solve such a problem and has a function of increasing / decreasing pulse rate data inside a pulse generating circuit, and a preset buffer is constantly provided a predetermined time before the data setting from μP. The purpose is to realize a pulse generation circuit that is in a ready state.

<Means for Solving the Problems> In the present invention, the data of the number of output pulses in one sampling cycle is preset, and the DDA circuit described later latches the data, and the output pulse of the next sampling cycle is generated during the current sampling cycle. The first preset buffer where the number data is preset, and the pulse rate data of the output pulse is preset,
When the DDA circuit described later latches the data, the second preset buffer in which the data of the pulse rate of the next sampling period is preset during the current sampling period, and the preset value of the first preset buffer are set, and the pulse is set. The count fluctuates each time is output, and a count that generates a count-up signal when the count fluctuates by the set value and data that gives the optimum pulse rate value corresponding to the preset value of the second preset buffer are stored. And a controller for reading an optimum pulse rate value from the memory by using the preset value of the second preset buffer as an address when a preset value is set in the counter, and a pulse rate value read by the controller. Latch this pulse A DDA circuit that generates a carry signal that becomes an output pulse in a cycle according to a rate value, a gate that prohibits passage of the carry signal when the count-up signal occurs, and terminates the generation of the output pulse, The second preset buffer is provided in the previous stage, and measures the time from the completion of pulse output to the start of presetting to the second preset buffer in the next sampling cycle, and the second time is measured according to the measured value. And a rate data control circuit for controlling a value preset in the preset buffer of.

<Operation> In the present invention as described above, the rate data control circuit is provided in the preceding stage of the preset buffer in which the data of the pulse rate of the output pulse is preset, and the pulse rate value is controlled by this circuit to set the data from the μP. On the other hand, the preset buffer is constantly set to the ready state a predetermined time before.

<Example> Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a pulse generating circuit according to the present invention.

In the figure, reference numeral 1 is a preset buffer in which data of the number of output pulses in one sampling period is preset. The preset value is given from the μP (not shown) via the 8-bit data bus IDB0-7. Since the number of bits of the preset value is larger than the number of bits of the data bus, the upper byte load signal ▲ ▼ and the lower byte load signal ▲ ▼ are used separately and set in time division. The number of output pulses in the next sampling period is preset in this buffer during the current sampling period.

1 ₁ is a preset buffer in which the pulse rate data of the output pulse is preset. The data of pulse rate is the same as the data of the number of output pulses.
Is set by using the upper byte load signal ▲ ▼ and the lower byte load signal ▲ ▼. Also, the pulse rate of the next sampling period is set during the current sampling period.

A down counter 2 is set with a preset value of the preset buffer 1 and counts down each time a pulse is output, and outputs a count-up signal when the count reaches 0. After the count-up signal is generated, the data of the next output pulse number is set from the preset buffer 1.

A latch 3 takes out the most significant bit of the output pulse number data and holds and outputs the signal SIGN indicating the pulse direction. When the motor is driven by the output pulse, the SIGN signal is a signal that determines the rotation direction of the motor.

4 is a memory, and the preset value of the preset buffer 1 ₁ to the address, data optimum pulse rate values corresponding to the preset value is stored. A ROM is used as the memory 4. The address to the memory 4 is given by the 15-bit address bus RA0-14.

5 is a status buffer status read signal ▲ ▼ by preset buffer 1 and 1 status signal from ₁ ▲ ▼ and ▲ ▼
Read.

6 is a control logic, which is a clock signal CLOCK
It operates at the timing given by, and stores the set value from the preset buffer 1 to the down counter 2 and the memory 4
Controls reading of data from the.

Reference numeral 7 is a rate latch, 8 is a full adder, and 9 is a latch, which form a DDA (Digital Differential Adder).

The rate latch 7 latches and outputs the data read from the memory 4. Read data is 8-bit data bus
Transferred by RD0-7.

Since the number of bits of data read from the memory 4 is larger than 8 bits, the upper bit and the lower bit are read separately according to the state of the least significant bit of the read address given to the memory 4. This least significant bit is the address bus
Transferred by RA0.

Further, since the number of bits of data latched in the rate latch 7 is larger than 8 bits, this data is latched in time division using the lower byte load signal ▲ ▼ and the upper byte load signal ▲ ▼. ▲
The control logic 6 generates ▼ and ▲ ▼.

The full adder 8 adds the outputs of the rate latch 7 and the latch 9 and gives the added value to the latch 9.

To the latch 9, the added value of the full adder 8 and the clock CLK1 from the control logic 6 are given. Latch 9
Latches the added value of the full adder 8 at the timing of the clock CLK1 and feeds the added value back to the input section of the full adder 8.

The full adder 8 adds the outputs of the rate latch 7 and the latch 9 and gives the added value to the latch 9. The carry signal ADDCY (pulse signal) is generated at the output of the latch 9 every time the most significant bit changes. The carry signal ADDCY becomes the output of the DDA circuit.

The pulse rate of the clock CLK1 is set to be higher than the pulse rates of the DLATCH signal and the ULATCH signal which latch the data in the rate latch 7.

Reference numeral 10 denotes an AND gate. The signal GC from the logic controller 6 allows the carry signal to pass before the down counter generates the count up signal, and prohibits the carry signal from passing when the count up signal occurs. The signal that has passed through the AND gate 10 becomes the output pulse of the pulse generation circuit.

11 is rate data control circuit at which the feature of the present invention, be provided in front of the preset buffer 1 _1, preset buffer 1 ₁ from the pulse output is completed in the previous sampling period in the next sampling period Measures the time until becomes ready and increases or decreases the pulse rate value preset in the preset buffer 1 ₁ according to the measured value. Pulse rate value depends on bus IDB0-7
The ▼ and ▲ ▼ are selectively used and given to the rate data control circuit 11. The increased / decreased pulse rate value is preset in the preset buffer 1 ₁ .

▲ ▼ is an initial reset signal given to the preset buffer 1, 11 ₁ , the down counter 2, the latches 3, 9, the control logic 6, and the rate latch 7.

▲ ▼, ▲ ▼, ▲
▼, ▲ ▼, ▲ ▼, ▲
The signal of ▼ is given from μP.

Next, the operation of such a pulse generating circuit will be described.

FIG. 2 is a time chart of each signal of the circuit of FIG.

First, the data of the number of pulses generated during one sampling period is
▼ Set in the preset buffer 1 by a signal.

At this time, the content of the most significant bit of the set value is set in the latch 3, and thereby the signal SIGN indicating the pulse direction is output.

When the data setting by ▲ ▼ is completed, the buffer write signal ▲ ▼ becomes high level,
As a result, the control logic 6 starts operating at the timing of the clock CLOCK, and the data of the output pulse number is loaded into the down counter 2 by the CLOAD signal.

On the other hand, the pulse rate data is
▼ signals and ▲ ▼ after being increased or decreased controlled by the rate data control circuit 11 by the timing signal is preset in the preset buffer 1 _1. In this case, ▲ ▼ signal and ▲ of the first sampling period
▼ The pulse rate data is set in the rate data control circuit 11 according to the signal timing, and the ▲ ▼ signal and ▲ of the next sampling cycle
▼ pulse rate data is increased or decreased controlled by the timing signal is preset to the preset buffer 1 _1.

When the preset of pulse rate data to the preset buffer 1 ₁ is completed, the buffer write signal ▲ ▼
Becomes high level, which enables the control logic 6 to access the memory 4 by the ROMOE signal.

Here, the preset buffer 1 ₁ of the preset value in the address read out data of the initial value or optimum output pulse rate of the full adder 8 from the memory 4, rate latch 7
Set to.

When setting is completed, the control logic 6 clocks
CLK1 is applied to the latch 9. As a result, the full adder 8 starts to move.

The latch 9 is the output of the full adder 8, that is, the rate latch 7
And the added value of the output of the latch 9 is latched and output at the cycle of the clock CLK1. The carry signal ADDCY is generated each time the most significant bit of the output of the latch 9 changes. The ADDCY signal is counted by the down counter 2.

At the same time the full adder 8 starts moving ▲ ▼ signals and ▲ ▼ signal goes low, the data of the output pulse count and pulse rate of the next sampling cycle is writable preset buffer 1 and 1 _1. The writing of the output pulse number and pulse rate data in the next sampling cycle is performed until the pulse output in the current sampling cycle is completed.

When the count of the down counter 2 becomes 0 and a count up signal is generated, the control logic 6 becomes a gate.
Close 10 to end the output of the pulse of this sampling cycle. At this time, when the data of the output pulse number is written in the preset buffer 1,
If the signal is at the high level, the operation after loading the data of the output pulse number into the down counter 2 is performed.

Here, the operation of the pulse data increase / decrease control by the rate data control circuit 11 will be described.

For the pulse rate setting data given by μP in the first sampling period and the second sampling period after the pulse generation circuit is activated, the rate data control circuit 11 (sampling period obtained from the setting data − and processing the set data to be Delta] t send the preset buffer 1 _1. here, Delta] t is sufficiently smaller than the period determined from the setting data, for example, about 10 [mu] s.

For the setting data of the third and subsequent sampling periods, the rate data control circuit 11 measures the time ti from when the ▲ ▼ signal becomes low level to when the ▲ ▼ signal becomes high level in the next sampling period. To do. The rate data control circuit 11 provides the preset buffer 1 ₁ by increasing or decreasing the pulse rate values as measured value becomes a value within a predetermined range.

As a result, the preset buffer is always in the ready state at a time point that is a predetermined time before the time point at which the data setting by the μP is performed.

An up counter may be used instead of the down counter 2.

Further, in the embodiment, the case where the preset buffer has one stage has been described, but the preset buffer may have two or more stages using a FIFO (first-in first-out memory) or the like. By doing so, the degree of freedom of the pulse number setting period of μP is increased and it becomes easier to use.

Further, the number of bits of the transfer signal of each bus may be other than that shown in the embodiment.

[Effect] According to the present invention, by controlling the pulse rate value, the preset buffer is always in the ready state at a time point that is a predetermined time before the time point at which the data setting by μP is performed. As a result, even if there is an error between the sampling cycle used to calculate the setting data and the actual sampling cycle, this error is absorbed inside the pulse generation circuit. Therefore, the error is not integrated even if the pulses are output continuously.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a pulse generating circuit according to the present invention, and FIG. 2 is an operation explanatory diagram of the circuit of FIG. 1 ... First preset buffer, 1 ₁ ... Second preset buffer, 2 ... Down counter, 4 ... Memory,
6 ... Control logic, 7 ... Rate latch, 8
…… Full adder, 9 …… Latch, 10 …… Gate, 11 …… Rate data control circuit.

Claims (1)

[Claims] 1. The data of the number of output pulses in one sampling cycle is preset, and the data of the number of output pulses of the next sampling cycle is preset during the sampling cycle of this time when the DDA circuit described later latches the data. The preset buffer of 1 and the pulse rate data of the output pulse are preset,
When the DDA circuit described later latches the data, the second preset buffer in which the data of the pulse rate of the next sampling period is preset during the current sampling period, and the preset value of the first preset buffer are set, and the pulse is set. , A counter that generates a count-up signal when the count changes by the set value, and data that gives an optimum pulse rate value corresponding to the preset value of the second preset buffer are stored. And a controller for reading an optimum pulse rate value from the memory by using the preset value of the second preset buffer as an address when a preset value is set in the counter, and a pulse rate value read by the controller. Latch this pulse A DDA circuit that generates a carry signal that becomes an output pulse in a cycle according to a rate value, a gate that prohibits passage of the carry signal when the count-up signal occurs, and terminates the generation of the output pulse, It is provided in the preceding stage of the second preset buffer, and measures the time from the completion of pulse output to the start of presetting to the second preset buffer in the next sampling cycle, and according to the measured value, the second A pulse generation circuit, comprising: a rate data control circuit for controlling a value preset in the preset buffer of.