JPH0715939B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a semiconductor device in which a plurality of MIS field effect transistors are formed on a semiconductor substrate formed on an insulating film, a channel stopper region that electrically separates each MIS field effect transistor is formed in the semiconductor device. By forming a high-concentration impurity region for contact in a part of the channel stopper region on the substrate, the high-concentration impurity region for contact is provided so that the channel stopper region and the gate of each MIS field effect transistor It becomes possible to set a common electric potential for the base body with a small occupation area.

[Industrial application field]

The present invention provides a plurality of MIS field-effect transistors (hereinafter MISFE) on a semiconductor substrate (hereinafter referred to as SOI) formed on an insulating film.
T. The present invention relates to a semiconductor device for forming a substrate, and more specifically, to a structure for setting the potential of the substrate under the gate of the MISFET so that a back channel does not occur in the substrate under the gate.

[Conventional technology]

A semiconductor device having an SOI structure has been attracting attention because it can be formed at a very small junction capacitance between a source and a drain to enable high-speed operation, or semiconductor elements can be stacked in a three-dimensional direction to achieve high integration. .

Such an SOI structure semiconductor device has a thick insulating film of, for example, about 1 μm formed on a silicon substrate and has a thickness of about 1 μm.
It is formed by forming a polycrystal silicon layer of about 5000 Å, polycrystallizing the polycrystal silicon layer by a laser annealing technique or the like to form a silicon substrate, and forming an element such as MISFET on the silicon substrate.

2 (a) to 2 (c) are diagrams showing the structure of a 6-transistor static memory cell composed of enhancement / depletion transistors of an n-channel MIS according to a conventional example, and FIG. 2 (a) is an equivalent circuit diagram. 2 (b) is a plan view and FIG. 2 (c) is a cross-sectional view taken along the arrow (AA).

In the figure, T1, T4 are depletion type n-MISFETs, T2,
T3, T5, T6 are enhancement type n-MISFETs (second
In FIG. 6B, the gate portion is shown by diagonal lines. ). W is a word line, which is formed of a polycrystalline silicon layer together with the gate electrode of the MISFET. BL1 and BL2 are each
The first and second bit lines, Vcc is a high potential power supply wiring, Vss is a ground potential power supply wiring, and these are formed of aluminum (Al).

Further, 1 is a silicon substrate, 2 is a thick silicon oxide film (SiO ₂ film) of about 1 μm, and 3 is a P-type silicon substrate. 4 is MISF
It is a high-concentration N-diameter diffusion layer that forms the source / drain of ET and is also used to reduce wiring resistance. Reference numeral 5 is a gate oxide film (SiO ₂ film), 7 is a block oxide film, and 6 is a polycrystalline silicon layer for a gate electrode. 8 is a PSG film for the cover.

[Problems to be solved by the invention]

As shown in the figure, since the blocking oxide film 7 and the PSG film 8 are formed between the MISFETs formed on the SOI and are electrically isolated from each other, proper circuit operation is possible.

By the way, since the thickness of the P-type silicon substrate 3 on SOI is about 5000 Å, which is relatively thin, even when the N-type diffusion layer 4 is formed by ion implantation, the depth thereof reaches the surface of the SiO ₂ film 2. become.

Therefore, the P-type silicon substrate under the gate electrode of each MISFET formed on the SOI is the MISF formed on the silicon substrate.
Unlike ET, it is in an electrically floating state.

When electrical noise is generated in the silicon substrate 1 for some reason for this, the surface of the silicon substrate 3 in contact with the SiO ₂ film 2 is N-type inverted through the SiO ₂ film 2, the leakage current between the source and the drain of the MISFET May occur.

Therefore, it is conceivable to provide a contact region for the substrate contact so that the P-type silicon substrate of each MISFET can be set to a constant potential. However, according to this method, it is necessary to provide contact regions for all MISFETs, and there is a problem in terms of high integration.

The present invention was created in view of such problems, and SO
When creating multiple MISFETs on I, each MISFET
It is an object of the present invention to provide a semiconductor device capable of ensuring stable operation and achieving high integration by setting the silicon substrate to a constant voltage.

[Means for solving problems]

According to the present invention, in a semiconductor device having a plurality of MIS field effect transistors in a one conductivity type semiconductor substrate formed on an insulating film, the semiconductor device is provided in the semiconductor substrate for electrically isolating each of the MIS field effect transistors. And a high-concentration one-conductivity type impurity region for contact formed in a part of the channel stopper region. The one conductivity type impurity region for the channel stopper and the substrate under the gate of each MIS field effect transistor are set to a constant common potential via the region.

[Action]

Between each MISFET formed in the SOI, a channel stopper region having the same conductivity type as the semiconductor substrate is formed instead of an insulating film such as a SiO ₂ film.

As a result, the semiconductor substrate under the gate electrode of each MISFET is electrically connected to the channel stopper region and the semiconductor substrate of another MISFET.

Further, since such continuous connection is made, a high-concentration impurity region for contact is formed in a part of the channel stopper region, and a predetermined power supply voltage is supplied through the impurity region, so that a plurality of contact regions can be formed. It becomes possible to set all of the semiconductor substrates of the MISFET at that voltage.

That is, it is possible to prevent the leakage current on the SOI due to the back channel of the MISFET while maintaining high integration.

〔Example〕

Next, examples will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of a semiconductor device according to an embodiment of the present invention, and the circuit function is the same as that of the circuit shown in FIG. 2 (a). 1 (a) is a plan view thereof, and FIG. 1 (b) is FIG. 1 (a).
FIG. 6 is a sectional view taken along line (A-A) shown in FIG.

FIG. 1 (a) corresponds to FIG. 2 (b), and FIG. 1 (b) corresponds to FIG. 2 (c), and the same reference numerals and the same numbers indicate the same things. The semiconductor device according to the embodiment of the present invention shown in FIG. 1 is basically different from the conventional device shown in FIG. 2 in that the separation between the MISFETs is performed by forming a channel stopper region instead of an insulating film. In addition, the potential of the P-type silicon substrate under the channel stopper region and the gate electrode of the MISFET is set to be constant.

That is, 9 is a P-type diffusion layer for the channel stopper (first
The shaded area in FIG. ), Which allows each MISF
The ETs (T1 to T6) are electrically separated. Further, 10 is a P-type diffusion layer for high-concentration contact, and 11 is a contact hole for connecting the Vss Al wiring and the P-type diffusion layer 10.

As described above, according to the embodiment of the present invention, by providing one contact P-type diffusion layer 10 for connecting to the ground power supply Vss, the channel stopper P-type diffusion layer 9 is interposed,
By setting the P-type silicon substrates of all MISFETs (T1 to T6) to the Vss potential, it becomes possible to prevent the occurrence of back channel leakage current.

In the embodiment, the n-channel MISFET is formed on the P-type silicon substrate 3.
Although the case of forming the p-channel MISFET has been described, the case of forming the p-channel MISFET on the N-type silicon substrate can be applied as it is by changing the impurity type of the channel stopper to N-type. The present invention is also applicable to semiconductor substrates other than silicon substrates.

Further, when the channel stopper region has a concentration suitable for ohmic contact, it is needless to say that it is not necessary to form a diffusion layer for contact.

〔The invention's effect〕

As described above, according to the present invention, the semiconductor substrates under the gates of the plurality of MISFETs formed on the SOI can be set to a predetermined voltage, so that it is possible to produce an element with a small leak current.

Further, since the area required for setting the potential of the semiconductor substrate of each MISFET can be reduced by utilizing the channel stopper region that electrically separates each MISFET, the degree of integration of semiconductor elements can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a configuration of a semiconductor device according to a conventional example. 1 ... Silicon substrate 2 ... SiO ₂ film 3 ... P-type silicon substrate (semiconductor substrate) 4 ... N-type diffusion layer 5 ... Gate oxide film 6 ... Gate electrode 7 ... Block oxide film 8 ... PSG film 9 …… P-type diffusion layer for channel stopper 10 …… P-type diffusion layer for contact 11 …… Contact hole

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 9056-4M H01L 29/78 311 X

Claims (1)

[Claims] 1. A semiconductor device comprising a plurality of MIS field effect transistors in a one-conductivity-type semiconductor substrate formed on an insulating film, wherein the semiconductor substrate for electrically isolating each of the MIS field effect transistors is provided. The semiconductor device includes a channel-stopper one-conductivity-type impurity region and a contact high-concentration one-conductivity-type impurity region formed in a part of the channel stopper region. A semiconductor device characterized in that the one conductivity type impurity region for the channel stopper and the substrate under the gate of each MIS field effect transistor are set to a constant common potential via a type impurity region.