JPH0722182B2 - Complementary semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary semiconductor device having low power consumption and suitable for high integration, more specifically, metal-insulator-semiconductor (hereinafter referred to as MI
It is a circuit element of a so-called MIS structure pair, that is, an interverter, which has a three-layer structure of S).

2. Description of the Related Art Reducing power consumption has become an important issue with the increase in scale of semiconductor integrated circuits.
MIS integrated circuits are suitable.

Conventionally, a circuit element of a unit forming a complementary MIS integrated circuit,
That is, the structure of the complementary MIS inverter was as shown in FIG.

This complementary MIS inverter has a P-type in the N-type semiconductor substrate 1.
The well 2, the P ^{+ type} source region 3 and the P ^{+ type} drain region 4 are formed, and the N ^{+ type} source region 5 and the N ^{+ type} source region 5 are formed in the well 2.
Drain region 6 is formed, and the source region 5 is formed between the source region 3 and the drain region 4 and the source region 5 is formed.
Gate insulating films 7 and 7'are formed on the well 2 between the drain region 6 and the drain region 6, and gate electrodes 8 and 8'connected to each other (not shown) are formed on the gate insulating film 7. Then, the element isolation insulating film 9 is selectively formed on the semiconductor substrate 1 and the well 2, and the interlayer insulating film 10 is formed on the gate electrode 8 and the element isolation insulating film 9. An output electrode 12 connected to the drain region 4 and the drain region 6 through a contact window 11 on the insulating film 10;
This is a structure in which a power supply line 13 connected to the source region 3 and a ground line 14 connected to the source region 5 are formed.

Problems to be Solved by the Invention In the above-described conventional complementary MIS inverter, the N-channel transistor and the P-channel transistor are formed in a positional relationship parallel to the main surface of the semiconductor substrate. Under such a structure, the distance between the source region or the drain region having the same conductivity type and the well or the semiconductor substrate should be less than the width of the depletion layer in order to prevent short circuit or leakage current. Also needs to be large, which inevitably leads to an increase in element area. Furthermore, P ^{+ type} drain region −
N type semiconductor substrate-P type well-N ^{+ type} drain region is PNPN
There is also a problem in that a so-called latch-up phenomenon occurs in which a junction is formed and it becomes a parasitic thyristor, which is turned off by an external voltage spike or the like.

Means for Solving the Problems In a complementary semiconductor device of the present invention for solving the above problems, a first conductivity type diffusion region serving as a source region of a first transistor is formed along a surface. A hole penetrating the first diffusion region is formed in the opposite-conductivity-type semiconductor substrate in which the first conductivity type second diffusion region to be the drain region of the first transistor is formed on the bottom surface of the hole. A first gate oxide film, a gate electrode, a second gate oxide film, a semiconductor film of one conductivity type to be a second transistor, an interlayer insulating film, and an output electrode are sequentially formed along the sidewall of the hole. A third diffusion region of opposite conductivity type formed in the semiconductor film near the bottom surface of the hole is connected to the second diffusion region by the output electrode, and the semiconductor is near the surface of the hole. The first in the membrane In this structure, a fourth diffusion region of the opposite conductivity type, which is the source region of the second transistor, is formed.

Action In the complementary semiconductor device of the present invention, the latch-up phenomenon can be completely prevented and the element area can be reduced without deteriorating the characteristics.

Embodiment An embodiment of the complementary semiconductor device of the present invention is shown in a sectional view in FIG. 1 and will be described with reference to this.

As shown, an N channel is formed on the surface of the P-type semiconductor substrate 21.
A source region 22 of the MIS transistor is formed, and a hole 23 is provided in the P-type semiconductor substrate 21 so as to penetrate the source region 22. The drain region 24 of the N-channel MIS transistor is formed on the bottom surface of the hole 23. Further, along the side wall of the hole 23, the gate insulating film 25 of the N-channel MIS transistor, the gate electrode 26, the gate insulating film 27 of the P-channel MIS transistor 27, the P-channel MIS transistor 28, the interlayer insulating film 29, and the output electrode 30 are sequentially formed. The drain region 31 of the P-channel MIS transistor 28 that is stacked and formed near the bottom surface of the hole 23 is connected to the drain region 24 of the N-channel MIS transistor by the output electrode 30. A source region 32 of the P-channel MIS transistor 28 is formed near the surface of the hole 23.

The channel region 33 of the N-channel MIS transistor
Are formed in a portion of the P-type semiconductor substrate 21 along the sidewall of the hole 23.

The source region 32 is the source side terminal of the inverter,
Reference numeral 22 corresponds to the ground side terminal of the inverter, and gate electrode 26 corresponds to the input terminal of the inverter.

In this complementary MIS inverter structure, the N-channel and P-channel MIS transistors are three-dimensionally arranged using the same hole 23, so that the area can be reduced as compared with the planar arrangement. . Further, since the gate length of the MIS transistor is determined by the depth of the hole 23, the short channel effect can be suppressed and the degree of integration can be increased while suppressing the punch through phenomenon.

Also, since no well is used, a PNPN junction is not formed,
Latch-up phenomenon does not occur.

In the embodiment shown in FIG. 1, the P-type semiconductor substrate is used and the P-channel MIS transistor is formed in the hole. However, this is an N-type semiconductor substrate and the N-channel MIS transistor is formed in the hole. You may form in.

Since the complementary semiconductor device of the present invention is composed of N-channel and P-channel MIS transistors which are three-dimensionally arranged using holes formed on the main surface of the semiconductor substrate, the gate length of the MIS transistor is It is determined by the depth of the hole rather than the opening area, and as a result, high integration can be achieved while suppressing the short channel effect and punch through phenomenon. Further, since the well is not used, a parasitic thyristor due to the PNPN junction is not formed, and the structure in which the latch-up phenomenon does not occur can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a complementary semiconductor device of the present invention, and FIG. 2 is a sectional view showing a conventional complementary semiconductor device. 21 …… P-type semiconductor substrate, 22,32 …… Source region, 23 ……
Hole, 24,31 …… Drain region, 25,27 …… Gate insulating film,
26 ... Gate electrode, 28 ... P-channel MIS transistor, 29 ... Interlayer insulating film, 30 ... Output electrode, 33 ... Channel region.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 29/786 9055-4M H01L 29/78 321 C 9056-4M 311 C 9056-4M 311 X

Claims (1)

[Claims] 1. A hole penetrating the first diffusion region is formed in a semiconductor substrate of opposite conductivity type in which a first diffusion region of one conductivity type serving as a source region of the first transistor is formed along the surface. A second diffusion region of one conductivity type, which becomes a drain region of the first transistor, is formed on the bottom surface of the hole, and a first gate oxide film is formed along the sidewall of the hole.
A gate electrode, a second gate oxide film, a semiconductor film of one conductivity type to be a second transistor, an interlayer insulating film, and an output electrode are sequentially stacked, and the opposite conductivity formed in the semiconductor film near the bottom surface of the hole. -Shaped third diffusion region and said second diffusion region are connected by said output electrode, and a fourth region of opposite conductivity type becomes a source region of said second transistor in said semiconductor film near the surface of said hole. A complementary semiconductor device having a diffusion region formed therein.