JPH0715975B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a control gate, and more particularly to an electrically rewritable memory device.

<Summary of the Invention> The present invention relates to an electrically rewritable nonvolatile memory element in which a floating gate and a control gate are provided on a semiconductor substrate via an insulating film, and a thin insulating film formed on the semiconductor substrate contains impurities. Is introduced to increase the barrier height on the side in contact with the floating gate and lower the barrier height on the side in contact with the n ⁺ layer of the semiconductor substrate to obtain good storage retention characteristics. In addition to holding, it facilitates carrier movement at the time of writing and erasing.

<Prior Art> A semiconductor element having a sectional structure shown in FIG. 3 is known as an electrically rewritable nonvolatile memory element having a floating gate.

In the figure, a memory transistor T _M and a select transistor T _S are formed in close proximity to each other on the same semiconductor substrate, and a p-type silicon substrate 10 having a LOCOS region formed by a thick oxide film is used for each transistor. N ⁺ regions 11a, 11b, and 11c to be the source and the drain are formed. An insulating film is formed so as to cover the semiconductor substrate 10, and the floating gate 16 is formed on the insulating film 13 in the memory transistor T _M portion.
However, a control gate 17 is further formed on the insulating film 15 in this order, and a gate electrode 18 is overlaid on the gate insulating film 14 in the selection transistor T _S portion.

The floating gate 16 that constitutes the memory transistor T _M
The control gate 17 is formed so as to cover not only the channel region of the transistor but also the extended portion thereof so as to cover part of the drain region 11b of the silicon substrate. The insulating film 12 interposed in the portion where the extended portion of the floating gate 16 covers the drain region 11b is formed thin in advance in order to facilitate the data writing and erasing operations.

That is, rewriting of data to the memory device is performed by selecting transistors
A high voltage is applied to the control gate 17 or the drain n ⁺ region 11a by applying a high voltage to the gate electrode 18 of T _S to make the n ⁺ region 11a and the n ⁺ region 11b conductive. And n
^A voltage is applied between the ⁺ regions 11b to cause a current to flow through the thin insulating film 12 to inject or flow out carriers into the floating gate 16 to perform a memory function.

<Problems to be Solved by the Invention> In the semiconductor memory device having the above element structure, a sufficient current flows through the thin insulating film 12 when a high voltage is applied at the time of rewriting the stored contents, and the stored contents are not changed at other times. It is necessary to secure the reliability of the insulating film 12.

Here, the thin insulating film 12 is formed after forming the n ⁺ region 11b on the semiconductor substrate 10, and the film quality thereof is uniform. However, this homogeneous insulating film has good memory retention characteristics when the barrier height for passing a current is high, but requires a high voltage for writing and erasing, and if the barrier height is lowered, the memory retention characteristics deteriorate. It was very difficult to obtain a proper insulating film.

<Means for Solving Problems> In order to eliminate the drawbacks in the conventional memory device,
According to the present invention, in the insulating film formed between the floating gate of the memory transistor portion and the semiconductor substrate, the barrier height of the insulating film is higher on the side in contact with the floating gate and on the side in contact with the n ⁺ region 11b on the semiconductor substrate. Lower to form. Such control of the barrier height is performed by introducing impurities by the ion implantation technique.

<Function> The insulating film under the floating gate is formed so that the barrier height against carrier movement is low on the side in contact with the n ⁺ region and high on the side in contact with the floating gate. In addition, it is possible to respond promptly, and the written contents can be held stably.

<Embodiment> FIGS. 1A, 1B and 1C are sectional views for explaining a manufacturing process of a semiconductor device according to the present invention.

A LOCOS region 29 made of a thick oxide film is formed on the p-type silicon substrate 20 so as to surround the device region, and a protective film 21 made of a relatively thin oxide film covering the device region forming a substantially flat surface.
Is formed. Since the protective film 21 forms a thin oxide film for passing a current when the stored contents are rewritten, an opening is formed in a part of the protective film 21.
A thin oxide film 22 having a film thickness of 150Å is formed.

A resist 28 is applied while leaving the thin oxide film 22 and its periphery, and arsenic or phosphorus is introduced as an impurity into the thin oxide film 22 portion by the ion implantation technique using the resist 28 as a mask. In this ion implantation step, in order to adjust the distribution of impurities in the oxide film 22 to a desired distribution, the projection range R _P is implanted with energy which is 1 to 5 times that of the thin oxide film 22. Impurities are introduced into the region not covered with the resist 28 by the ion implantation, but by selecting the energy at the time of ion implantation within the range of the projection range, the concentration distribution of the impurities in the thin insulating film 22 can be adjusted to the semiconductor substrate surface. It becomes higher as it approaches the formed n ⁺ region 23, and becomes highest at the portion in contact with the n ⁺ region 23.

After the ion implantation process, heat treatment is performed in an inert gas in order to recover the damage received in the ion implantation process, and a desired impurity concentration distribution is formed.

Fig. 2 shows the amount of arsenic implanted and the barrier height of the oxide film when ion-implanted with arsenic as an impurity and the R _P / SiO ₂ film thickness is set to 2 by the side curve A in contact with the n ⁺ region and the floating gate. A side curve B in contact with a certain polysilicon is shown. Incidentally, such a tendency was confirmed even in the element in which phosphorus was ion-implanted as an impurity.

As is clear from the figure, the barrier height on the n ⁺ region side decreases with an increase in the amount of arsenic implantation, and rewriting becomes easier, and the barrier height on the floating gate side remains high, and the memory retention characteristics are Show that you are excellent.

The n ⁺ region 23 formed in the semiconductor region in the step of implanting ions into the thin oxide film 22 forms an integral impurity region continuously with the n ⁺ region formed in the subsequent step.

On the semiconductor substrate which has undergone the ion implantation process, as shown in FIG.
Subsequently, the insulating film 25, the control gate 26, and the gate electrode 27 of the selection transistor are formed. Further, n ⁺ regions 23a, 23b, 23c to be a source or a drain are formed on the semiconductor substrate,
Contact holes, Al wirings, and the like are formed by a conventionally known technique to obtain the nonvolatile semiconductor device shown in FIG.

In order to facilitate writing and erasing to the memory element, the impurity distribution in the thin oxide film 22 is such that the concentration on the n ⁺ region side of the substrate is 2
It is important to increase it by a digit or more, and by setting the ratio of the oxide film thickness to the ion projection range R _{P in} the range of 1: 1 to 5, an impurity distribution satisfying the above conditions can be obtained.

<Effects of the Invention> As described above, according to the present invention, in an electrically rewritable non-volatile semiconductor device, the stored contents can be rewritten at a low voltage, and the written contents are reliably and stably retained. Therefore, the nonvolatile semiconductor memory device can be easily handled and the operation reliability can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a), (b) and (c) are sectional views for explaining an embodiment of the present invention, and FIG. 2 is an impurity implantation amount and barrier height in the same embodiment. FIG. 3 is a sectional view showing a conventional device. T _M : Memory transistor, T _S : Select transistor, 20: p
Type silicon substrate 23a, 23b, 23c: n ⁺ region, 22: thin oxide film, 2
4: Floating gate, 26: Control gate.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (1)

[Claims] 1. A storage device comprising an electrically rewritable non-volatile memory element in which a floating gate and a control gate are stacked on a semiconductor substrate with an insulating film interposed therebetween, wherein the floating gate is a source / drain of the semiconductor substrate. A part of the channel region and the drain high-concentration impurity region formed between the floating gate and the drain high-concentration impurity region, where the impurity concentration is low on the side in contact with the floating gate and in contact with the drain high-concentration impurity region. And a non-volatile semiconductor memory device characterized in that an insulating film having a high impurity concentration distribution is interposed.