Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPH0716008B2 - Method for manufacturing semiconductor device - Google Patents
[go: Go Back, main page]

JPH0716008B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH0716008B2
JPH0716008B2 JP63279843A JP27984388A JPH0716008B2 JP H0716008 B2 JPH0716008 B2 JP H0716008B2 JP 63279843 A JP63279843 A JP 63279843A JP 27984388 A JP27984388 A JP 27984388A JP H0716008 B2 JPH0716008 B2 JP H0716008B2
Authority
JP
Japan
Prior art keywords
oxide film
silicon oxide
thick silicon
diffusion layer
layer region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63279843A
Other languages
Japanese (ja)
Other versions
JPH02125617A (en
Inventor
修一 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63279843A priority Critical patent/JPH0716008B2/en
Publication of JPH02125617A publication Critical patent/JPH02125617A/en
Publication of JPH0716008B2 publication Critical patent/JPH0716008B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に絶縁破壊耐
圧の高いゲート酸化膜の形成法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate oxide film having a high dielectric breakdown voltage.

〔従来の技術〕[Conventional technology]

従来、半導体集積回路装置のゲート酸化膜は、第3図
(a)〜(b)が示すように、厚い酸化膜をドライ・エ
ッチングまたはウェット・エッチング法で開口した後、
改めて設計された規定膜厚となるように熱酸化法により
形成される。
Conventionally, as shown in FIGS. 3 (a) and 3 (b), a gate oxide film of a semiconductor integrated circuit device is formed by opening a thick oxide film by dry etching or wet etching.
It is formed by a thermal oxidation method so as to have a newly designed specified film thickness.

すなわち、従来のゲート酸化膜は、第3図(a)が示す
ように、厚いシリコン酸化膜31がエッチングでまず開口
され拡散層領域32が形成された後、そのまま拡散層領域
32上に設計膜厚のゲート酸化膜33が第3図(b)の如く
熱酸化法を用いて形成される。
That is, in the conventional gate oxide film, as shown in FIG. 3A, the thick silicon oxide film 31 is first opened by etching to form the diffusion layer region 32, and then the diffusion layer region is directly formed.
A gate oxide film 33 having a designed film thickness is formed on the film 32 by using a thermal oxidation method as shown in FIG.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

しかしながら、この方法によると拡散層領域32と厚い酸
化膜31との境界に薄いゲート酸化膜33のくびれ部34が形
成される。これは、拡散層領域32のシリコン基板を熱酸
化するとき酸化種の横方向の浸透が厚い酸化膜によって
阻止されこの部分で基板横方向の酸化が十分に行われな
いために生ずる。このようにゲート酸化膜にくびれ部が
生じ薄膜化する現象はゲート酸化膜の絶縁破壊耐圧を設
計値よりも低下させるため、集積回路の製造歩留りを著
しく低下させ、更には動作時における信頼性を大幅に低
下させる。
However, according to this method, the narrowed portion 34 of the thin gate oxide film 33 is formed at the boundary between the diffusion layer region 32 and the thick oxide film 31. This occurs because the lateral permeation of oxidizing species is blocked by the thick oxide film when the silicon substrate in the diffusion layer region 32 is thermally oxidized, and the lateral oxidation of the substrate is not sufficiently performed at this portion. The phenomenon in which the gate oxide film has a constricted portion and becomes thin as described above causes the dielectric breakdown voltage of the gate oxide film to be lower than the design value, thus significantly lowering the manufacturing yield of the integrated circuit and further improving the reliability during operation. Greatly reduce.

本発明の目的は、上記の情況に鑑み、厚い酸化膜との境
界にゲート酸化膜の薄いくびれ部を生じることなき半導
体装置の製造方法を提供することである。
In view of the above situation, an object of the present invention is to provide a method for manufacturing a semiconductor device without forming a thin constriction portion of a gate oxide film at a boundary with a thick oxide film.

〔課題を解決するための手段〕[Means for Solving the Problems]

本発明によれば、半導体装置の製造方法は、厚いシリコ
ン酸化膜を選択的に開口し拡散層領域を形成する工程
と、形成すべきゲート酸化膜の膜厚を超える比較的厚目
のシリコン酸化膜を前記拡散層領域上に形成する工程
と、前記厚いシリコン酸化膜との境界部を除く前記比較
的厚めのシリコン酸化膜内に、前記厚いシリコン酸化膜
あるいは前記厚いシリコン酸化膜の選択的開口に用いた
マスク材をイオン注入マスクにして、高濃度のイオンを
選択的にイオン注入する工程と、前記シリコン酸化膜の
高濃度イオン注入領域を前記拡散層領域上から除去する
選択的エッチング工程と、前記拡散層領域の露出面上に
ゲート酸化膜を形成する熱酸化工程とを含んで構成され
る。
According to the present invention, a method of manufacturing a semiconductor device includes a step of selectively opening a thick silicon oxide film to form a diffusion layer region, and a relatively thick silicon oxide film that exceeds the film thickness of a gate oxide film to be formed. Forming a film on the diffusion layer region, and selectively opening the thick silicon oxide film or the thick silicon oxide film in the relatively thick silicon oxide film excluding the boundary portion with the thick silicon oxide film. A step of selectively ion-implanting high-concentration ions using the mask material used for the above as an ion-implantation mask, and a selective etching step of removing the high-concentration ion-implanted region of the silicon oxide film from the diffusion layer region. And a thermal oxidation step of forming a gate oxide film on the exposed surface of the diffusion layer region.

〔実施例〕〔Example〕

以下図面を参照して本発明を詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings.

第1図(a)〜(e)は本発明の一実施例を示すゲート
酸化膜の形成工程図である。本実施例によれば、シリコ
ン基板上に化学的気相成長法(CVD法)で形成した厚さ6
000Åの厚いシリコン酸化膜11を弗酸を用いたウエット
・エッチング法で除去して拡散層領域12を形成する(第
1図(a))。次に熱酸化法により温度950℃の水素と
酸素の燃焼雰囲気内で膜厚800Åの比較的厚目のシリコ
ン酸化膜10を形成する。この時このシリコン酸化膜10と
厚い酸化膜11との境界部には膜厚が約500Åの第1のく
びれ14が形成される(第1図(b))。ついで、入射角
約40°の基板回転斜めイオン注入法を用いて、アルゴン
・イオンを加速電圧30keV、ドーズ量1×1414/cm2の条
件でイオン注入する(第1図(c))。この際、右方向
からの注入ビーム15はシリコン酸化膜の全面に注入され
るが、左方向からの注入ビーム16は厚い酸化膜11の影の
部分17には注入されないので、平均すると影の部分の注
入量はその他の部分に比べると少ない(第1図
(c))。次に、弗酸を用いたウエット・エッチング法
で全面エッチングを行う。このとき、イオンを注入され
たシリコン酸化膜10の部分領域は原子間の結合が乱れて
いるため、通常の熱酸化膜よりもエッチング速度が速い
ので、左からの注入ビームの影になってイオン注入量が
少なかった部分はイオン注入量が大きかった部分がエッ
チング除去されても原形をほぼ留めて残る(第1図
(d))。このような構造が得られた時間でウエット・
エッチングを停止する。この時、第1のくびれ14の部分
膜厚は約300Åとなる。ここで熱酸化法を用いてゲート
酸化膜13を温度900℃の酸素雰囲気内で膜厚200Åに形成
する。この時、酸化膜10との境界部には第2のくびれ18
が生ずるが、ゲート酸化膜13に接する酸化膜10の膜厚が
薄くて酸化種の供給が十分行われるため、その厚さは約
180Åにとどまる(第1図(e))。従来法によると、
くびれ34の酸化膜厚は100〜120Åと極めて薄くなるの
で、この部位における酸化膜厚の減少は格段に改善され
る。また第1のくびれ14の酸化膜厚は約300Åとなる
が、ゲート酸化膜厚よりは厚いのでゲート酸化膜13の絶
縁耐圧は影響されない。また、イオン注入に用いたアル
ゴンは、仮令シリコン基板内に到達しても電気的に中性
であるため、拡散層領域12内に形成するMOSトランジス
タまたはMOSキャパシタの電気的特性に影響を与えるこ
とはない。
FIGS. 1A to 1E are process diagrams of forming a gate oxide film showing an embodiment of the present invention. According to this embodiment, the thickness 6 formed by the chemical vapor deposition method (CVD method) on the silicon substrate
The 000Å thick silicon oxide film 11 is removed by a wet etching method using hydrofluoric acid to form a diffusion layer region 12 (FIG. 1 (a)). Next, a relatively thick silicon oxide film 10 having a film thickness of 800 Å is formed in a combustion atmosphere of hydrogen and oxygen at a temperature of 950 ° C. by a thermal oxidation method. At this time, a first constriction 14 having a thickness of about 500Å is formed at the boundary between the silicon oxide film 10 and the thick oxide film 11 (Fig. 1 (b)). Next, argon ions are ion-implanted under the conditions of an acceleration voltage of 30 keV and a dose amount of 1 × 14 14 / cm 2 by using a substrate rotating oblique ion implantation method with an incident angle of about 40 ° (FIG. 1 (c)). At this time, the injection beam 15 from the right direction is injected to the entire surface of the silicon oxide film, but the injection beam 16 from the left direction is not injected to the shaded portion 17 of the thick oxide film 11, so the shadowed portion on average. Is smaller than the other portions (Fig. 1 (c)). Next, the entire surface is etched by a wet etching method using hydrofluoric acid. At this time, since the interatomic bonds are disturbed in the partial region of the silicon oxide film 10 into which the ions have been implanted, the etching rate is faster than that of a normal thermal oxide film, so that the ions are shadowed by the implantation beam from the left. The portion where the implantation amount is small remains almost in its original shape even if the portion where the implantation amount is large is removed by etching (FIG. 1 (d)). Wet in the time when such a structure was obtained
Stop etching. At this time, the partial film thickness of the first constriction 14 becomes about 300Å. Here, the gate oxide film 13 is formed to a film thickness of 200 Å in an oxygen atmosphere at a temperature of 900 ° C. by using a thermal oxidation method. At this time, the second constriction 18 is formed at the boundary with the oxide film 10.
However, since the thickness of the oxide film 10 in contact with the gate oxide film 13 is thin and the oxidizing species are sufficiently supplied, its thickness is about
It stays at 180Å (Fig. 1 (e)). According to the conventional method,
Since the oxide film thickness of the constriction 34 is extremely thin at 100 to 120Å, the reduction of the oxide film thickness at this portion is remarkably improved. The oxide film thickness of the first constriction 14 is about 300Å, but since it is thicker than the gate oxide film thickness, the withstand voltage of the gate oxide film 13 is not affected. Further, since the argon used for ion implantation is electrically neutral even when it reaches the temporary silicon substrate, it may affect the electrical characteristics of the MOS transistor or MOS capacitor formed in the diffusion layer region 12. There is no.

第2図(a)〜(e)は本発明の他の実施例を示すゲー
ト酸化膜の形成工程図である。本実施例によれば、シリ
コン基板上にCVD法で形成した厚さ6000Åの厚いシリコ
ン酸化膜21上に厚さ2000Åの窒化膜をやはりCVD法で形
成する。つぎに、この窒化膜をドライ・エッチングでパ
ターニングしてマスク用窒化膜30を形成し、ついでこの
マスク用窒化膜30をマスクにして厚い酸化膜21を弗酸で
選択的にエッチング除去し、拡散層領域22を形成する
(第2図(a))。次に前実施例と同様、熱酸化法によ
り温度950℃の水素と酸素の燃焼雰囲気内で膜厚800Åの
比較的厚目のシリコン酸化膜20を形成する。この場合、
やはり厚いシリコン酸化膜21とシリコン酸化膜20との境
界部に酸化膜厚が約500Åのくびれ24が形成される(第
2図(b))。次に、通常の垂直イオン注入法を用いて
アルゴン・イオン25を加速電圧30keV、ドーズ量1×10
14/cm2の条件でイオン注入する(第2図(c))。この
際、アルゴンのイオン注入ビーム25は、マスク用窒化膜
30のひさしの影26で遮えぎられ、厚いシリコン酸化膜21
とシリコン酸化膜20との境界近傍には到達しない。つい
で、弗酸を用いたウエット・エッチング法で全面エッチ
ングを行う。このときイオン注入された部分のシリコン
酸化膜20はエッチング速度が増速されているためマスク
用窒化膜30のひさしで遮えぎられた部分が第2図(d)
に示すように残る。このような構造が得られた時間でウ
エット・エッチングを停止する。この時、第1のくびれ
24の部分膜厚は約350Åとなる。ここで、熱リン酸でマ
スク用窒化膜30を除去した後、熱酸化法を用いてゲート
酸化膜23を温度900℃の酸素雰囲気内で膜厚200Åに形成
する。このとき、第2のくびれ部28の酸化膜厚は前実施
例と同様に180Åである。すなわち、従来法による100〜
120Åの膜厚と比べてくびれ部における酸化膜厚の減少
は格段に改善される。本実施例で用いるマスク用の半導
体膜には、炭化ケイ素等の弗酸ではエッチングされず、
かつ、酸化雰囲気内で変形,消滅しない材料であれば窒
化膜に代えて用いることができる。また、前実施例で用
いた基板回転斜めイオン注入法のような複雑な装置を必
要としないので簡便に実施することができる。
2 (a) to 2 (e) are process diagrams of forming a gate oxide film showing another embodiment of the present invention. According to this embodiment, a 2000 Å-thick nitride film is also formed by the CVD method on the thick 6000 Å-thick silicon oxide film 21 formed on the silicon substrate by the CVD method. Next, this nitride film is patterned by dry etching to form a masking nitride film 30, and then the thick oxide film 21 is selectively removed by etching with hydrofluoric acid using the masking nitride film 30 as a mask, and diffusion is performed. A layer region 22 is formed (FIG. 2 (a)). Next, as in the previous embodiment, a relatively thick silicon oxide film 20 having a film thickness of 800 Å is formed by a thermal oxidation method in a combustion atmosphere of hydrogen and oxygen at a temperature of 950 ° C. in this case,
A constriction 24 having an oxide film thickness of about 500Å is formed at the boundary between the thick silicon oxide film 21 and the silicon oxide film 20 (FIG. 2 (b)). Next, using a normal vertical ion implantation method, argon ions 25 are accelerated at a voltage of 30 keV and a dose amount of 1 × 10 5.
Ions are implanted under the condition of 14 / cm 2 (Fig. 2 (c)). At this time, the ion implantation beam 25 of argon is used as the mask nitride film.
Blocked by 30 eaves shadows 26, thick silicon oxide film 21
Does not reach the vicinity of the boundary between the silicon oxide film 20 and the silicon oxide film 20. Then, the entire surface is etched by the wet etching method using hydrofluoric acid. At this time, since the etching rate of the ion-implanted portion of the silicon oxide film 20 is increased, the portion of the mask nitride film 30 shielded by the eaves is shown in FIG. 2 (d).
Remains as shown in. The wet etching is stopped at the time when such a structure is obtained. At this time, the first constriction
The partial film thickness of 24 is about 350Å. Here, after removing the masking nitride film 30 with hot phosphoric acid, the gate oxide film 23 is formed to a film thickness of 200 Å in an oxygen atmosphere at a temperature of 900 ° C. by using a thermal oxidation method. At this time, the oxide film thickness of the second constricted portion 28 is 180Å as in the previous embodiment. That is, the conventional method 100-
The reduction of the oxide film thickness in the constricted part is markedly improved compared with the film thickness of 120Å. The semiconductor film for a mask used in this example is not etched with hydrofluoric acid such as silicon carbide,
In addition, any material that does not deform or disappear in an oxidizing atmosphere can be used instead of the nitride film. Further, since a complicated device such as the substrate rotating oblique ion implantation method used in the previous embodiment is not required, it can be easily carried out.

〔発明の効果〕〔The invention's effect〕

以上説明したように、本発明によれば、拡散層領域と素
子分離領域を形成する厚いシリコン酸化膜との境界部に
ゲート酸化膜厚より厚い酸化膜の領域を形成することが
できるので、ゲート酸化膜のくびれ部の膜厚の減少を従
来法に比べて格段に改善することができ、ゲート酸化膜
の絶縁破壊耐圧の低下を大幅に改善することができる。
従ってこれにより、集積回路装置の製造歩留りを著しく
向上することが可能となり、また、その動作時における
信頼性を大幅に向上せしめ得る。
As described above, according to the present invention, an oxide film region thicker than the gate oxide film thickness can be formed at the boundary between the diffusion layer region and the thick silicon oxide film forming the element isolation region. The reduction in the film thickness of the constricted portion of the oxide film can be remarkably improved as compared with the conventional method, and the reduction in the dielectric breakdown voltage of the gate oxide film can be significantly improved.
Therefore, the manufacturing yield of the integrated circuit device can be remarkably improved, and the reliability in the operation thereof can be remarkably improved.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(e)は本発明の一実施例を示すゲート
酸化膜の形成工程図、第2図(a)〜(e)は本発明の
他の実施例を示すゲート酸化膜の形成工程図、第3図
(a)〜(b)は従来のゲート酸化膜の形成工程図であ
る。 11,21…厚いシリコン酸化膜、12,22…拡散層領域、13,2
3…ゲート酸化膜、10,20…シリコン酸化膜、14,24…第
1のくびれ、15…右からのイオン注入ビーム、16…左か
らのイオン注入ビーム、17…イオン注入の影、18,28…
第2のくびれ、25…アルゴン・イオン・ビーム、26…マ
スク用窒化膜のひさしの影、30…マスク用窒化膜。
1 (a) to 1 (e) are process diagrams of forming a gate oxide film showing an embodiment of the present invention, and FIGS. 2 (a) to 2 (e) are gate oxide films showing another embodiment of the present invention. And FIG. 3A and FIG. 3B are process diagrams of forming a conventional gate oxide film. 11,21… Thick silicon oxide film, 12,22… Diffusion layer region, 13,2
3 ... Gate oxide film, 10, 20 ... Silicon oxide film, 14, 24 ... First constriction, 15 ... Ion implantation beam from right side, 16 ... Ion implantation beam from left side, 17 ... Shadow of ion implantation, 18, 28 ...
Second constriction, 25 ... Argon ion beam, 26 ... Shadow of mask mask eaves, 30 ... Mask nitride film.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】厚いシリコン酸化膜を選択的に開口し拡散
層領域を形成する工程と、形成すべきゲート酸化膜の膜
厚を超える比較的厚目のシリコン酸化膜を前記拡散層領
域上に形成する工程と、前記厚いシリコン酸化膜との境
界部を除く前記比較的厚目のシリコン酸化膜内に、前記
厚いシリコン酸化膜あるいは前記厚いシリコン酸化膜の
選択的開口に用いたマスク材をイオン注入マスクにし
て、高濃度のイオンを選択的にイオン注入する工程と、
前記シリコン酸化膜の高濃度イオン注入領域を前記拡散
層領域上から除去する選択的エッチング工程と、前記拡
散層領域の露出面上にゲート酸化膜を形成する熱酸化工
程とを含むことを特徴とする半導体装置の製造方法。
1. A step of selectively opening a thick silicon oxide film to form a diffusion layer region, and a relatively thick silicon oxide film exceeding the film thickness of a gate oxide film to be formed on the diffusion layer region. In the step of forming and in the relatively thick silicon oxide film excluding the boundary with the thick silicon oxide film, the thick silicon oxide film or the mask material used for the selective opening of the thick silicon oxide film is ionized. Using an implantation mask to selectively implant high-concentration ions,
A selective etching step of removing a high-concentration ion implantation region of the silicon oxide film from the diffusion layer region; and a thermal oxidation process of forming a gate oxide film on the exposed surface of the diffusion layer region. Of manufacturing a semiconductor device.
JP63279843A 1988-11-04 1988-11-04 Method for manufacturing semiconductor device Expired - Lifetime JPH0716008B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63279843A JPH0716008B2 (en) 1988-11-04 1988-11-04 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63279843A JPH0716008B2 (en) 1988-11-04 1988-11-04 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02125617A JPH02125617A (en) 1990-05-14
JPH0716008B2 true JPH0716008B2 (en) 1995-02-22

Family

ID=17616706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63279843A Expired - Lifetime JPH0716008B2 (en) 1988-11-04 1988-11-04 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0716008B2 (en)

Also Published As

Publication number Publication date
JPH02125617A (en) 1990-05-14

Similar Documents

Publication Publication Date Title
US4925807A (en) Method of manufacturing a semiconductor device
US5473184A (en) Semiconductor device and method for fabricating same
JPS6260817B2 (en)
EP0209939B1 (en) Method of manufacturing a semiconductor device
US5773339A (en) Method of making diffused layer resistors for semiconductor devices
JPH0669099B2 (en) MIS type semiconductor device
US5698468A (en) Silicidation process with etch stop
US6316804B1 (en) Oxygen implant self-aligned, floating gate and isolation structure
US5763316A (en) Substrate isolation process to minimize junction leakage
JPS6289357A (en) Manufacture of low resistivity region with low defect density in bipolar integrated circuit
JPH0640549B2 (en) Method for manufacturing MOS semiconductor device
JPH0716008B2 (en) Method for manufacturing semiconductor device
JPH0697667B2 (en) Method for manufacturing semiconductor device
JPS5923476B2 (en) Manufacturing method of semiconductor device
JPS605065B2 (en) Manufacturing method of MIS type semiconductor device
JPH10308448A (en) Isolation film for semiconductor device and method for forming the same
JP3360970B2 (en) Method for manufacturing semiconductor device
EP0292042B1 (en) Semiconductor fabrication process using sacrificial oxidation to reduce tunnel formation during tungsten deposition
JPH04290273A (en) Manufacture of silicon nitride capacitor
JP2890550B2 (en) Method for manufacturing semiconductor device
JP3224432B2 (en) Method for manufacturing semiconductor device
JPH02186625A (en) Manufacture of semiconductor device
JP3009683B2 (en) Method for manufacturing semiconductor nonvolatile memory element
JPS6154661A (en) Manufacture of semiconductor device
JPH08204189A (en) Manufacture of semiconductor device