JPH071864B2 - Switch circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch circuit that controls transmission of an output signal of an amplifier circuit.

Conventional technology An amplifier circuit integrated in an IC (integrated circuit) uses a current mirror circuit composed of NPN transistors or a current mirror circuit composed of PNP transistors as an output buffer circuit. In many cases, the collectors are commonly connected and the output signal is transmitted from the common connection point to the input of the next-stage amplifier. Such a switching operation of the conventional amplifier circuit has been performed by switching the gain of the amplifier circuit.

FIG. 4 is a specific circuit configuration diagram of an amplifier circuit that performs the above switching operation. In the figure, 1 to 4 are PNP type transistors, 5 to 8 and 25 are NPN type transistors, and 10 is a power supply voltage. Power supply terminal to be supplied, 11 is an AC ground terminal to which a predetermined DC potential is given, 12 and 13 are differential input terminals, 14 is an output terminal, 1
Reference numeral 5 is a control terminal to which a control signal for switching operation is given, 16 is a current source, 17 to 22 are resistors, and 23 is a load resistor.

Then, the transistors 5 and 6 form a differential circuit, and amplify the input signals input to their bases through the differential input terminals 12 and 13. The collector current of the transistor 6 is mirror-inverted by the current mirror circuit composed of the transistors 3 and 4, and the collector current of the transistor 5 is the transistors 1 and 2.
After being mirror-inverted by a current mirror circuit consisting of, the output current is further mirror-inverted by a current mirror circuit consisting of transistors 7 and 8 and amplified so that complementary output transistors 4 and 8 are alternately conducted. Take action. If the characteristics of the transistors 5 and 6 forming the differential circuit and the transistors forming the current mirror circuits are balanced, the direct current component of the collector current of the transistor 4 and the direct current component of the collector current of the transistor 8 cancel each other out. Therefore, the output current of only the AC component is given to the resistor 23. Therefore, the signal output to the output terminal 14 has a DC output potential determined by a predetermined DC voltage externally applied to the AC ground terminal 11, and the AC gain is the operating current of the transistors 5 and 6 and the resistance value of the load resistor 23. Determined by the relationship.

Next, the switching operation will be described. When the control voltage input to the control terminal 15 is a low potential close to the ground potential, the transistor 25 is in the cutoff state, and the operation of the differential circuit described above is executed as it is. When the control voltage input to the control terminal 15 is at a high potential close to the power supply voltage, the transistor 25 becomes conductive, the transistors 5 and 6 become cut off, and the amplification operation is stopped, and the output currents of the transistors 4 and 8 become Both the DC component and the AC component become zero, and no signal is output to the output terminal 14.

An example of a conventional switch circuit in which a 1-input multi-output circuit is configured by using the above-mentioned amplifier circuit will be described with reference to FIG.

In FIG. 5, 26 is an input terminal, 36 to 38 are amplifiers, and 30 to
Reference numeral 31 is a control terminal to which a control voltage is input, and 33 to 35 are output buffer circuits associated with the amplifiers 36 to 38, respectively. The amplifiers 36 to 38 in FIG. 5 correspond to the transistors 5 and 6 in FIG. 4,
The output buffer circuit of FIG. 5 corresponds to the transistor 4 of FIG.
And 8 are equivalent. And the switch circuit of FIG.
In accordance with the number of output terminals 27 to 29, amplifiers 36 to 38 and output buffer circuits 33 to 35 are provided respectively, and the input terminals of the amplifiers 36 to 38 are commonly connected to the input terminal 26.

Problems to be Solved by the Invention In the switch circuit using the amplifier as described above, the response time from the application of the control signal to the response of the output is long,
It was not suitable for high-speed switching operation. Further, when a one-input multi-output circuit is constructed by using the same amplifier, there is a drawback that the number of elements constituting the amplifier and the output buffer circuit is considerably increased.

The present invention solves the above-mentioned problems and speeds up the response speed of the output with respect to the control signal and enables high-speed switching operation. Another object of the present invention is to provide a switch circuit capable of significantly reducing the number of elements constituting the circuit when the present invention is used to form a one-input multi-output circuit.

Means for Solving the Problems In order to achieve the above object, the switch circuit of the present invention comprises:
A differential circuit and a one conductivity type output transistor (4) whose emitter is coupled to a power supply terminal (10) through a first resistor (20) and which mirrors one output current of the differential circuit. Mirror inversion of the other output current of the differential circuit, which has a first current mirror circuit that is inverted and an output transistor (8) of the opposite conductivity type whose emitter is grounded through the second resistor (22). A second current mirror circuit, an output terminal (14) connected to a common connection point of the outputs of the first and second current mirror circuits, and an output terminal of each of the first and second current mirror circuits. And switching means (9) for controlling the conduction between the emitters of the transistors.

Operation With the above configuration, when the switching means is turned on, the base and emitter of each output transistor are reverse-biased and cut off, and the signal amplified by the differential circuit is not output. On the contrary, when the switching means cuts off, the reverse bias between the base and emitter of the output transistor is released, and the signal amplified by the differential circuit is output as it is. Since such a switching operation is performed by directly controlling the emitter potential of the output transistor, the responsiveness of the switching operation is good and a high-speed switching operation becomes possible.

When this switch circuit is used in a one-input multi-output circuit, a pair of complementary output transistors and switching means may be provided according to the required number of output terminals, and a plurality of differential circuits can be avoided. It is possible to significantly reduce the number of elements constituting the circuit.

Embodiment One embodiment of the switch circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of an embodiment of a switch circuit of the present invention, in which 1 to 4 are PNP type transistors, and 5 to
Reference numeral 9 is an NPN transistor, 10 is a power supply terminal to which a power supply voltage is supplied, 11 is an AC ground terminal to which a predetermined DC potential is applied, 12 and 13 are differential input terminals, 14 is an output terminal, and 15 is a switching operation. A control terminal to which a control signal is given, 16 is a current source, 17
22 to 24 are resistors, and 23 is a load resistor. Although the basic configuration of the circuit is almost the same as that of the conventional example shown in FIG. 4, in the conventional example shown in FIG.
In 5), the operating current at the common emitter connection point of the transistors 5 and 6 of the differential pair was controlled, but the present embodiment shown in FIG.
A significant difference is that a switching means (transistor 9) is provided between the emitters of the output transistors 4 and 8, and the resistor 24 is for limiting the current.

The operation of this circuit will be described below. When the control voltage input to the control terminal 15 is a low voltage close to the ground potential, the transistor (switching means) 9 is in the cut-off state, the entire circuit functions as a normal differential amplifier circuit, and the differential input terminal 12
Amplifies the input signal input to the input terminals 13 and 13 and outputs the output signal from the output terminal 14. Next, when the control voltage input to the control terminal 15 is a high voltage close to the power supply potential, the transistor (switching means) 9 becomes conductive and the voltage drop across the resistors 20 and 22 is increased to increase the voltage of the transistor 4. The emitter potential is lowered and the emitter potential of the transistor 8 is raised. On the other hand, the differential circuit (transistor 5,
The operating current of 6) is set to a predetermined value by the current source 16, and the voltage across the terminals of the input means (transistor 3 and resistor 19) of the first current mirror circuit does not change depending on the operating state of the switching means. . Similarly, the voltage across the terminals of the input means (transistor 7 and resistor 21) of the second current mirror circuit does not change depending on the operating state of the switching means. Therefore, when the transistor 9 is turned on, the bases and emitters of the output transistors 4 and 8 are reverse-biased, and the transistors 4 and 8 are cut off at the same time. Since the operation is switched by directly controlling the emitter potentials of the output transistors 4 and 8, the responsiveness of the switching operation is good, and the high-speed switching operation is also possible.

Next, another embodiment shown in FIG. 2 will be described. This embodiment is a specific example in which a 1-input 2-output circuit is constructed based on the switch circuit of FIG. 1, and the base of the transistor 40 is newly connected to the base of the output transistor 4 of the first current mirror circuit. The base of the transistor 41 is newly and commonly connected to the base of the output transistor 8 of the second current mirror circuit, the output terminal 43 is added to the common connection point of the collectors of the transistors 40 and 41, and the transistor 42 which is the second switching means. Is added between the emitters of the transistors 40 and 41. And 45 to 48 are resistors,
Resistance values of 47 and 20, resistance values of resistors 46 and 22, and resistance 48
The resistance values of 23 and 23 are equal.

As shown in FIG. 2, while the differential circuits 5 and 6 on the input side are single, the output transistors 4 and 8 connected to the output terminal 14 and the output transistors connected to the output terminal 43 40,
41 is driven in parallel and the control voltage is applied to control terminal 15 or 44.
By selectively inputting to the output terminal, the output signal is selectively output to the corresponding output terminal 14 or 43.

In the circuit configuration of FIG. 2, a pair of PNP-type and NPN-type output transistors and switching means may be provided according to the required number of output terminals, and duplication of differential circuits can be avoided.
The number of elements constituting the circuit can be significantly reduced.

FIG. 3 is a block diagram showing an embodiment in which the number of outputs is larger than that of the embodiment shown in FIG. 2, in which an input signal inputted from the input terminal 26 is amplified by a single amplifier 39, and the control terminal 3
The output buffer circuits 33, 34, and 35 individually having 0, 31, and 32 are connected in parallel to the output terminal of the amplifier 39.
A control voltage is selectively applied from and 32, and the output voltage is selectively taken out from the corresponding output terminals 27, 28 and 29. According to this, the control of the extraction of the output signal is individually performed by the plurality of output buffer circuits, and one amplifier is sufficient.

EFFECTS OF THE INVENTION As described above, the switch circuit of the present invention directly controls the emitter potential of the output transistor to perform the switching operation, so that the switching operation has a high responsiveness and a high-speed switching operation is possible.

When this switch circuit is used in a one-input multi-output circuit, a pair of complementary output transistors and switching means may be provided according to the required number of output terminals, and duplication of differential circuits can be avoided. The particular effect is that the number of elements constituting the circuit can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment according to a switch circuit of the present invention, FIG. 2 is a circuit configuration diagram of another embodiment, and FIG. 3 is a block configuration diagram of a 1-input multi-output circuit using the present invention. FIG. 4 is a circuit configuration diagram of a conventional switch circuit, and FIG. 5 is a block configuration diagram of a 1-input multi-output circuit using a conventional switch circuit. 1-4,40 …… PNP type transistor, 5-9,41,42 …… NP
N-type transistor, 10 ... power supply terminal, 11 ... AC ground terminal, 12, 13 ... differential input terminal, 14, 43 ... output terminal, 1
5,44,30〜32 …… Control terminal, output buffer circuit.

Claims (1)

[Claims] 1. A first circuit which has a differential circuit and an output transistor of one conductivity type whose emitter is coupled to a power supply terminal through a first resistor and which mirror-inverts one output current of the differential circuit. And a second current mirror circuit which has a reverse-conductivity-type output transistor whose emitter is grounded via a second resistor and which mirror-inverts the other output current of the differential circuit, An output terminal connected to a common connection point of the outputs of the first and second current mirror circuits and a switching means for controlling conduction between the emitters of the output transistors of the first and second current mirror circuits. Switch circuit equipped.