JPH0719225B2 - Information processing equipment - Google Patents

Description

TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly to a cache control method for the information processing apparatus.

2. Description of the Related Art Conventionally, in an information processing device, cache memory control is performed so that writing to the cache memory by block transfer from the main memory device and a read request to the cache memory that follows the cache memory do not conflict with each other. .

That is, when a buffer for holding the data of the block transfer is provided between the main memory device and the cache memory and the data transferred in the block is stored in the buffer,
There is a method of controlling such that the stored data is written in the cache memory at the time of the next block transfer or used for the subsequent read request. In this method, the buffer prevents the block transfer on the cache memory and the subsequent read request from conflicting with each other. This method is described in detail in Japanese Patent Publication No. 53-24260.

In addition, when writing to the cache memory by block transfer, the write register data width is set to an integer multiple of the block transfer data width to reduce the number of write operations. There is also a method of controlling to process. This method is described in detail in JP-A-57-105879.

In such a conventional information processing apparatus, a buffer for holding block transfer data is provided between the main storage device and the cache memory so that the block transfer on the cache memory and the subsequent read request do not conflict with each other. If you want to control the cache by this method, it is necessary to install a buffer that can request read of one block.
In addition, when cache control is performed by a method of setting the data width of the write register to be an integral multiple of the data width of block transfer so that block transfer on the cache memory and subsequent read requests do not conflict, Since it is necessary to install a write path in the cache memory that is an integral multiple of the data width of, there is a drawback that the amount of hardware increases.

The present invention has been made to eliminate the above-mentioned drawbacks of the conventional ones, and is realized with a small amount of hardware, and block transfer and subsequent read requests can be simultaneously processed on the cache memory without conflict. It is an object of the present invention to provide an information processing device that can perform

Advantageous Effects of Invention An information processing apparatus according to the present invention stores a read request, a storage unit, a write level of write data block-transferred from a main storage device by a first read request set in the storage unit, and the storage unit. A plurality of levels of cache memory capable of simultaneously processing the writing of the write data and the reading of the read data when the read level of the read data read by the subsequent second read request set in the means is different; Detecting means for detecting a match between the write level according to the first read request and the read level according to the second read request, and read by the second read request for which a match is detected by the detecting means Suppression means for suppressing the transfer of the read data, and reset for resetting the second read request in the storage means. And a setting means.

EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the cache memory according to one embodiment of the present invention has a 4-level structure, and the address of the data registered in the cache memory is divided into address arrays corresponding to the level structure (4 levels) of the cache memory. The data stored and registered in the address array 2 composed of (AA) 21 to 24 are stored in the data arrays (DA) 10 to 13 divided corresponding to the level configuration of the cache memory.

Addresses are supplied to the data arrays 10 to 13 from address registers (AR) 6 to 9 provided correspondingly.

A read request address from a read request source (not shown) input via the address line 100 is stored in the address register (ADAR) 1, and this read request address is compared with the address array 2 via the signal line 101. Circuit 3, address register (ADBR) 5, and address registers 6-9
Are sent to and respectively.

In the address array 2, each address array 21 to 24 is read by the read request address sent from the address register 1.
Are indexed and the index result is output to the comparison circuit 3.

In the comparison circuit 3, comparators 31 to 34 provided corresponding to the address arrays 21 to 24 compare the index result from the address arrays 21 to 24 with the read request address from the address register 1. That is, each of the comparators 31 to 34 determines whether or not the data designated by the read request address has been registered in the cache memory.

When any of the comparators 31 to 34 determines that the data has been registered in the cache memory, the comparison circuit 3 outputs the hit level to the control block 4 and the hit level register 14 via the signal line 102.

At the next timing, the read request address from the address register 1 is stored in the address register 5, and a part of the read request address is stored in the address registers 6 to 9 as an address to the data arrays 10 to 13. Further, the hit level from the comparison circuit 3 is stored in the hit level register 14.

In the data arrays 10 to 13, data is read by supplying addresses from the address registers 6 to 9, and these data are output to the read data register (RDR) 17 via the data lines 105 to 108.

In the read data register 17, one of the data from the data arrays 10 to 13 is selected and stored according to the hit level from the hit level register 14 input via the signal line 109, and stored in the read data register 17. The generated data is transferred to the read request source via the data line 111.

When the comparators 31 to 34 determine that the read-requested data is not registered in the cache memory, the read-request address stored in the address register 5 is the address line.
It is transferred to the address register (ADCR) 15 via 103,
This read request address is stored in the address register 15.

At this time, a block transfer is started to the main memory (not shown), and a block transfer level indicating which level of the data array 10 to 13 the block transfer data is written is created. The level is stored in the block transfer level register 16.

When the block transfer data is transferred from the main storage device, the block transfer data is input to and stored in the write data register (WDR) 18 via the data line 112.

A write address to the data arrays 10 to 13 is generated from the read request address stored in the address register 15, and the write address is sent to the address registers 6 to 9 via the address line 104. Further, the write address is stored in the address registers 6 to 9 corresponding to the block transfer level stored in the block transfer level register 16.

Therefore, the data array 10 corresponding to the block transfer level
The block transfer data sent from the write data register 18 via the data line 113 is written by supplying the write addresses to the data registers 13 to 13 from the address registers 6 to 9.

That is, the address registers 6 to 9 of the data arrays 10 to 13 provided corresponding to the level configuration of the cache memory.
Stores the write address from the address register 15 in correspondence with the level indicated by the block transfer level only when the block transfer data is transferred from the main storage device, and stores it in the address register 1 otherwise. Part of the read request address that is specified, that is, the data array
The read address to 10 to 13 is stored.

Therefore, even when the block transfer to the main memory is activated, the data requested by the subsequent read request is registered in the data arrays 10 to 13 corresponding to the block transfer level stored in the block transfer level register 16. Unless it is done, there is no collision in hardware, and block transfer and read request can be processed simultaneously without conflict.

However, the data arrays 10 to 13 corresponding to the block transfer level stored in the block transfer level register 16 are
If the data requested by the read request is registered in the read request, the subsequent read request is suppressed because the hardware used by them, that is, the hit level address registers 6-9 and the data arrays 10-13, overlap. There is a need to.

Therefore, the control block 4 compares the hit level from the comparison circuit 3 with the block transfer level stored in the block transfer level register 16, and when a match between them is detected, in order to suppress the subsequent read request, the address Control is performed to suppress the transfer of the read request address from the register 1 to the address register 5.

FIG. 2 is a block diagram showing the configuration of the control block 4 of FIG. In the figure, ADAR valid flag (AV) (hereinafter referred to as address valid flag) 40, ADBR valid flag (BV) (hereinafter referred to as address valid flag) 41,
ADCR valid flag (CV) (hereinafter referred to as address valid flag) 42 has a logical value of "1" when the addresses stored in the address registers 1, 5 and 15 are valid,
This flag is a logical value "0" when it is invalid.

When the address valid flag 42 has a logical value of “0” (when block transfer is not started for the main memory), the address valid flag is stored when the read request address is stored in the address register 1 from the read request source. 40
Becomes a logical value "1".

Further, the address array 2 is indexed by the read request address stored in the address register 1, and when one of the hit levels from the comparison circuit 3 becomes a hit state, the output from the OR circuit 49 becomes a logical value "1". Become.

Therefore, at the next timing, the logical value "1" is set to the address valid flag 41 via the AND circuit 53, and the logical value "1" is set to the hit flag (HV) 44 via the AND circuit 51. . As a result, data is read from the data arrays 10 to 13 corresponding to the hit level from the comparison circuit 3.

Further, at the next timing, the logical value “1” is set to the data reply valid flag (DV) (hereinafter referred to as the data valid flag) 43 through the AND circuit 55, and the data transfer instruction to the read request source is output. It By this data transfer instruction, the data array 10 corresponding to the hit level is
The data read from ~ 13 and stored in the read data register 17 is transferred to the read request source. Since the negative output of the hit flag 44 is the logical value "0", the logical value "1" is not set in the address valid flag 42.

When the address valid flag 42 is the logical value "1" (when block transfer is activated to the main memory)
When the read request address is stored in the address register 1 from the read request source, the address valid flag 40 becomes the logical value "1".

Further, the address array 2 is indexed by the read request address stored in the address register 1, and when one of the hit levels from the comparison circuit 3 becomes a hit state, the output from the OR circuit 49 becomes a logical value "1". Become.

At this time, the comparators 45 to 48 compare the hit level from the comparison circuit 3 with the block transfer level stored in the block transfer level register 16, and if any of the comparators 45 to 48 detects a match. The output of the OR circuit 50 becomes the logical value "1", the output of the NAND circuit 52 becomes the logical value "0", and the output of the AND circuit 53 also becomes the logical value "0".

As a result, even if the logical value "1" is set in the address valid flag 40, the logical value "1" is not set in the address valid flag 41, and the state of the address valid flag 40 is set to the logical value by the output of the AND circuit 53. Holds to "1".

That is, the target level for writing the block transfer data by the address stored in the address register 15,
If the hit level of the subsequent read request by the cache memory index is the same, the read request address stored in the address register 1 is not transferred to the address register 5, and the subsequent read request by this read request address is suppressed. Will be done.

On the other hand, if no match is detected by the comparators 45 to 48 and the output of the OR circuit 50 becomes the logical value "0", or the address valid flag 42 is reset due to the end of the block transfer, the address valid flag 42 is reset. Since the logical value "1" is set in the flag 41, the subsequent read request processing by the read request address stored in the address register 1 is performed.

In the read request by the read request address stored in the address register 1, when the comparison circuit 3 does not detect a match, the block transfer from the main storage device is activated. At this time, the address valid flag 41 The logical value “1” is set to the address valid flag 42 via the AND circuit 54 by the output and the negative output of the hit flag 44.

The operation of the embodiment of the present invention will be specifically described with reference to FIGS. 1 and 2.

When the block transfer data from the main memory is written in the level 2 data array 12, level 2 is stored in the block transfer level register 16.

The block transfer data from the main storage device is stored in the write data register 18, and a part of the read request address stored in the address register 15, that is, the write address is transferred to the address register 8 to transfer the block. Data is written to level 2 data array 12. At this time, the logical value “1” is set in the address valid flag 42 of the control block 4.

Independently of the operation of writing the block transfer data to the data array 12, when the address of the subsequent read request is stored in the address register 1, the address array 2 is indexed by this address, and the address register 5 is read at the next timing. Although the address is to be transferred to .about.9, the write address is stored in the level 2 address register 8 because the block transfer is in progress. Therefore, the subsequent read request cannot read data from the level 2 data array 12.

At this time, the comparator 47 of the control block 4 detects a match between the hit level of the subsequent read request and the block transfer level (level 2) stored in the block transfer level register 16, and the state of the address valid flag 40 is logical. Since the value "1" is held and the logical value "0" is set in the address valid flag 41, the read request address of the address register 1 is held and the address transferred to the address register 5 is invalid. Therefore, the subsequent read request is suppressed until the block transfer is completed.

When the block transfer is completed, the address valid flag 42 is reset. Therefore, the logical value "1" is set in the address valid flag 41, and the subsequent read request is executed by the read request address held in the address register 1.

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, an information processing apparatus according to another embodiment of the present invention is a control block instead of the control block 4 of FIG.
The structure is the same as that of the embodiment of the present invention shown in FIG. 1 except that the numeral 19 is added. The same components are designated by the same reference numerals and their operation is also the same.

That is, also in another embodiment of the present invention, when the block transfer is activated to the main memory device, the data requested by the subsequent read request is stored in the block transfer level register 16 at the block transfer level. As long as it is not registered in the data arrays 10 to 13 corresponding to, there is no collision in hardware, and block transfer and read request can be processed simultaneously without conflict.

However, the data arrays 10 to 13 corresponding to the block transfer level stored in the block transfer level register 16 are
If the data required by the subsequent read request is registered in the hardware, the hardware used by them, that is, the hit level address registers 6 to 9 are registered.
And the data arrays 10 to 13 overlap, so the data array
Even if the data read from the data arrays 10 to 13 is stored in the read data register 17 due to the subsequent read request when the timings of using 10 to 13 overlap, this data is erroneous data. Therefore, it is necessary to issue the read request again.

Therefore, in the control block 19, the hit level stored in the hit level register 14 and the block transfer level stored in the block transfer level register 16 are compared, and when a match between them is detected, a subsequent read request is made. In order to suppress the above, the control for suppressing the data transfer instruction to the read request source for the data stored in the read data register 17 and for making the read request again is performed. To make the read request again means to make the access from the address register 1 again.

FIG. 4 is a block diagram showing the configuration of the control block 19 shown in FIG. In the figure, a control block 19 according to another embodiment of the present invention is provided with AND circuits 56, 57, 59 and a gate circuit 58, and the hit flag 44 of FIG. The configuration is the same as the configuration of the control block 4 of the embodiment, the same components are denoted by the same reference numerals, and their operations are also the same.

When the address valid flag 42 has a logical value of “0” (when block transfer is not started for the main memory), the address valid flag is stored when the read request address is stored in the address register 1 from the read request source. 40
Becomes a logical value "1".

In addition, the address array 2 is indexed by the read request address stored in the address register 1, and when one of the hit levels from the comparison circuit 3 becomes a hit state, the output from the OR circuit 49 becomes a logical value "1". Become.

Therefore, at the next timing, the address valid flag 41 is set to the logical value "1" via the AND circuit 53, so that the data is read from the data arrays 10 to 13 corresponding to the hit level from the comparison circuit 3. .

Furthermore, at the next timing, the data valid flag 43
The logical value "1" is set to the AND via the AND circuit 59, and the data transfer instruction to the read request source is output. By this data transfer instruction, the data array corresponding to the hit level
The data read from 10 to 13 and stored in the read data register 17 is transferred to the read request source.

When the address valid flag 42 is the logical value "1" (when block transfer is activated to the main memory)
When the read request address is stored in the address register 1 from the read request source, the address valid flag 40 becomes the logical value "1".

Further, the address array 2 is indexed by the read request address stored in the address register 1, and when one of the hit levels from the comparison circuit 3 becomes a hit state, the output from the OR circuit 49 becomes a logical value "1". Become.

At this time, the comparators 45 to 48 compare the hit level from the hit level register 14 with the block transfer level stored in the block transfer level register 16, and the comparators
When a match is detected in any of 45 to 48, the output of the OR circuit 50 becomes the logical value "1" and the negative output of the AND circuit 56 becomes the logical value "0", and the outputs of the AND circuit 53 and 59. Also has a logical value of "0".

As a result, even if the logical value "1" is set in the address valid flag 40, the logical value "1" is not set in the address valid flag 41, and the logical value "1" is not set in the data valid flag 43 either. . Therefore, a data transfer instruction to the read request source of the data read from the data arrays 10 to 13 by the subsequent read request is not output.

Further, the positive output of the AND circuit 56 becomes the logical value “1”, the output of the AND circuit 53 also becomes the logical value “1”, and the logical value “1” is set again in the address valid flag 40. At the same time, the read request address stored in the address register 5 is transferred to the address register 1, and the read request address is stored again in the address register 1.

That is, the target level for writing the block transfer data by the address stored in the address register 15,
If the subsequent read request has the same hit level as the cache memory index, the data array 10 is read by the read request address stored in the address register 1.
Data transfer of the data read from -13 to the read request source is suppressed, and the read request address of the subsequent read request is reset in the address register 1.

As a result, even if the logical value "1" is set in the address valid flag 40 again, this state is maintained until the address valid flag 42 is reset by the end of the block transfer, and the logical value "0" is set in the address valid flag 42. Is set, the logical value "1" is set in the address valid flag 41, and the subsequent read request is processed by the read request address stored in the address register 1.

In the read request by the read request address stored in the address register 1, when the comparison circuit 3 does not detect a match, the block transfer from the main storage device is activated. At this time, the address valid flag 41 The logical value "1" is set in the address valid flag 42 via the AND circuit 54 by the output and the negative output of the gate circuit 58.

The operation of another embodiment of the present invention will be specifically described with reference to FIGS. 3 and 4.

When the block transfer data from the main memory is written in the level 2 data array 12, level 2 is stored in the block transfer level register 16.

The block transfer data from the main storage device is stored in the ride data register 18, and a part of the read request address stored in the address register 15, that is, the write address is transferred to the address register 8 to transfer the block. Data is written to level 2 data array 12. At this time, the logical value “1” is set in the address valid flag 42 of the control block 19.

Independently of the operation of writing the block transfer data to the data array 12, when the address of the subsequent read request is stored in the address register 1, the address array 2 is indexed by this address, and the address register 5 is read at the next timing. Addresses are transferred to ~ 9.

In this case, if it is the write timing to the data array 12 by block transfer, the level 2 address register 8
The write address from the address register 15 is stored in.

Therefore, even if the subsequent read request tries to read the requested data from the level 2 data array 12, the requested data cannot be read from the data array 12.

Therefore, the comparator 47 of the control block 19 detects a match between the hit level of the subsequent read request and the block transfer level (level 2) stored in the block transfer level register 16, and uses the level 2 data array 12. If the timing is the same, the address valid flag 40
Is set to the logical value "1" again, and the data valid flag 43 is set to the logical value "0". Therefore, the read request address is reset in the address register 1 and the data is read by the subsequent read request. The data transfer of the data read from the array 12 is suppressed, and the subsequent read request is suppressed until the block transfer is completed.

When the block transfer is completed, the address valid flag 42 is reset, so that the logical value “1” is set in the address valid flag 41 and the subsequent read request is executed by the read request address reset in the address register 1.

In this way, the block transfer level stored in the block transfer level register 16 and the hit level from the comparison circuit 3 for the subsequent read request are compared by the control block 4, and when a match is detected, the subsequent read request is performed. Is suppressed by the control block 4, and the address register 1
By holding the read request address of the subsequent read request stored in, the block transfer from the main memory to the cache memory and the subsequent read request for the cache memory can be processed simultaneously without conflict. You can

Therefore, it is possible to realize the simultaneous processing of these processes with a small increase in the amount of hardware such as the addition of the control block 4.

Further, the comparison circuit 3 receives the block transfer level stored in the block transfer level register 16 and the subsequent read request.
Is compared with the hit level output from the hit level register 14 and stored in the hit level register 14 in the control block 19, and when a match is detected, the subsequent read request causes the data arrays 10 to 13 to be read.
By controlling the transfer of the data read from the control block 19 and resetting the read request address of the subsequent read request in the address register 1, the subsequent read request causes the data arrays 10-13.
Even if erroneous data is read from, the data is not transferred, and correct data can be transferred by the read request address of the subsequent read request reset in the address register 1.

Therefore, the block transfer from the main memory to the cache memory and the subsequent read request to the cache memory can be processed simultaneously without conflict, and the addition of the control block 19 and the like increases the small amount of hardware. It is possible to realize simultaneous processing of the above processing.

As described above, according to the present invention, the write level of the write data block-transferred from the main storage device by the first read request set in the storage means and the subsequent first set in the storage means. In a multi-level cache memory capable of simultaneously processing the writing of write data and the reading of read data when the read level of the read data read by the second read request is different from the write level of the first read request. When a match with the read level of the second read request is detected, the transfer of the read data read by the second read request is suppressed, and the second read request is reset in the storage unit, thereby making a mistake. Even if the data is read, the data is not transferred, and the subsequent second data set in the storage means is reset. Correct data can be transferred by a read request. Therefore, it is realized with a small amount of hardware, and there is an effect that the block transfer and the subsequent read request can be simultaneously processed in the cache memory without conflict.

[Brief description of drawings]

1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the control block of FIG. 1,
FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention,
FIG. 4 is a block diagram showing the configuration of the control block shown in FIG. 1,5-9,15 …… Address register 2 …… Address array 3 …… Comparison circuit 4,19 …… Control block 10 ～ 13 …… Data array 14 …… Hit level register 16 …… Block transfer level register 40 ～ 42 …… Address register, valid flag 43 …… Data reply Valid flag 44 …… Hit flag 45 to 48 …… Comparator

Claims (1)

[Claims] 1. A storage unit for storing a read request, a write level of write data block-transferred from a main storage device by a first read request set in the storage unit, and a subsequent set in the storage unit. A plurality of levels of cache memory capable of simultaneously processing the writing of the write data and the reading of the read data when the read level of the read data read by the second read request is different; and the first read request. Detecting means for detecting a match between the write level according to the second read request and the read level according to the second read request, and transfer of the read data read according to the second read request for which a match is detected by the detecting means. Deterring means for deterring, and the second
And a resetting means for resetting the read request of the above in the storing means.