JPH0719247B2 - Command transmission control method in information processing apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A transmission control method of a vector instruction corresponding to each scalar unit in an information processing apparatus including a vector unit for processing a vector instruction sent from a plurality of scalar units, Even if the commands sent from the unit system are mixed in the common command transmission queue buffer, the SU0 commands or the SU1 commands output in the order in which they are input, but the commands of different systems do not. The purpose is to provide a command transmission control method in an information processing device that can output the one that can transmit, and to process multiple scalar units that process scalar instructions and vector instructions sent from these scalar units. It is composed of vector units, and the vector control unit in the vector unit issues instructions for each instruction of each scalar unit. In an information processing device having an instruction transmission queue buffer that is set to be shared between instructions of each scalar unit in the preceding stage of the reception stage, a read pointer queue of the instruction transmission queue for each scalar unit and a read pointer queue control unit are provided. And the read pointer queue control unit, when setting an instruction in the instruction transmission queue buffer,
The pointer of the command transmission queue buffer is set in the read pointer queue, the read pointer queue is shifted when output from the command transmission queue, and the head of the read pointer queue for each scalar unit is for each scalar unit of the command transmission queue. It is configured to control so as to indicate the read position of the instruction.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector command transmission control method corresponding to each scalar unit in an information processing apparatus having a vector unit for processing vector commands sent from a plurality of scalar units.

In a scientific and technological computer equipped with a scalar unit for processing scalar instructions and a vector unit for processing vector instructions, it depends on the program to be executed. There has been a problem that the operating rate of the unit has declined and effective use of resources cannot be achieved.

In order to solve this problem, a new multiprocessor system that connects multiple scalar units to one vector unit and increases the vector unit operation rate by increasing the number of vector instructions sent from multiple scalar units to the vector unit has been developed. Figured out.

In the multiprocessor system, processing is advanced while exclusively switching the right of use of the vector unit to a plurality of scalar units. However, such a switching control has a drawback that it takes time to rise the command transmission at the time of switching the vector unit use right.

Therefore, the applicant has proposed a method for effectively utilizing the instruction execution pipeline by alternately switching the vector unit usage right for each instruction.

However, even in that method, the device of multiple stages (instruction decoding stage, instruction transmission stage, etc.) from when an instruction is input into the vector unit to when the instruction is transmitted, responds to the instruction of the system of multiple scalar units. Therefore, it is desired to have flexibility in controlling the transmission of commands between systems.

[Prior Art] A vector processor (VP) is a vector unit (VU) that processes vector instructions and other instructions (scalar instructions).
And a scalar unit (SU) for processing.

Fig. 6 shows the structure of a conventional multi-system VP with two SUs and one VU.

In the figure, 60 is a main memory (represented by MSU), 61 is a storage controller (represented by MCU), 62 is a scalar unit 0 (represented by SU0), 63 is a scalar unit 1 (represented by SU1), and 64 is a vector. Unit (represented by VU), 65 is a vector execution unit (represented by VEU), 66 is a vector control unit (represented by VCU), 650 is a load pipeline, 651 is a store pipeline, and 652 is a vector register (represented by VR). , 653 represents an addition pipeline, 654 represents a multiplication pipeline, 655 represents a division pipeline, and 660 represents a control signal.

The VCU 66 is a unit for controlling vector instructions. When receiving vector instructions sent from a plurality of scalar units SU0 and SU1, the VCU 66 is controlled to be switched in instruction units and sent to the VEU 65 through the signal line 660.

VEU65 is a unit that executes vector instructions, load pipeline 650 that transfers data to and from memory,
It has a store pipeline 651 and a VR 652 that holds vector data.

Further, it has an addition pipeline 653, a multiplication pipeline 654, and a division pipeline 655 in order to execute an instruction for reading vector data from the VR 652, performing an operation, and writing the result to the VR 652.

In VP, SU is used for the instructions from MSU.
Each SU0 and SU1 executes in the SU when the scalar instruction is fetched, and passes it to the VU when the vector instruction is fetched.

Next, FIG. 7 shows a circuit configuration proposed for the VCU in the configuration shown in FIG.

In FIG. 7, vector instructions are input from SU0 and SU1 to respective instruction fetch stage registers (represented by VFSR0 and VFSR1) via respective buses.

The operation on the SU0 side will be described below. When an instruction is fetched into VFSR0, the vector etch buffer register (represented by VFBRO) is empty, and the instruction switching control unit 721 causes the selector 744 to select the SU0 side. The command is VFSR
0730 to vector predecode stage register (VPSR
It is sent to 750.

If the preceding command is included in VFBR0,740 or if the selector 744 selects the SU1 side, VFSR0,730 to V
Moved to FBR0,740 and buffered.

The first instruction in the VFBR0 which is a first-in first-out (FIFO) type buffer moves to the VPSR750 when the selector 744 selects SU0. The above operation on the SU0 side is SU
The instruction from 1 is similarly performed on the SU1 side.

The instruction switching control unit 721 determines which of the vector instruction sent from SU0 (hereinafter referred to as the 0-system vector instruction) and the vector instruction sent from SU1 (hereinafter referred to as the 1-system vector instruction) at the pre-execution queue ( Control to select whether to move to the queue) (normally switching is performed alternately, but control according to the situation is also possible).

The vector instruction of each system selected by the instruction switching control unit 721 is decoded and an exception check is performed in the VPSR750.

Stores the decoded result vector instruction to memory,
If it is an access-related instruction such as a load, it moves to the access queue stage, four SU0 (represented by AQS0) 771 or access queue stage four SU1 (represented by AQS1) 772. However, if the instruction is 0 series, AQSO, 771 is empty, and
AQ when access queue buffer (denoted by AQB) 761 is empty
You can move to S0,771. Even in the case of the 1-system instruction, when AQS1 is empty and the access queue buffer AQB761 is empty, it is possible to move to AQS1,772.

Here, AQS0,771 and AQS1,772 are registers dedicated to SU0 and SU1, respectively, and are command transmission registers dedicated to 0-system access-related instructions and 1-system access-related instructions, and the instruction management control unit.
Under the control of 781, transmission (putting into a pipeline for access processing such as loading and storing) is performed.

The condition for moving from VPSR750 to AQB761 which is the instruction transmission queue is that AQS of the system (SU0 or SU1) to which the instruction belongs is not empty or there is a predecessor instruction of the same system in AQB761. If this condition is satisfied, 0 The vector instructions for both the access system and the access system 1 are stored in the AQB761 in a first-in first-out (FIFO) format (for example, a shift register).

In addition, in the case of arithmetic instructions such as addition, multiplication, and division, VP
The instruction sent from SR750 is the same circuit as the access system, execution queue stage for SU0 (represented by EQS0) 773, or execution queue stage for S.
Input to U1 (represented by EQS1) 774 or execution queue buffer (represented by EQB) 762.

The instruction of each stage of AQS0, AQS1, EQS0, and EQS1 is the instruction management control unit 781 for the access system and the instruction management control unit 782 for the operation system.
When the transmission timings are controlled by each of them and the conditions are met, VEU (No. 6) is passed through signal line 79 (corresponding to signal line 660 in FIG. 6).
Figure) sent to.

[Problems to be Solved by the Invention] In the configuration of the conventional example of FIG. 7 described above, an instruction predecode stage (VPSR) from when an instruction is input into the VCU after the right to use the VU is obtained until the instruction is issued. ), And the instruction transmission stage (AQB, EQB), the circuit is shared by SU0 and SU1 systems. This is because the number of circuits increases when a circuit is provided for each system,
This is a common device considering that the device becomes large.

However, when issuing a command, there are times when the command of one system cannot be sent for some reason. In such a case, for example, there is a problem in that the transmission of another SU-based command that follows succeeds even if the computing unit is empty.

Specifically, in the case of the operation system, when the operation instructions of both the SU0 system and the SU1 system are alternately stored in the EQB762, which is a FIFO type buffer, as shown in FIG. It is assumed that the 1-system instructions are in the order of n + 1, m + 1, n + 2, m + 2.

At this time, instructions m and n are stored in EQS0 and EQS1, respectively, and the instruction management control unit 782 tries to send the 0-system instruction m, but it is not ready (the operation data is not loaded in the vector register). Etc.), the calculation cannot be executed.

At this time, the command n of the other 1 system is transmitted, but its EQ
Even if S1 becomes empty, the head (FIFO
Since the SU0 series command n + 1 is included in (OUT side of), the next SU1 series command m + 1 that follows cannot be moved to the transmission stage, and the SU1 system command is executed overtaking the SU0 system command. The problem is that you cannot do it.

According to the present invention, even if commands sent from a plurality of scalar unit systems are mixed in a common name transmission queue buffer, the SU0 system commands or the SU1 system commands output in the order in which they are input, but they are different. It is an object of the present invention to provide a command transmission control system in an information processing device that can output the one that can transmit between the commands of the system first.

[Means for Solving Problems] The principle mechanism of the present invention is shown in FIG.

FIG. 1 shows the basic structure related to the command transmission queue according to the present invention in the structure of the VCU, and FIG. 1 shows only the structure related to the EQB of the operation system in the command transmission queue.
The configuration related to the AQB of other access systems is also similar, and is not shown. The structure other than the part related to the command transmission queue in the VCU is the same as that of the conventional example shown in FIG.
In FIG. 1, 10 is a VPSR, 11 is an EQB (arithmetic instruction dispatch queue buffer), 12 is an EQB controller, 13 is a write controller, 14 is a read controller, 141 is a SU0 EQB read pointer queue control. , 142 is a SU0 system EQB read pointer queue, 143 is a SU1 system EQB read pointer queue control unit, 144 is a SU1 system EQB read pointer queue, 145
Is a selector, and 15 and 16 are EQS0 and EQS1 of 0 system and 1 system.

INDUSTRIAL APPLICABILITY The present invention is a command transmission queue buffer (11) that stores both 0 and 1 system instructions sent from the preceding stage (VPSR) of the command transmission queue buffer in a random access type command transmission queue buffer (11). The read pointer queue is stored in each system image, and the read pointer queue is shifted in a first-in first-out manner so that any of the read pointer queues outputs the pointer of the command transmission queue that can be transmitted next from the head position. The commands are output in order within the system, and the command transmission queue buffer at which the head can be transmitted can be arbitrarily taken out between the systems.

[Operation] To explain the operation of FIG. 1, after the decoding and exception check are performed in the VPSR10, the vector instruction of the arithmetic system is EQB1 which is the instruction transmission queue of the arithmetic system according to the decoding result.
Written to 1 (Direct command transmission stage EQS0,15 or
(Except when the conditions to move to EQS1,16 are satisfied).

At the time of writing, the writing control unit 13 of the EQB control unit 12 indicates the writing position of the BQB 11. At the same time as this writing, in the read control unit 14, depending on whether the instruction is the 0-system or the 1-system, the EQB read pointer queue 142 (or 14)
Store in 4). In this case, the EQB read pointer queue control unit 141 (143), when the queue newly written in the EQB is the instruction of its own system, is the number of the instruction of its own system stored in the EQB. Is counted and input to the corresponding register position of the shift register type EQB read pointer queue 142 (144) to be held.

Each of these EQB read pointer queues 142 and 144 receives an instruction of its own system from EQS0,15 or EQS1,16 (puts it into the pipeline for execution) and sends an instruction from the instruction management control unit (not shown). 2 by selector 145 by command
The contents of the head position of one of the EQB read pointer queues 142 and 144 (a pointer indicating the storage position of the head instruction of each system stored in the EQB11) is output, and the instruction is fetched from the EQB11 using the pointer as an address. .

When the instruction is fetched from EQB11 and set in the next stage EQS0 or EQS1, the EQB read pointer queue control unit 141,
In 143, one of the EQB read pointer queues 142 and 144 corresponding to the extracted system shifts by one to bring the pointer of the next oldest queue to the head position.

As a result, for example, the SU0 type vector instructions (arithmetic type) are input to the EQB11 of FIG. 1 in the order of, and the SU1 type vector instructions are input in the order of
When the 0-series command is not transmitted from AQS0 while it is stored alternately, the next command of the 1st system, SU1, skips SU0 and moves to AQS1 at the next timing (the timing after AQS1 starts transmission). You can

[Embodiment] FIG. 2 shows the configuration of an embodiment of the present invention. In this figure, 19 is a VPSR (vector predecode stage register), 20 is an access-related instruction transmission queue buffer AQB, 2
1 is the AQB control unit, 22 is the instruction dispatch queue buffer EQ of the arithmetic system
B and 23 are EQB control units, and 24 and 25 are access systems of 0 system and 1 system.
AQS0, AQS1, 26, 27 are the operation system EQS0, EQS of system 0 and 1
Reference numerals 1, 28, and 29 represent instruction management control of access system and operation system.

The configuration of the embodiment shown in FIG. 2 is the same as that of the conventional example shown in FIG. 7 except for the AQB20, EQB22 and the configuration related thereto.
The vector instructions sent from SU0 and SU1 are received by VFSR0 and VFSR1 and reach VPSR19 in the same manner as in the conventional example. Predecoding and exception checking are performed in VPSR19, and the access-related and arithmetic-related instructions are separated according to the decoding result and input and written to the instruction transmission queue buffers AQB20 and EQB22 (however, the corresponding 0-system in the next stage is written. Or if the AQS and EQS of the 1st system are empty and the buffers AQB and EQB are empty, move directly to the next stage).

The AQB control unit 21 and the EQB control unit 23, which control the AQB20 and EQB22, are provided with 0-system and 1-system AQB read pointer queues and EQB read pointer queues, respectively, and the head of each is always AQB2.
0 and the pointer of the command transmission queue to be read next to the 0 system and 1 system in the EQB22 are output.

FIG. 3 shows the configuration of the read control unit in the EQB control unit 23 that controls the instruction transmission queue buffer EQB22 of the arithmetic system (see the read control unit 14 in the EQB control unit 12 in FIG. 1). Actually, the read control unit is provided with two systems, SU0 system and SU1 system, and FIG. 3 shows the configuration of one system (0 system for explanation).

In the figure, 30 is an EQB read pointer queue (RPQ) input pointer generator (hereinafter referred to as an input pointer generator), 31
Is the EQB read pointer queue (RPQ) write enable generator (hereafter called the write enable generator), 32 is
Encoder to encode EQB write pointer input, 33
~ 36 is a register that holds the EQB read pointer,
Each register stage is connected in a shift register format for shifting to the next stage, and 37 represents a read pointer decoder.

The operation of the configuration shown in FIG. 3 will be described. When a 0-system operation instruction is set in the EQB22 (see FIG. 2) from the VPSR19 (see FIG. 2), the pointer indicating the storage position of the EQB22 is moved to the encoder 3
It is given to the second input and encoded.

On the other hand, the input pointer generator 30 counts how many 0-system read pointers are stored from the head (36) of the read pointer queue (33 to 36), and the EQB pointer output from the encoder 32 is counted. A pointer to be stored (a pointer in the read pointer queue) is designated by driving any of IN0 to IN3 by a logical operation using the count information, and is set in the corresponding queue (one of 33 to 36).

That is, the storage positions of the 0-system operation instructions are sequentially set in the read pointer queue in the order in which they are stored in the EQB.

Next, each read pointer set in the read pointer queue moves from the first queue 36 to the next EQS0, 26 (when the current EQS0 instruction starts and EQB22
(When the first instruction is set), the contents of the first queue 36 of the read pointer queue of FIG. 3 are decoded by the decoder 37 to generate the EQB read pointer output. When the EQB22 is read using this pointer, the corresponding instruction is read and set in EQS0.

When this read pointer queue is read, at the same time, an operation for shifting the subsequent read pointer queue is performed by the signals WE0 to W from the write enable signal generator 31.
It is performed by controlling the generation of E3. Further, the write enable signal generator 31 supplies a signal (one of WE0 to WE3) to the input gate of the corresponding queue even when a new 0-system operation instruction is stored in the EQB 22, and thus the EQB pointer Control writing.

Next, FIG. 4 shows a logical configuration for generating control signals of the input pointer generator 30 and the write enable signal generator 31 in the configuration of FIG.

First, the principle of the signal generation logic configuration of the input pointer generator (however, EQB SU0 system) will be described.

The IN0 signal is a pointer signal for setting the EQB input pointer to the queue 36 (see FIG. 3), and the condition for its generation is that an SU0 instruction (0 system operation instruction) is entered and the EQB22 is currently in the EQB22. When no operation instruction of 0 system is set (NUM represents the number (number) of pointer queues set in this read pointer queue, and NUM0 represents 0).

EQB2 when one read pointer queue is stored
When the 0-system at the head of 2 moves the operation instruction to EQS0 in the next stage to send the instruction.

When either of these logics is established, the pointer signal IN
0 is generated. In the following, signals are also generated for IN1 to IN3 by the logical configuration shown in the figure. The line above the symbol represents negation.

The logic configuration of signal generation of the write enable signal generator is also as shown in FIG. Among them, each signal WE0 to WE3
The first term in the equation of occurs when the instruction shifts from EQB to EQS0 for transmission, and the next term occurs when a new instruction is stored in EQB.

Negation of SU1.INST in the expression indicates that it is not an instruction (instruction) of the scalar unit 1.

EQB and read pointer queue described above (represented by RPQ)
FIG. 5 is a diagram for explaining the relationship of the above.

In Figure 5, EQB50 has a pointer (or identification number)
There are four storage positions 0 to 3, and as shown in the figure, the nth and n + 1th instructions of the 0th system and the mth and m + 1th instructions of the 1st system are alternately stored in order. At this time, E of SU0 series
In QB.RPQ51 and EQ1.RPQ52 of SU1 series, EQB pointers (numerical values in "") are stored in order of the EQB storage positions from the beginning position.
Is set to the read pointer position indicated by the solid and dotted arrows.

[Effects of the Invention] According to the present invention, it is possible to share a command transmission queue among a plurality of scalar unit systems and achieve economy, while overtaking among commands of a plurality of scalar unit systems, thus efficiently transmitting commands. Therefore, it is possible to effectively use the calculator.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention, FIG. 2 is a diagram showing a configuration of an embodiment of the present invention, FIG. 3 is a diagram showing configurations of a read pointer queue and a control unit, and FIG. 4 is a control. FIG. 5 is a diagram showing the logical configuration of the signal generator, FIG. 5 is a diagram for explaining the relationship between the EQB and the read pointer queue, FIG. 6 is a diagram showing the configuration of a conventional multi-system VU, and FIG. 7 is a conventional multi-system. 5 is a diagram showing the configuration of a VCU of FIG. In Fig. 1, 10: VPSR 11: EQB (arithmetic system instruction send queue buffer) 12: EQB control unit, 13: Write control unit 14: Read control unit 141: SU0 system EQB read pointer queue control unit 142: SU0 system EQB read pointer queue 143: SU1 system EQB read pointer queue controller 144: SU1 system EQB read pointer queue 145: Selector 15: 0 system EQS0 16: 1 system EQS1

Claims (1)

[Claims] 1. A vector control unit (VCU) in a vector unit, comprising a plurality of scalar units (SU0, SU1) for processing scalar instructions and a vector unit (VU) for processing vector instructions sent from these scalar units. ) To the instruction output stage (EQS0, EQS1) for each instruction of each scalar unit
In an information processing device equipped with an instruction transmission queue buffer (EQB) that is shared and set between the instructions of each scalar unit in the preceding stage, a read pointer queue (142, 144) and a read pointer of the instruction transmission queue for each scalar unit A queue control unit (141, 143) is provided, and when the read pointer queue control unit (141, 143) sets an instruction in the instruction transmission queue buffer (EQB),
The pointer of the command transmission queue buffer is set to the read pointer queue, the read pointer queue (142, 144) is shifted when output from the command transmission queue, and the head of the read pointer queue for each scalar unit is A command transmission control method in an information processing device, characterized by controlling so as to indicate a command reading position for each scalar unit.