JPH0769895B2 - Command transmission control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In an information processing apparatus having a vector unit for processing vector instructions sent from a plurality of scalar units, transmission control of vector instructions for access systems and arithmetic systems corresponding to each scalar unit Regarding the method, if the instructions sent from multiple scalar units exist in a common instruction dispatch queue buffer that is provided separately for the access system and the operation system, it is possible to dispatch between the commands of different scalar unit systems. For the purpose of providing a command transmission control method in an information processing device that can be executed first, a plurality of scalar units that process scalar commands, a vector execution unit that processes vector commands sent from these scalar units, and a vector It is composed of a vector unit composed of a control unit and each of the vector control units. An information processing apparatus having one instruction predecode stage for sequentially setting instructions sent from the scalar unit and two instruction dispatch queue buffers for separately setting the vector instructions from the instruction predecode stage into an access system and an operation system, respectively. In, the instructions from the two instruction transmission queue buffers of the access system and the operation system are set separately for the access system and the operation system, respectively, and for the scalar unit which is the source of the instruction. A plurality of instruction transmission queue stages, and an instruction transmission selection unit for selecting one instruction from the plurality of instruction transmission queue stages. The instruction transmission selection unit outputs the timing signal assigned to each instruction transmission stage. Equipped with a cycle counter that generates instructions and checks the instruction transmission conditions at each instruction transmission queue stage When a valid instruction to be assigned is assigned, a signal for selecting the instruction transmission waiting stage is generated at the assigned timing, and the instruction transmission condition is set to the other instruction transmission waiting stage at the timing determined for the other instruction transmission waiting stage. When there is no command to be chucked, it is configured to generate a signal for selecting a command transmission waiting stage having a command to check the command transmission condition.

[Industrial application] The present invention is an information processing apparatus equipped with a vector unit for processing vector instructions sent from a plurality of scalar units, and controls the transmission of vector instructions for access and arithmetic systems corresponding to each scalar unit. Regarding the scheme.

In a scientific and technological computer equipped with a scalar unit that processes scalar instructions and a vector unit that processes vector instructions, it depends on the program to be executed. There has been a problem that the utilization rate of the vector unit has decreased, and effective use of resources cannot be achieved.

In order to solve this problem, a new multiprocessor system that connects multiple scalar units to one vector unit and increases the vector unit operation rate by increasing the number of vector instructions sent from multiple scalar units to the vector unit has been developed. Figured out.

In the multiprocessor system, processing is advanced while exclusively switching the right of use of the vector unit to the scalar unit of negative number cormorant. However, such a switching control has a drawback that it takes time to rise the command transmission at the time of switching the vector unit use right.

However, after the instruction is input in the vector unit,
The devices of multiple stages (instruction decoding stage, instruction transmission stage, etc.) until the instruction is issued are shared for the instructions of the system of multiple scalar units. Therefore, it is necessary to have flexibility in controlling the transmission of instructions, and in particular, it is desirable to perform flexible control in the instruction transmission queue stage so that there is no vacancy in the multiple instruction execution pipelines in the next stage. ing.

[Prior Art] A vector processor (VP) is a vector unit (VU) that processes vector instructions and other instructions (scalar instructions).
And a scalar unit (SU) for processing.

Figure 5 shows the configuration of a conventional multi-system VU with two SUs and one VU.

In the figure, 60 is a main storage unit (represented by MSU), 61 is a storage control unit (MCU), and 62 is a scalar unit 0 (SU0).
, 63 is a scalar unit 1 (represented by SU1), 64 is a vector unit (represented by VU), 65 is a vector execution unit (represented by VEU), 66 is a vector control unit (represented by VCU), and 650 is a load. A pipeline, 651 is a store pipeline, 652 is a vector register (represented by VR), 653 is an addition pipeline, 654 is a multiplication pipeline, 655 is a division pipeline, and 660 is a control signal.

The VCU 66 is a unit for controlling vector instructions, and when receiving vector instructions sent from a plurality of scalar units SU0 and SU1, switching control is performed in instruction units and the signals are sent to the VEU 65 through the signal line 660.

VEU65 is a unit that executes vector instructions, load pipeline 650 that transfers data to and from memory,
It has a store pipeline 651 and a VR 652 that holds vector data.

Further, it has an addition pipeline 653, a multiplication pipeline 654, and a division pipeline 655 in order to execute an instruction for reading vector data from the VR 652, performing an operation, and writing the result to the VR 652.

In VP, SU is used for the instructions from MSU.
Each SU0 and SU1 executes in the SU when the scalar instruction is fetched, and passes it to the VU when the vector instruction is fetched.

Next, FIG. 6 shows the circuit configuration of the multi-system VCU 66 shown in FIG.

In FIG. 6, vector instructions are input from SU0 and SU1 to the respective vector instruction fuse stage registers 730 and 731 (represented by VFSR0 and VFSR1) via respective paths.

The operation on the SU0 side will be described below. When an instruction is fetched into the VFSR0,730, the vector etch buffer register 740 (represented by VFBRO) is empty, and the instruction switching control unit 721 causes the selector 744 to shift the SU0 side. If selected, the instruction is sent from the VFSR0,730 to the vector predecode stage register 750 (denoted by VPSR).

If the preceding command is included in VFBR0,740 or if the selector 744 selects the SU1 side, VFSR0,730 to V
Moved to FBR0,740 and buffered.

The first instruction in the VFBR0,740 which is a first-in first-out (FIFO) type buffer moves to the VPSR750 when the selector 744 selects SU0. The above operation on the SU0 side is similarly performed on the SU1 side with respect to the instruction from the SU1.

The instruction switching control unit 721 determines which of the vector instruction sent from SU0 (hereinafter referred to as the 0-system vector instruction) and the vector instruction sent from SU1 (hereinafter referred to as the 1-system vector instruction) at the pre-execution queue ( Queue) control to select whether to move (usually switching alternately, but it is possible to limit depending on the situation).

The vector instruction of each system selected by the instruction switching control unit 721 is decoded and an exception check is performed in the VPSR750.

Stores the decoded result vector instruction to memory,
If it is an access-related instruction such as load, it moves to the access queue stage (represented by AQS) 771. However, when the AQS771 is empty and the access queue buffer (represented by AQB) 761 is empty, it is possible to move to the AQS771.

Here, the AQ771 is an instruction transmission register that is shared by both 0-system access instructions and 1-system access instructions.
Transmission (putting into a pipeline for access processing such as loading and storing) is performed under the control of the instruction management control unit 781.

The condition to move from VPSR750 to AQB761 which is the command transmission queue is that AQS771 is not empty or there is a predecessor command in AQB761. Stored in AQB761 in first in first out (FIFO) format (eg shift register).

In addition, in the case of arithmetic instructions such as addition, multiplication, and division, VP
The instruction sent from SR750 is the Execution Queue Stage (represented by EQS) 772 which is a circuit similar to the access system,
Input to the execution queue buffer (represented by EQB) 762.

As for the instruction of each stage of AQS771 and EQS772, the access system is the instruction management control unit 781, and the operation system is the instruction management control unit 782. When the transmission timing is controlled and the conditions are met, the signal line 79 (the signal line 660 in FIG. 5) is used. It is sent to VEU65 (Fig. 5).

[Problems to be Solved by the Invention] In the configuration of the conventional example shown in FIG. 6 described above, an instruction predecode stage (VPSR) from when an instruction is input into the VCU after the right to use the VU is obtained until the instruction is issued. ), And the command transmission stage (AQB, EQB, AQS, EQS), the circuit is shared by SU0 and SU1 systems. This is common in view of the fact that the number of circuits increases when each system is provided, and the size of the device increases.

However, when issuing a command, there are times when the command of one system cannot be sent for some reason. In such a case, there is a problem that, for example, the transmission of subsequent SU-related commands can be interrupted even though the arithmetic unit is the partner.

Specifically, taking the case of an access system as an example,
As shown in the enlarged view at the end of the dotted line with an arrow in the figure, AQB7
The 0-system (SU0) instructions "LOAD1" and "LOAD2" are set to 61 in sequence, and then the 1-system (SU1) instruction "STORE1"
And "STORE2" are set in order.

The first instruction LOAD1 is set in the AQS771 and is transmitted (started) when the previous instruction is transmitted (which is input to the execution pipeline in the vector execution unit VEU to start execution). Due to the transmission, the next command LOAD2 is AQB76.
Move to the beginning of 1 and set to AQS771. However, since the previous instruction LOAD1 uses the load pipeline (see 650 in FIG. 5), the next same pipeline cannot be used to issue the instruction LOAD2 immediately.

In such a case, the following 1st series instruction STORE1 in AQB761
Cannot send even if the store pipeline in the vector execution unit is empty and ready for immediate use.

That is, the 1-system STORE 1 instruction is the preceding 0-system instruction LO.
The problem is that wasteful processing time is required because the pipeline cannot be used effectively because AD2 has to wait until the call is sent.

According to the present invention, when an instruction sent from a plurality of scalar units exists in an instruction transmission queue buffer provided separately for an access system and an arithmetic system, it is possible to transmit between instructions of different scalar unit systems in an instruction transmission queue stage. It is an object of the present invention to provide a command transmission control system in an information processing device that can be executed first.

[Means for Solving Problems] FIG. 1 shows a basic configuration of the present invention.

FIG. 1 shows the basic structure related to the instruction transmission queue stage according to the present invention in the structure of the VCU.
(Vector pre-decode stage register), AQB, EQB
The configuration before VPSR (not shown) is the same as the conventional one shown in FIG.

In FIG. 1, 10 is VPSR, 11 is AQB (access queue buffer), 12 is EQB (execution queue buffer), 13 is access queue stage for SU0 (AQS0
, 14 is the access queue stage for SU1 (A
QS1), 15 is an execution queue stage for SU0 (represented by EQS0), 16 is an execution queue stage for SU1 (represented by EQS1), 17 is an instruction transmission selection section, and 18 is one selected instruction. Hold and check the transmission condition, start when the condition is satisfied, and corresponding AQS0
~ Represents a select queue stage (represented by SQS) with the ability to release EQS1.

According to the present invention, even if instructions of different scalar unit systems exist in the instruction transmission queue buffers (11, 12), the next instruction transmission queue stage (13-16) is individually associated with each unit system (0, 1). In addition, one instruction is selected and controlled from a plurality of instruction transmission queue stages and set to the next selection queue stage.

[Operation] To explain the operation of FIG. 1, after the decoding and exception check are performed in the VPSR10, the vector instructions of the memory access system (store, load) are sent to the AQB11 according to the decoding result as in the conventional configuration. The vector instructions of the operation system (addition, multiplication, division) that are stored are stored in the EQB12.

However, as for access system, AQB11 is free,
Moreover, when the AQS0,13 or AQS1,14 corresponding to the system (0 system or 1 system) to which the instruction belongs is free, the switch 110
Is set to the corresponding AQS0, 13 or AQS1, 14 directly, and similarly for the operation system, it is also set to EQS0, 15 or EQS1, 16 by the switch 120.

The multiple instructions of AQB11 and EQB12 are output in a first-in first-out (FIFO) manner. In that case, after the next selected AQS0,13 to EQS1,16 is set, when the selected instruction in the selection queue stage starts (transmits) to the execution pipeline, the started instruction is set in AQS0,13, for example. When the instruction is released, the next instruction can be set in AQS0, 13 after the instruction is released (released).

Thus, each outgoing queue stage AQS from AQB11, EQB12
When instructions are stored in 0, 13 to EQS 1, 16 (actually, the contents are transmitted one after another and the contents are exchanged), any one of them is selected and set in SQS 18.

Selection is made by the selection signal SA0, SA output from the command transmission selection unit 17.
This is performed by supplying 1, SE0 and SE1 to the AND circuits 131 to 161. In that case, the selection signals SA0 to SE1 are generated by performing a logical process on each input signal in the selection signal generation unit 172 in the command transmission selection unit 17.

Although each timing signal (time) generated from the cycle counter 171 that is one of the input signals is associated with each instruction transmission queue stage, each instruction transmission queue stage
The status of the command from 13 to 16 is determined by the signal lines 130 and 140 to 160 (indicated by, in the figure), and the signal line 1 from the SQS18
It is configured to detect the command transmission status by 81, and not only generate a selection signal for the assigned timing signal (time) if conditions are met, but also generate a selection signal for a timing signal (time) not assigned. Has been done.

In SQS18, when an instruction is set, it checks whether the set instruction can be transmitted according to the status of the instruction execution unit (pipeline) in the next stage, and if the transmission condition is satisfied, it starts and responds accordingly. Release (release) the contents of the command transmission queue buffer in which the command is set, and the next command (AQ
B11 or EQB12) can be set.

[Embodiment] FIG. 2 shows the construction of an embodiment of the present invention.

FIG. 2A shows the structure of the command transmission selection unit, which is the main part of the basic structure of the present invention shown in FIG.

In (a) of FIG. 2, 20 is an instruction transmission selection unit, 21 is a cycle counter, 22 is a selection signal generation unit, and 23 to 26 are SU0 and SU1 access system instructions similar to AQS0 to EQS1 in FIG. SU0
And SU1 represent the respective instruction transmission queue stages of the operation system instructions, and 27 represents the same selection queue stage as SQS shown in FIG.

As shown in (a), the command transmission selection section 20 is provided with a cycle counter 21, which is driven by a clock signal (indicated by CLK) to repeatedly generate signals of eight time slots T0 to T7.

The selection signal generation unit 22 in the instruction transmission selection unit 20 receives each time slot signal from the cycle counter 21 and, as shown in the figure, four transmission queue stages AQS0,2.
3 to EQS1,26 receives a signal indicating whether each instruction is valid or invalid, and further, from SQS27, an instruction of any one of the four outgoing queue stages 23 to 26 is transmitted. A signal that indicates whether or not START / AQS0 to START
・ EQS1 signal (any one is output when command is issued)
And its inverted (negative) signal (three outputs that do not occur when a command is issued) are input.

The logical configuration of the selection signal generation in the selection signal generation section 22 is shown in FIG.

First, the selection signal SA0 of AQS0,23 (hereinafter simply referred to as AQS0) of the 0 system of the access system (this name is Set SQS from AQS0
It means).

Here, the instruction is the instruction transmission queue stage (for example, AQS0)
The operation after it is set to AQS0 is briefly explained. After the instruction is set to AQS0, the instruction is set to SQS27 (hereinafter simply referred to as SQS) at a predetermined timing. When the instruction is started from the time slot SQS assigned to AQS0 (injected into the execution pipeline), the instruction held by AQS0 is released (released) by the start signal. The above ST depends on which instruction transmission queue stage (AQS0 to EQS1) the instruction was from.
One of AT_AQS0, START_AQS1 ... Is turned on.

In the example of (b) in FIG. 2, the start of the instruction set in AQS0 is assigned to be performed in time slots T1 and T5,
Then, it is necessary to set the instruction from AQS0 to SQS before that, and if this is done 2τ (1τ is a time slot interval) before, the setting timing will be time slots T7 and T3.

The other AQS1 of the access system is time slots T1 and T5.
It is set to SQS at and is assigned to start at time slots T3 and T7.

Therefore, the logical configuration of SA0 shown in FIG. 2B will be described.

According to this logical expression, it is shown that a selection signal for setting an instruction from AQS0 to SQS is generated when the following three conditions are met.

The same applies to the setting from AQS1, EQS0, EQS1 to SQS.

It is the timing to set the access type instruction to SQS, that is, one of T1, T3, T5, and T7. The inverted (negative) signal of this timing signal is SLIECT_A.
This signal is called the QS signal, and this signal indicates the timing when the instruction set in SQS is an access-related instruction from AQS. To do this, when the SELECT_AQS signal is off,
Must be set to SQS.

Since an instruction from AQS and an instruction from EQS are alternately set in SQS, this signal indicates the timing for determining which of AQS and EQS should select the instruction to be set in SQS.

It is the timing to set the 0 system (SU0 system) to SQS. (However, if there is no valid instruction in 1-system AQS1 even when 1-system is set, 0-system instruction can be set.

AQS0 is valid (AQSO_VALID), and AQS0 is not needed at the next timing (START_AQS0 is off).

In this case, "unnecessary" means that it is not necessary to select an instruction from the same AQSO and set it in SQS because the instruction of the AQS0 concerned is transmitted when the start signal is turned on.

FIG. 3 shows a time chart of an example of the setting operation to this SQS.

In the operation example (a) of FIG. 3, when AQS0 is valid (VALID) when SELECT_AQS is off and AQS0 does not transmit (start) (small circles in the figure indicate that START_AQS0 does not occur). The condition is satisfied, the selection signal SA0 is generated, and the instruction of AQS0 is set in SQS.

Then, when the next SELECT_AQS signal is off, the SQS instruction (the instruction that was set from AQS0 before that) is sent to the execution pipeline (start) to generate START_AQS0, which is held in AQS0. It is shown that the ordered instruction is released.

Next, in the operation example (b) of FIG. 3, a valid instruction is set in AQS0, and the selection signal SA0 is generated at the timing of being set in SQS, and the instruction is set in SQS. It shows the operation when the command does not transmit from SQS even when the timing of is reached (START_AQS0 does not occur when the transmission conditions are not satisfied).

In this case, the second select signal SA0 generated when the next SELECT_AQS is off sets it to SQS again, and this time it is transmitted at the next transmission timing, which releases the AQS0 holding that instruction. To be done.

Next, FIG. 4 shows a time chart of the selection operation corresponding to the time slots of the 0-system and 1-system for each of the access system and the arithmetic system.

The operation of the access system is shown in the upper half of FIG. 4, and in this case, AQS0 (0 system) and AQS1 in the first time slots T0 to T5.
When a valid instruction is set in both (1st system), the 1st system instruction is set in SQS at time slot T1, the 0th system instruction is set in SQS at the time slot T3 (START) Then, the 1-system AQS1 is released.
Then, in the next time slot T5, a 0-system instruction is transmitted from SQS to release AQS0.

The subsequent time slot T7 is originally the timing when the 0-system AQS0 instruction is selected, but at this time, no valid instruction is set in AQS0 (indicated by a small circle), whereas 1 Since a valid instruction is set in AQS1 of the system, the instruction of the 1st system is set in SQS. Then, the instruction is transmitted to the next time slot T0, and the instruction of AQS1 is released. At this time, the selection signal SA1 generated when AQS1 is set to SQS is represented by the logical expression of FIG. 2 (AQSO_VA
LID negative signal term).

Then, the time slot T1 is originally the timing when the instruction of the 1-system AQS1 is selected. At this time, the START of the AQS1 is started.
Occurs, and it is not necessary to set the same instruction in SQS, so the valid instruction set in AQS0 of the other system is set in SQS. The selection signal SA0 generated at this time is also shown by the logical expression in FIG. 2 (the term of START_AQS1).

Next, the case of the operation system shown in the lower half of FIG. 4 will be explained. As shown in the figure, the time slots T2 and T6 are assigned to the transmission (start) of the operation system 0 system and 1 system, respectively. Therefore, the timing at which each instruction is set in SQS is the time slots T0 and T4 two τ before.

In the figure, time slots T0 to T6 are 0-system EQS0.
As for the instruction of EQS1 of the 1st system, the instruction is set to SQS in the time slots T0 and T5 assigned to the respective system, and the respective instructions are transmitted to T2 and T6.

However, in the subsequent time slot T0 (the time slot in which the operation instruction of the 0 system is set), the effective instruction is not set in the 0 system (EQSO) but the effective instruction is set in the 1 system (EQS1). Therefore, the system 1 command is set in SQS, and transmission is performed in the next time slot. At this time, the selection signal SE1 is generated by the logical configuration shown in FIG. 2 similarly to the above SA0 and SA1.

EFFECTS OF THE INVENTION Conventionally, when a command of one system is waiting for transmission, a command of another system that follows cannot be sent, but according to the present invention, a command of another system that follows succeeds and sends. As a result, computer resources can be efficiently used, and performance improvement such as speeding up of vector instruction processing can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention, FIG. 2 is a diagram showing a configuration of an embodiment of the present invention, FIG. 3 is a diagram showing a time chart of an operation example of setting to SQS, and FIG. FIG. 5 is a diagram showing a time chart of the selection operation, and FIG. 5 is a conventional multi-system VU.
FIG. 6 is a diagram showing a configuration, and FIG. 6 is a diagram showing a configuration of a conventional multi-system VCU. In Fig. 1, 10: VPSR 11: AQB (access queue buffer) 12: EQB (execution queue buffer 13: AQS0 (access queue stage for SU0) 14: AQS1 15: EQS0 (execution queue stage for SU0 16 : EQS1 17: Command transmission selection section 18: SQS (selection queue stage)

Claims (1)

[Claims] 1. A configuration comprising a plurality of scalar units (SU0, SU1) for processing scalar instructions, a vector execution unit (VEU) for processing vector instructions sent from these scalar units, and a vector control unit (VCU). One vector pre-decoding stage (10), which is composed of two vector units (VU) and sequentially sets the instructions sent from each scalar unit to the vector control unit (VCU), and the vector instructions from the instruction pre-decoding stage. In an information processing device having two instruction transmission queue buffers (11, 12) which are set separately for access and operation systems, the two instruction transmission queue buffers (11, 12) for the access system and operation system The instruction is set separately for the access system and the operation system, and separately for the scalar unit that is the source of the instruction. A plurality of command transmission queue stages (13 to 16) and a command transmission selection unit (17) for selecting one command from the plurality of command transmission queue stages, the command transmission selection unit (17) , Equipped with a cycle counter (171) that generates a timing signal assigned to each instruction transmission stage, and assigned to each instruction transmission queue stage (13 to 16) if there is a valid instruction to check the instruction transmission condition At the timing, a signal for selecting the instruction transmission waiting stage is generated, and if there is no instruction to check the instruction transmission condition in the other instruction transmission waiting stage at the timing defined in the other instruction transmission waiting stage A method for controlling instruction transmission in an information processing device, characterized in that a signal for selecting a stage for waiting instruction transmission having an instruction to check transmission conditions is generated. .