JPH071927B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a camera head unit having a built-in solid-state image sensor, and a video for supplying a power supply voltage to the solid-state image sensor and processing a signal from the solid-state image sensor. The present invention relates to a solid-state imaging device connected to a processor unit via a cable.

[Prior Art] With the progress of integration technology in recent years, very small-sized solid-state imaging devices such as charge-coupled devices (abbreviated as CCD) have become possible, and are used for imaging means such as television cameras and endoscopes It became so.

For example, FIG. 5 shows a conventional example of a solid-state image sensor using an interline transfer type CCD.

The light receiving portion of the solid-state image sensor 1 is composed of photodiodes 2 arranged in a matrix. The charges generated by the photodiodes 2 in each column (vertical column) are supplied to the vertical transfer CCD 4 via the read gate 3. A power supply voltage (DC voltage) of + 3V is applied to the read gate 3 via the read gate terminal LG, and the charges generated in the photodiode 2 are read every frame or field period. Vertical transfer
CCD4 is driven by 4 vertical drive pulses φV1, φV2, φV3, φV4
This is performed by applying the set clock signal, and the charges generated in the photodiode 2 are read out and transferred at a predetermined timing. The charges transferred in the vertical transfer CCD 4 are supplied to the horizontal transfer CCD 5 for each scanning line.

The horizontal transfer CCD 5 sends out the charges supplied from the vertical transfer CCD 4 one scan line at a time. The horizontal transfer CCD 5 is driven by applying a 4-phase clock signal of horizontal drive pulses φH1, φH2, φH3, and φH4.

An output gate 6 is formed at the output terminal of the horizontal transfer CCD 5,
+ 7V power supply voltage is applied through the output gate terminal OG. The signal charge output through the output gate 6 is supplied to the gate of the output transistor 7 formed of a field effect transistor (FET), and the signal charge from each photodiode is output through the signal output terminal Vout of the source of the output transistor 7. The image pickup signal corresponding to is output. To the drain of the output transistor 7 via the output drain terminal OD
A drain voltage of 16V is applied.

The gate of the output transistor 7 is also connected to the source of the reset transistor 8 formed of a FET, and after the image pickup signal of each photodiode is output, the charge applied to the gate of the output transistor 7 is at a predetermined timing by the reset pulse φR. Then, it is released from the reset drain terminal RD via the drain of the reset transistor 8. The power supply voltage of + 16V is also applied to the reset drain terminal RD.

Further, a power supply voltage of 0V is applied to the P well terminal PW of the solid-state imaging device 1, and a power supply voltage of + 8V is applied to the substrate bias terminal SUB.

FIG. 6 shows an image pickup device 14 in which a camera head 11 incorporating such a solid-state image pickup device 1 and a video processor 12 are separated via a cable 13.

The solid-state image pickup device 1 is built in a camera head 11 and is connected to a video processor 12 having a power supply circuit, a video signal processing circuit and the like via a cable 13.

As described above, the solid-state imaging device 1 requires a total of four types of power source voltages, and the four types of power source voltages divide the single + 16V power source voltage supplied from the video processor 12 as shown in FIG. We are pressing for it.

The signal output terminal Vout of the solid-state image pickup device 1 is connected to the base of the output buffer transistor Q1 ', and the image pickup signal is amplified and output from the emitter.

The emitter output of the transistor Q1 'is transmitted via the inner conductor of the coaxial cable 15 to a video signal processing circuit (not shown) in the video processor 12. The signal processed by the video processor 12 is supplied to the CRT monitor 16 and displayed.

The outer conductor of the coaxial cable 15 is grounded within the video processor 12.

In order to reduce the size of the camera head in the image pickup apparatus as described above, the applicant of the present invention has disclosed in Japanese Patent Laid-Open No. 63-1260
I devised the configuration of the integrated circuit U1 in. That is, the single power supply supplied from the video processor 12 in U1 +16
V is divided by resistors R1 ', R2', R3 ', R4', and the divided voltages are current-amplified by buffer transistors Q2 ', Q3', Q4 ', and their output voltages + 8Vout, + 7Vout, + 3Vout are respectively output. Input to the substrate bias terminal SUB, the output gate terminal OG, and the read gate LG of the solid-state imaging device 1.

[Problems to be Solved by the Invention] Here, focusing only on the output signal line of the solid-state image pickup device 1, it becomes as shown in FIG. That is, in order to transmit the output signal from the camera head 11 to the separated video processor 12, the output Vout of the solid-state image sensor 1 is buffered by the buffer Q1 '.
Drives the coaxial cable 15 with low impedance conversion. At this time, the ideal output signal is as shown in FIG. t _R is a reset portion of a signal corresponding to the reset pulse φR period, t _F is a feedthrough portion, and t _S is a photoelectric conversion signal portion proportional to the amount of incident light. Ideally, it has such a rectangular wave shape. The video processor receives this waveform and calculates the signal levels of the t _F and t _S parts by a technique such as sampling to remove noise components and effectively separate only the signal components. When a waveform with poor high-frequency characteristics such as is input, signal separation will not be effectively performed.

Here, the high frequency characteristics deteriorate due to the following reasons. The coaxial cable 15 has a capacitance as high as 100 PF / m and a matching impedance as low as several tens of Ω, especially for a micro coaxial cable. Therefore, in order to obtain an ideal waveform at the power receiving end of the video processor, the output impedance of the emitter follower composed of the transistor Q1 'and the resistor R _L must be sufficiently low with respect to the cable load.

Transistors generally have the characteristics shown in Fig. 9, and when the optimum collector current ic flows, the current amplification factor hfe
Has a maximum value, and by driving near this maximum value,
Optimal frequency characteristics can be obtained. Further, in driving a high capacity load such as the coaxial cable, in order to obtain a good frequency characteristic, the emitter size must be increased to some extent to increase the current value. In this case, the value of the base-emitter capacitance Cbe of the transistor Q1 'shown in FIG. 7 increases in proportion to the emitter size.

Here, the output stage of the solid-state imaging device (actually, charge-coupled device) 1 is a source follower with an active load, which will be described with reference to FIG. FET20 active load
It is a constant current source with a resistor 21 and a constant current value can be changed by the LG voltage, that is, the load on the source follower can be changed. The active load can be similarly considered by simply replacing it with a resistor. The capacitance Cbe becomes a capacitive load with respect to the output Vout of the source follower, and the high frequency characteristic deteriorates.

That is, the output stage of the solid-state imaging device 1 is in a state in which the capacitance Cbe and the resistance R _L are connected in parallel to the active load due to the capacitance Cbe, and the influence becomes large especially on the high frequency side. Therefore, when the frequency becomes higher, the output signal Vout from the output stage is output to the load resistance R _L via the capacitor Cbe (without being amplified), so that the current amplification factor is significantly reduced. Resulting in. For this reason, the high frequency characteristic is deteriorated.

The influence of the capacitance Cbe becomes significant when the impedance of the capacitance Cbe becomes a value close to the impedance of the output stage of the solid-state image pickup device 1, so it is advantageous to reduce the impedance of the output stage. On the contrary, when the impedance of the output stage is high, the influence of the capacitance Cbe appears even at a frequency that is not so high, and the deterioration of the high frequency characteristic becomes more remarkable.

Therefore, as described above, in order to prevent this deterioration, the output impedance of the source follower may be lowered by lowering the load resistance value of the active load, but then the current in the solid-state imaging device 1 increases and the amount of heat generation increases. It will increase. An increase in temperature of the solid-state image sensor leads to an increase in noise, which is not preferable. In this way, when trying to drive the coaxial cable load with the optimum frequency characteristic, there is a disadvantageous problem between the output stage of the solid-state imaging device and the emitter follower for driving the cable as described above.

The present invention has been made in view of the above points, and a buffer circuit capable of preventing an increase in noise due to a temperature rise of a solid-state image sensor and preventing deterioration of high frequency characteristics even in the case of a capacitive load due to a coaxial cable. An object of the present invention is to provide a solid-state image pickup device including the.

[Means and Actions for Solving Problems] As shown in FIG. 1, the solid-state imaging device 1 of the camera head 11
The output signal Vout of is received by the first transistor Q1 of the emitter follower connection having a small base-emitter capacitance C1, and converted into a low impedance signal across the resistor R1 without degrading the frequency characteristics. The signal of this resistor R1 is
A video processor that receives a second collector Q2 of an emitter follower connection capable of allowing a large collector current to sufficiently drive a capacitive load to which the coaxial cable 15 is connected and processes a signal via the coaxial cable 15 connected to an emitter resistor R2. Transmitted to 12. In this configuration, the emitter size of the first transistor Q1 is smaller than that of the second transistor, and thus the first and second transistors
The base-emitter capacitances C1 and C2 of Q1 and Q2 are C1 <C2.

This first transistor Q1 allows the signal at the output stage of the solid-state image sensor 1 to be generated in the emitter resistor R1 of the solid-state image sensor 1 without deteriorating the high frequency characteristics. Since the resistor R1 has a low impedance, the capacitance C2 is Even if the second transistor Q2 included therein is connected, it can be output to the resistor R2 without significantly deteriorating the high frequency characteristic. The base current Ib flowing through the base of the second transistor Q2 is the current amplification factor of the transistor Q2 with respect to the drive current Io of the coaxial cable 15.
Since hfe is 1 / hfe, the first resistor R1 does not have to be as small as the second resistor R2, and R1> R2 is sufficient.

In this way, a signal can be transmitted to the power receiving end side without increasing the output current of the solid-state image sensor and without deteriorating the high frequency characteristic.

EXAMPLES The present invention will be specifically described below with reference to the drawings.

FIG. 2 shows a first embodiment of the present invention.

The solid-state image pickup device 31 of the first embodiment is used as a solid-state image pickup element.
Camera head 33 with built-in CCD 32 and this camera head 3
3 and a signal processing video processor 35 connected via a cable 34, and a color monitor 36 for displaying a video signal output from the video processor 35.

In the camera head 33, a CCD 32 is arranged on the focal plane of an imaging lens (not shown), and a drive signal φR, φH1 to φH2, φV1 to φV4 for driving the CCD 35 is supplied to the CCD 32 from a video processor 35 by a cable 34. At the same time, the integrated circuit U1 'supplies various power supply voltages obtained by dividing the voltage to the terminals RD, OD to the terminals SUB, OG, LG, PW.

Further, the output terminal Vout output signal of the CCD 32 is converted to low impedance by the drive buffer 36 of the integrated circuit U1 ′,
It is transmitted to the power receiving end of the video processor 35 via the coaxial cable 37.

The drive buffer (buffer circuit) 36 has a small base-emitter capacitance like that shown in FIG.
A first transistor Q1 that converts to low impedance,
A second transistor Q2, which is connected to the base of the emitter resistor R1 for driving a cable and allows a large collector current ic to flow, is provided. The emitter resistance R2 of the second transistor Q1 is connected to one end of the coaxial cable 37 via a matching resistance R3 for matching with the coaxial cable 37.

The integrated circuit U1 'is similar to the integrated circuit U1 shown in FIG. 6 except that the driver buffer 36 is different.

The power receiving end of the coaxial cable 37 is input to the amplifier A whose input end is matched by the resistor R4. Incidentally, the series capacitance C3 of the resistor R4 is for AC termination, and if the capacitance C3 is not provided, a large direct current will flow to the drive system and the transistor
It suppresses the increase in the amount of current in Q2, that is, the amount of heat generated.

In the first embodiment, as described in FIG. 1,
By the first transistor Q1, the output signal of CCD32 is converted into low impedance without deteriorating the high frequency characteristic,
The signal is transmitted to the power receiving end side via the cable 37 by the second transistor Q2 capable of flowing a larger collector current ic. Therefore, even if the second transistor Q2 has a large base-emitter capacitance, it can be transmitted without significantly deteriorating the high frequency characteristic.

Also, since it is not necessary to increase the current of the CCD32 output stage,
The generation of noise can be prevented.

In the first embodiment, the integrated circuit U1 'is a cable drive circuit.
Since 36 is configured, the size can be reduced, and the conditions such as C1 <C2 can be easily satisfied by forming transistors Q1 and Q2 having different emitter sizes on the same chip.

FIG. 3 shows a second embodiment of the present invention.

This second embodiment is the same as the first embodiment shown in FIG.
The emitter resistance R2 of the second transistor Q2 is moved to the power receiving end.

By this movement, the integrated circuit U1 ′ in the camera head 33 is
It reduces the heat generation. That is, by moving the resistor R2 of the main heat sources Q2 and R2 in the integrated circuit U1 'to the power receiving end, heat generation in the integrated circuit U1' is reduced, and the circuit operation is the first embodiment. It has the same function as.

FIG. 4 shows a third embodiment of the present invention.

In the third embodiment, the output signal of the CCD 32 has a complementary structure, and the output impedance is complementary to the direction of the current with respect to the load, which is advantageous for improving efficiency and characteristics.

That is, in the drive buffer 36 in the first embodiment shown in FIG. 2, the base of the first transistor Q2 is connected to the emitter of the first transistor Q1 and the resistance is connected via the two equivalent diodes D1 and D2. It is connected to R1 and also to the base of a third transistor Q3 having a characteristic complementary to that of the second transistor Q2. The collector of the third transistor Q3 is grounded, and its emitter is the second
Is connected to one end of the matching resistor R3 together with the emitter of the transistor Q2.

The equivalent diodes D1 and D2 are each configured by connecting, for example, the base of a transistor to the collector. Also in this embodiment, the drive buffer and the like are formed as an integrated circuit.

A diamond structure may be used as a circuit having an output circuit (cable driving circuit) having a similar complementary structure. In either case, the input capacitance is lowered and the impedance is low on the front side connected to the output end of the CCD32, and the output impedance is low on the rear side to drive a capacitive load such as a coaxial cable with a large output current. I am able to do it.

In the first to third embodiments described above, the transistors (Q1, Q2, etc.) forming the driver buffer (36, etc.) may not be integrated circuits formed on the same chip, but may be discrete. it is obvious.

As described above, according to the present invention, the drive buffer that receives the output signal of the solid-state imaging device and drives the capacitive load such as the coaxial cable is divided into a plurality of stages, and the solid-state imaging device is provided on the front stage side. The output also has a small input capacitance, lowers the output impedance, and allows the drive current to increase on the subsequent stage, so that the solid-state image sensor does not increase the amount of heat generation and the cable is transmitted with good frequency characteristics and the receiving end. The output signal can be transmitted to the side.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic structure of the present invention, FIG. 2 is a block diagram of the first embodiment of the present invention, FIG. 3 is a block diagram of the second embodiment of the present invention, and FIG. FIG. 5 is a configuration diagram of a third embodiment of the invention, FIG. 5 is a configuration diagram of a charge-coupled device as a solid-state image sensor, FIG. 6 is a configuration diagram of a conventional example, and FIG. 7 is an output stage periphery of the solid-state image sensor in the conventional example. FIG. 8 is a waveform diagram showing the output waveform of the solid-state imaging device, and FIG. 9 is a characteristic diagram showing the current amplification factor with respect to the collector current. 1 …… Solid-state image sensor, 11 …… Camera head 12 …… Video processor 15 …… Coaxial cable 36 …… Drive buffer Q1, Q2 …… Transistor C1, C2 …… Capacitance, R1, R2 …… Resistance

Claims (1)

[Claims] 1. A solid state in which a camera head having a solid-state image sensor and a video processor section for supplying a drive signal to the solid-state image sensor and processing a signal from the solid-state image sensor are separated via a cable. In the imaging device, the camera head has a buffer circuit that receives the output signal of the solid-state image sensor and drives the cable, and the buffer circuit includes a plurality of stages, and receives at least the output signal of the solid-state image sensor. A first transistor buffer for converting to a low impedance; and a second transistor buffer for receiving the output signal of the first transistor buffer and driving the cable, and having an input capacitance of the first transistor buffer 2. A solid-state image pickup device characterized in that it is smaller than the input capacitance of the second transistor buffer.