JPH0719852B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a floating gate (floating gate) and a control gate (control gate).
Read-only semiconductor memory (EPROM: Erasable Programmable Read Only Memory) equipped with
The present invention relates to a semiconductor device used as a memory cell.

[Technical background of the invention]

As a memory cell used for EPROM, a memory cell having a structure shown in the sectional view of FIG. 3 has been conventionally known. In the figure, 1 is a p-type silicon single crystal substrate, 2 is a field insulating film, 3 and 4 are n ⁺ type source and drain regions separately provided on the surface region of the substrate 1, and 5 is a gate insulating film. , 6 is a floating gate provided on the gate insulating film 5, 7 is an insulating film provided on the floating gate 6, 8 is a control gate further provided on the insulating film 7, 9 is a source electrode, and 10 is a drain The electrode 11 is an insulating film.

In the memory cell having such a configuration, the drain electrode 10
And control gate 8 both have a high voltage, for example + 20V
By applying the above, electrons flowing from the source region 3 toward the drain region 4 cause an impact ionization (avalanche) phenomenon in the vicinity of the drain region 4. Electrons generated at this time, a part of the electrons of the hole pairs are injected into the floating gate 6 through the gate insulating film 5 and trapped. This operation is referred to as writing of information. When the information is written, electrons are trapped in the floating gate 6, so that the threshold voltage V _TH becomes high, and even if the read voltage is applied to the control gate 3. This memory cell does not turn on. Further, the threshold voltage V _TH remains low in a state in which no information is written, that is, in a state in which no electrons are trapped in the floating gate 6, and it easily turns on at this time. In such a memory cell, a state in which information is written and a state in which information is not written can be distinguished. Further, the information once written can be erased by irradiating with ultraviolet rays, and the information can be rewritten after the information is erased.

[Problems of background technology]

By the way, in the field of semiconductor devices at present, the fine processing technology of elements is remarkable, and in particular, from the viewpoint of improving the switching speed, the reduction of the channel length is being promoted. This tendency is no exception in the field of EPROM, and the channel length of each memory cell is being reduced more and more, but there is a problem in terms of characteristics. That is, as the channel length decreases, the electric field generated in the channel region becomes stronger due to the voltage (potential difference) applied between the source and the drain. Therefore, even when a drain voltage and a gate voltage of a relatively low voltage (about +5 V) used for reading an EPROM are applied, the electrons flowing from the source region to the drain region are sufficiently accelerated, and the electrons in the vicinity of the drain region are accelerated. It has energy that can cause the impact ionization as described above in the channel region. Therefore, in the highly integrated EPROM with a short channel length, when reading information, electrons are trapped in the floating gate of the memory cell where information is not originally written, and finally, The result will be the same as when the information was written. Such a phenomenon is generally referred to as erroneous writing of information, and when the memory cell having the configuration shown in FIG. 3 is highly integrated, erroneous writing cannot be prevented unless the power supply voltage is lowered. However, if the power supply voltage is reduced, the speed of reading information from the memory cell will be reduced.

[Object of the Invention]

According to the present invention, a switching speed is high, erroneous writing of information is unlikely to occur, a value of a write voltage to be applied at the time of writing information can be reduced, and further, a cell in which information at the time of reading is written. It is an object of the present invention to provide a semiconductor device capable of enhancing the discrimination between unwritten cells.

[Outline of Invention]

The present invention provides first and second regions of the second conductivity type, which are provided separately from each other in the surface region of a semiconductor substrate of the first conductivity type and serve as source and drain regions, respectively, and between the first and second regions. A floating gate and a control gate provided on the channel region via an insulating film, the floating gate being unevenly arranged on the channel region near the second region, and the control gate being The floating gate and the floating gate are adjacent to each other with an insulating film interposed therebetween, and they are unevenly distributed on the channel region in the vicinity of the first region. Further, the channel region under the floating gate has a concentration higher than that of the second region of the second conductivity type. It is characterized in that a low second conductivity type impurity is added. According to the present invention, as described above, the switching speed is high, erroneous writing of information is unlikely to occur, and the value of the write voltage to be applied at the time of writing information can be reduced. It is possible to obtain a semiconductor device capable of enhancing the discrimination between cells in which is written and cells in which is not written.

Example of Invention

Hereinafter, an example in which the present invention is applied to a memory cell of an EPROM will be described in detail with reference to the manufacturing process of FIGS. 1 (a) to (h) and FIG.

First, the p-type silicon substrate 101 is selectively oxidized to form a field oxide film 102 for separating the surface of the substrate 101 into islands, and then thermally oxidized in an oxidizing atmosphere at 900 to 1000 ° C. to form islands. An oxide film 103 having a thickness of about 250 Å was formed on the surface of the substrate 101 (Fig. 1 (a), illustration). In this step, ions may be implanted into the silicon substrate 101 to control the threshold value of the control gate, which will be described later. Continuing,
A 3000 Å-thick n-type or p-type impurity-doped polycrystalline silicon film is deposited on the entire surface by a LPCVD method, and this is patterned to form a control gate made of polycrystalline silicon.
104 was formed (the figure (b) illustration). In this state, using the control gate 104 and the field oxide film 102 as a mask, n-type impurities were ion-implanted into the silicon substrate 101 in order to control the threshold value of the channel region under the floating gate (shown in FIG. 3C).

Then, a thickness of 5 is formed around the control gate 104 made of polycrystalline silicon by thermal oxidation in an oxidizing atmosphere of 900 to 1000 ° C.
After growing an oxide film 105 of 00Å, a polycrystalline silicon film 106 doped with an n-type or p-type impurity having a thickness of 3500Å was deposited again on the entire surface by the LPCVD method (shown in FIG. 3D). Subsequently, the polycrystalline silicon film 106 is formed by using an anisotropic etching method, for example, a reactive ion etching method (RIE method).
Was removed by etching for that thickness. At this time, since the periphery of the control gate 104 is effectively thick in the height direction, the polycrystalline silicon 106 'remains around it (shown in FIG. 7E). Subsequently, the remaining polycrystalline silicon 106 'is selectively removed by etching using a photoresist pattern (not shown) formed by a photo-etching method as a mask,
A floating gate 107 was formed on one side of the control gate 104 and only on the periphery of the element portion (shown in FIG. 6F).

Then, thermal oxidation is performed in an oxidizing atmosphere at 900 to 1000 ° C. to grow an oxide film 108 having a thickness of 500 Å around the floating gate 107, and then the field oxide film 102, the control gate 104 and the floating gate 107 are used as masks. Type impurities such as arsenic were ion-implanted under the conditions of implanting energy of 50 kev and implanting dose of 1 × 10 ¹⁵ cm ^-2 (Fig. (G)).
(Shown). Next, a heat treatment is performed to activate the ion-implanted arsenic to form the n ⁺ -type diffusion layer 10 to be the source and drain regions.
Formed 9,110. Continuing, SiO ₂ was deposited on the entire surface by the CVD method.
After depositing the film 111 and opening the contact holes 112 and 112, vapor deposition and patterning of the Al film are performed to form the Al electrodes 113 and 114.
To form EPROM memory cells (Fig. (H))
And FIG. 2). Note that FIG. 2 is a plan view of FIG. 1 (h).

Then, the memory cell of the EPROM of the present invention is shown in FIG.
And the source or provided n ⁺ -type diffusion region 109 and 110 serving as the drain region are separated from each other in the island region surface of the p-type silicon substrate 101 separated by the field oxide film 102 as shown in FIG. 2, these n ⁺ -type Substrate 10 between diffusion regions 109, 110
A control gate 104 and a floating gate 107 are provided on one region (channel region) via a gate oxide film 103, and an oxide film 105 is interposed between the control gate 104 and the floating gate 107 to be insulated from each other and further floating. The channel region under the gate 107 has a structure in which an n-type impurity having a lower concentration than the n ⁺ -type diffusion regions 109 and 110 is added.

In the memory cell having such a configuration, when writing information, one of the n ⁺ type diffusion regions 109 is used as a drain region,
The other n ⁺ type diffusion region 110 is used as a source region.
That is, using the electrode 113 as a drain electrode and the electrode 114 as a source electrode, a high voltage is applied to both the drain electrode 113 and the control gate 104. At this time, the potential in the channel region is equal to or extremely close to the potential of the source region, that is, the n ⁺ type diffusion region 110, so that the electric field between the source and the drain is concentrated in the drain region, that is, the drain region.
It becomes stronger in the channel region near the n ⁺ type diffusion region 109, and hot carriers (electron-hole pairs) are generated and impact electrons are injected into the floating gate 107 due to impact ionization in this portion. As a result, information is written. In this information writing, an n-type impurity is added to the channel region below the floating gate 107 located in the vicinity of the n ⁺ -type diffusion layer 109 which will be the drain region.
Since it is sufficiently lower than the n ⁺ type diffusion region 109 and a depletion layer can be formed in the region, the generation of hot carriers due to the impact ionization is not hindered, and electrons generated thereby can be injected into the floating gate 107. .

On the other hand, when reading out the information, the source region one of the n ⁺ -type diffusion region 109 as opposed to the time of information writing, the other n ⁺
The mold region 110 is used as a drain region. That is, electrode 1
13 is a source electrode, electrode 114 is a drain electrode, an appropriate potential difference (eg, 5V) is applied between the source and drain, and then an appropriate voltage (eg, + 5V) is applied to the control gate 104.
The information is read by applying a voltage and examining the change in the characteristics of the cell in which the information is written and another cell, for example, the threshold voltage V _TH . At this time, since an n-type impurity is added to the channel region under the floating gate 107, if no charge is accumulated in the floating gate 107,
By applying the voltage of the above condition to the control gate 104, the inversion of the channel region under the floating gate 107 can be accelerated. As a result, when reading the EPROM, the value of the current flowing through the cell in which information has not been written can be made sufficiently large, so that the cell in which information has been written can be easily distinguished from the cell in which information has not been written.
Even during such reading, the electric field between the source and drain is concentrated in the drain region, that is, the n ⁺ type diffusion region 11
Since it becomes stronger near 0, generation of hot carriers may occur at this portion. However, the EPROM of the present invention
However, since the floating gate does not exist near the portion where hot carriers are generated, the generated carriers are not injected into the floating gate, and as a result, erroneous writing of information can be prevented.

Further, the information once written can be erased by irradiating it with ultraviolet rays, and the information can be rewritten after the information is erased.

As described above, in the memory cell having the structure of the present invention,
Since there is no risk of erroneous writing when reading information, the channel length can be made sufficiently short. as a result,
Since the writing efficiency at the time of writing information can be improved, it becomes possible to reduce the values of the writing voltage such as the drain voltage and the control gate voltage to be applied at the time of writing information as compared with the conventional case. For example, the voltage applied when writing information and the voltage used when reading information can both be about 5V. Moreover, it is possible to easily discriminate between cells in which information is written and cells in which information is not written during reading.

The n-type impurity added to the channel region under the floating gate has the effect of increasing the current value for a cell in which information has not been written, but cuts the current due to the floating gate in the cell in which information has been written. It may hinder the off. Therefore, in the state where the n-type impurity is added to the channel region under the floating gate, no information is written that the n-type layer is not formed in the region and that the n-type impurity is added to the channel region under the floating gate. It is necessary to set the concentration so that the cutoff of the current by the floating gate is not hindered in the filled cell.

In the above embodiment, the case where the memory cell has n channels has been described, but the present invention is not limited to this, and the same effect can be obtained even if the memory cell has p channels.

〔The invention's effect〕

As described in detail above, according to the present invention, the switching speed is fast, erroneous writing of information is unlikely to occur, and the value of the write voltage to be applied at the time of writing information can be reduced. It is possible to provide a semiconductor device having a remarkable effect such that it is possible to enhance the discrimination between the cell in which is written and the cell in which is not written.

[Brief description of drawings]

1 (a) to 1 (h) are EPROMs in an embodiment of the present invention.
Sectional views showing a manufacturing process for obtaining the memory cell of FIG.
FIG. 1 is a plan view of FIG. 1 (h), and FIG. 3 is a sectional view showing a memory cell of a conventional EPROM. 101: p-type silicon substrate, 103: gate oxide film, 104
Control gate, 105 oxide film, 107 floating gate, 109,110 n ⁺ type diffusion region, 113,114
...... Al electrode.

Claims (1)

[Claims] 1. First and second regions of second conductivity type, which are provided separately from each other in a surface region of a semiconductor substrate of the first conductivity type and serve as source and drain regions, respectively, and these first and second regions. A floating gate and a control gate provided on an intervening channel region via an insulating film, wherein the floating gate is eccentrically arranged on the channel region near the second region, and the control gate is The floating gate and the floating gate are adjacent to each other with an insulating film interposed therebetween, and they are unevenly distributed on the channel region in the vicinity of the first region, and further, in the channel region under the floating gate, a concentration higher than that of the second region of the second conductivity type. A semiconductor device characterized by adding a second conductivity type impurity having a low conductivity.