JPH0719880B2 - Complementary memory cell matrix - Google Patents

Description

The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a MOS type nonvolatile semiconductor memory device having a floating gate electrode.

[Conventional technology]

Various non-volatile semiconductor memory devices have been studied so far, but among them, MOS having a floating gate electrode
As a writable / erasable non-volatile semiconductor memory device having a p-type transistor structure, various products have been put into practical use because of the ease of the manufacturing method and the high reliability such as data retention. In particular, recently, various cell structures have been devised to compose the memory unit according to each application.

FIG. 4 (a) is a diagram showing the structure of a one-transistor type cell which is the most basic cell structure. An N-channel type, which is widely used in this structure, will be described below.
This memory cell is composed of a P-type semiconductor substrate 1, N-type source / drain diffusion layers 2a and 2b, a floating gate electrode 4, and a control gate electrode 5, and storage is for storage / emission of electrons in the floating gate electrode 4. Generally, in many cases, the state of writing electrons is called the written state, and the state of emitted electrons is called the erased state. Electrically, a sense amplifier or the like detects a threshold variation according to the accumulated charge of this cell as a current variation of the cell transistor Q _M41 , and stores it in correspondence with the “1” or “0” state.

FIG. 4 (b) shows a structure in which the P-channel memory transistor and the N-channel memory transistor having the structure shown in FIG. 4 (a) are paired (hereinafter referred to as floating gate shared N-channel P-channel memory cell). FIG. Source / drain diffusion layers 2a, 2b of opposite conductivity type to the memory cell semiconductor substrate 1, well 6 of opposite conductivity type to the substrate 1, source / drain diffusion layers 3a, 3b of opposite conductivity type to the well 6, N-channel memory transistor The floating gate electrode 4 and the control gate electrode 5 commonly cover the channel of Q _{M43 and} the channel of the P-channel memory transistor Q _M42 . This structure is known in JP-A-54-78679 and JP-A-54-27778. However, a method of forming a cell array with such P-channel and N-channel memory transistors to form a product having effective characteristics has not been known. It has a serious drawback when a cell array is composed of the cells of FIG. 4 (b).

Regarding this drawback, the operation of this cell and an example when the array is constructed will be described below.

When electrons are injected into the cell of FIG. 4 (b) to put it in a written state, as shown in FIG. 5 (a), an N-channel transistor Q _M43 ,
The threshold voltage of the P-channel transistor Q _M42 rises, respectively. The P-channel transistor is brought into a normally-on state by injecting electrons.

FIG. 5 (b) uses the cell of FIG. 4 (b) to generate Q _M51 , Q _M53 , Q
A diagram showing a cell array in which _M55 is an N-channel transistor, Q _M52 , Q _M54 , and Q _M56 are P-channel transistors, bit lines are commonly connected to respective drain diffusion layers, and word lines are commonly connected to respective control gates. Is. Here, the cells of the transistors Q _M51 and Q _M52 are connected to the word line, for example, V _DD potential,
The P channel well potential is selected as the V _DD potential, for example. At this time, if the writing state, the threshold value of the transistor Q _M51 is
Since it is higher than V _DD , transistor Q _M51 turns off. vice versa,
Since the transistor Q _M52 is in the depletion state, it is turned on. The other N-channel memory transistors Q _M53 and Q _M55 cannot be identified as the on or off state of the transistor Q _M51 unless the current is made to flow regardless of the state of writing or erasing, so that the word line potential is, for example, the ground potential. Etc. are fixed. At this time, the transistor Q _M54 source-gate control voltage V _GS when a source potential is also V _DD and the transistor Q _M52 in the transistor Q _M54 regardless write or erase state of the transistor Q _M54 since it is -V _DD Turns on. Therefore, both the current passing through the transistor Q _M52 and the current passing through the transistor Q _M54 flow in the bit line, and the state of the selected cell cannot be identified. Therefore, it is conceivable to set the source potential to the ground potential like the transistor Q _M56 . In this way, the threshold voltage of the transistor Q _M56 is Ov, so if the transistor Q _M56 is in the erased state, the transistor Q _M56 is turned off and the transistor Q _M56 is connected to the bit line.
Only the current that flows through _M52 flows and it is possible to identify. But,
Transistor Q _M56 if written, transistor
A current flows through Q _M56, and again it is impossible to identify the state of transistor Q _M52 . That is, the P-channel memory transistor, which is normally-on type in the written state, changes the voltage V _GS to -V _DD.
No matter how it changes within the range of + V _DD , current always flows in the written state, and the selected and unselected cells cannot be discriminated.

[Problems to be solved by the invention]

The composite cell of the conventional P-channel N-channel memory transistor described above has a drawback that the information of the address selected when the cell array is constructed cannot be identified.

[Means for solving problems]

A complementary memory according to the present invention includes a first conductivity type first MOS memory transistor having a floating gate electrode and a control gate electrode, a conductivity type opposite to the first MOS memory transistor, and a floating gate electrode and a control gate. A second MOS memory transistor whose gate electrodes are respectively connected to the floating gate electrode and the control gate electrode of the first MOS memory transistor; and a first MOS memory transistor of the same conductivity type as that of the first MOS memory transistor. A normally-on type first MOS type transistor connected in series to the MOS type memory transistor, and a second MOS type memory transistor of the same conductivity type, and connected in series to the second MOS type memory transistor, and A normally-off type second MOS type transistor whose gate electrode is connected to the gate electrode of the first MOS type transistor.

Further, the memory cell matrix of the present invention includes a first conductivity type first MOS type memory transistor having a floating gate electrode and a control gate electrode, a conductivity type opposite to that of the first MOS type memory transistor, and a floating gate electrode and control. A second MOS type memory transistor whose gate electrodes are connected to the floating gate electrode and the control gate electrode of the first MOS type memory transistor, respectively, and a second MOS type memory transistor of the same conductivity type as the first MOS type memory transistor, and A normally-on type first MOS type transistor connected in series to the MOS type memory transistor, and a second MOS type memory transistor of the same conductivity type, and connected in series to the second MOS type memory transistor, and A normally-off second MO whose gate electrode is connected to the gate electrode of the first MOS transistor.
The complementary memory cells having S-type transistors are arranged in a matrix as a unit, and the control gate electrodes of the first and second MOS type memory transistors are commonly connected to each row to form the first word line. And the gate electrodes of the first and second MOS type transistors are commonly connected for each row to form a second word line.
Drain electrodes of the MOS type transistors are commonly connected for each column to form a first bit line, and drain electrodes of the second MOS type transistors are commonly connected for each column to form a second bit line. The source electrode and the substrate electrode of the first MOS type memory transistor and the first MOS type transistor are commonly connected to the first power supply line of a sufficiently small voltage, and the second MOS type memory transistor and the second MOS type memory transistor are connected.
The source electrode and the substrate electrode of the MOS transistor are commonly connected to the second power supply line having a voltage higher than the absolute value of the threshold voltage at the time of erasing of the first and second memory transistors and lower than the threshold voltage at the time of writing. It is connected.

[Action]

As described above, by configuring the AND circuit with the normally-on type memory transistor and the normally-off type transistor in the written state, it is possible to identify the selected and unselected memory cells.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 (a) is a circuit diagram of an embodiment of a nonvolatile semiconductor memory device of the present invention, and FIG. 1 (b) is a circuit diagram of a memory cell which is a basic unit of information storage. The semiconductor memory device of is an example in which a cell array is configured using this memory cell.

This memory cell is composed of an N-channel memory transistor Q _M11 and a P-channel memory transistor Q _M12 whose floating gate electrodes are commonly connected, a normally-on type N-channel transistor Q _S11 and a normally-off type P-channel transistor Q _S12. There is. The control gate electrodes of the two memory transistors Q _M11 and Q _M12 are commonly connected, and the gate electrodes of the two transistors Q _S11 and Q _S12 are also commonly connected. The source electrode and the substrate electrode of the memory transistor Q _M11 are connected to a low potential power supply such as Ov, and the source electrode and the substrate electrode of the memory transistor Q _M12 are connected to a V _DD power supply such as 5 v. The drain electrode of the memory transistor Q _M11 is connected to the cell N-channel drain electrode through the transistor Q _{S11 and the} memory transistor Q _M11.
The drain electrode of _M12 is connected to the cell P-channel drain electrode through Q _S12 .

The memory cell array shown in FIG. 1 (a) is obtained by arranging the memory cells of FIG. 1 (b) in a matrix. Here, memory transistors Q _M11 , Q _M12 ,
The control gate electrodes of Q _M13 , Q _M14 and Q _M15 , Q _M16 , Q _M17 , Q _M18 are commonly connected for each row to connect the first word lines X _i and X _{i + 1.}
And transistors Q _S11 , Q _S12 , of both channels
Second word lines X _i and X _{i + 1} are formed by commonly connecting the gate electrodes of Q _S13 , Q _S14 and Q _S15 , Q _S16 , Q _S17 , Q _S18 row by row. Further, the N-channel drain electrodes are connected column by column to form the first bit lines B _i and B _{i + 1} , and the P-channel drain electrodes are connected column by column between the second bit lines B _{i and} B _i. And B _{i + 1} are configured. Further, the first and second bit lines B _i , B _i and B _{i + 1} , B _{i + 1} of each column are N
Channel bit line select transistors Q ₁₁ , Q ₁₂ and Q
Connected to nodes A and B through ₁₃ and Q ₁₄ , respectively. The node A and the node B are connected to a sense amplifier SA formed of, for example, a differential amplifier circuit through N-channel transfer gate transistors Q ₁₅ and Q ₁₆ .

Next, the driving method and operation of the circuit of this embodiment will be described. Now, assume that a cell including the transistors Q _S11 , Q _S12 , Q _M11 , and Q _M12 is selected to read information. At this time, the first word line X _i is connected to V _DD such as 5v.
Potential to the second word line For example, a low potential such as Ov is set. All the _first word lines X _{i + 1} of the other cells are set to a low potential such as Ov and the second word lines Are all at V _DD potential, eg 5v. The bit line selection signal Y _i is set to V _DD potential such as 5v, and the bit line selection signal Y _{i + 1} is set to low potential such as Ov so that only the nodes C and D are connected to the nodes A and B. To connect the nodes A and B to the sense amplifier SA, a V _DD potential such as 5v is applied to the node G. Memory transistor Q _M11 as shown in FIG. 5 (a) for the source to the control gate voltage V _GS + V _DD is applied when the selected cell was erased state memory transistor Q _M11 is turned on . Since the source-gate control voltage V _GS of Q _S11 is the transistor Q _S11 is Ov a normally-first bit line B _i eventually becomes a state in which current flows through the transistor Q _S11, Q _M11. Since the memory transistor Q _M12 is in the normally off state in the erased state and the source-gate control voltage V _GS is Ov, the memory transistor Q _M12 does not conduct and no current flows through the second bit line B _i .

On the contrary, when the selected cell is in the written state and the threshold value of the memory transistor Q _M11 is V _DD or more as shown in FIG. 5A, the source-gate control voltage V _{GS of the} memory transistor Q _M11 is Is at V _DD , the memory transistor Q _M11 is turned off. Therefore, no current flows through the first bit line B _i . On the contrary, the source-gate control voltage V _GS of the memory transistor Q _M12 is Ov, but the memory transistor Q _M12 is in the normally-on state due to writing, that is, electron injection. Furthermore, at transistor Q _S12 the voltage V
_Since -V _DD is applied to _{GS, the} transistor Q _S12 is turned on, and the second bit line B _i is connected to the transistors Q _S12 and Q _M12.
A current flows through it.

Next, the other N-channel memory transistor connected to the first bit line B _i has V _GS of Ov as represented by Q _M15.
Therefore, it is turned off regardless of the written and erased states. Therefore, the current flowing through the first bit line B _i is only for the selected cell. The other memory transistors connected to the second bit line B _i have a voltage V _GS of −V _DD as typified by Q _M16 and are turned on regardless of the written and erased states. However, since the voltage V _GS of the normally-off P-channel transistor typified by Q _S16 becomes Ov and turns off, no current flows through the second bit line B _i . That is, the current flowing through the second bit line B _i also belongs to the selected cell. This state is summarized in the table below.

Eventually, only the current of the selected cell flows through both the first bit line B _i and the second bit line B _i, and as a result, the selective identification read operation becomes possible. The word line driving method is to decode the word lines X _i and X _i by associating potentials such as V _DD and Ov with each other, which means that V _DD is Ov or Ov is V
_This can be easily achieved by using an inverted signal of _DD . Further, when the cell consisting of the transistors Q _S13 , Q _S14 , Q _M13 , Q _M14 is selected, the bit line selection signal Y _i , Y _{i + 1} is switched,
This is performed by connecting only nodes E and F to nodes A and B, and the reading method is the same as above.

The writing operation is performed by connecting only the node A to a programming power source such as 10v. At this time, the sense amplifier SA sets the node G to a low potential such as Ov and disconnects it from the node A. When selecting and writing a cell composed of the transistors Q _S11 , Q _S12 , Q _M11 , and Q _M12 , the first word line X _{i is set} to, for example, 15v.
Etc., the first word lines of the other memory transistors are all set to a low voltage. At this time, the second word lines of the selected and non-selected cells may have a low voltage or a high voltage.
If node B is disconnected from all nodes at the time of writing, there is no current path flowing from V _DD through the bit line. Channel current flows through the first bit line B _i only to the memory transistor Q _M11 the above driving method, electrons are injected into the floating gate electrode of the memory transistor Q _M11, Q _M12.

FIG. 2 (a) is an embodiment in which the nonvolatile semiconductor memory device of the present invention is realized on a P-type silicon substrate, and is a plan view showing two sets of cells H in FIG. 1 (a), and FIG. b), (c),
(D) and (e) are respectively AA, BB, CC, in FIG.
It is sectional drawing of DD line.

Here, the P-type silicon substrate 1, the n-type impurity diffusion layers 2a, 2b,
2c, 2d, P-type impurity diffusion layers 3a, 3b, 3c, 3d, floating gate electrode 4, control gate electrode 5 constitute a first word line, and N-type well 6, interlayer insulating film 7, field insulating film 11 are formed. And the transistor gate electrode 10 constitutes the second word line. 8a is the first bit line 9a and the n-type impurity diffusion layer 2c
A contact hole for connection with the second bit line 9b and a contact hole for connection with the P-type impurity diffusion layer 3c, 8c is a low potential power supply line 9c, a source electrode diffusion layer 2a of the N-channel memory transistor and a substrate electrode. A contact hole that simultaneously connects to the diffusion layer 3d, and a contact hole 8d that simultaneously connects to the V _DD power supply line 9d, the source electrode diffusion layer 3a of the P-channel memory transistor, and the N-type well electrode diffusion layer 2d. A major feature is that the floating gate electrode 4 covers the N channel channel and the P channel channel in common. FIG. 3 (b) is another embodiment in which the nonvolatile semiconductor memory device of the present invention is realized on a P-type silicon substrate, and is a plan view showing two sets of cells I in FIG. 1 (a), FIG. (A), (b) is sectional drawing of the AA line of FIG. 3 (a), and a BB line, respectively.

This embodiment is characterized by the V _DD power supply line 12c and the low potential power supply line.
This is to reduce the cell area by using 12d as one for two sets of cells. Here, 12b and 12e are first bit lines, 12a is a second bit line paired with 12b, and 12f is a second bit line paired with the first bit line 12e.
As shown in FIG. 3, the P-channel memory transistor and the normally-off P-channel transistor are arranged adjacent to each other and in the same well.

Although the embodiment on the semiconductor has been described with respect to a P-type silicon substrate, it may be an N-type silicon substrate. In that case, the N-channel memory transistor is formed in the P-type well. Further, various circuits such as a sense amplifier using a current mirror circuit can be applied to the sense amplifier circuit for performing the read operation, and various word line decoding circuits can be applied.

The feature of this cell is that two signals are obtained at the time of reading. That is, in the erased state, current flows from the node A to the ground power supply in the first bit line, but no current flows in the second bit line. Conversely, in the written state, no current flows through the first bit line, but V _DD flows through the second bit line.
A current flows from the power supply to the node B. That is, the cell itself has the power to charge up the node B during writing. This point is largely different from the conventional cell having the N-channel memory transistor structure only having the discharging function, and the high current reading capability enables high-speed reading. Further, for example, a sense amplifier circuit configuration is possible in which the potentials of the node A and the node B are set to the same potential at a certain potential, and then the potential difference between the node A and the node B is differentially amplified. It became possible.

That is, according to the present invention, it is possible to configure a cell array using memory transistor cells by combining P channels and N channels, and since the operation is suitable for realizing high-speed reading, a large-capacity non-volatile memory capable of high-speed reading. It has become easier to commercialize a memory storage device.

〔The invention's effect〕

 As described above, the present invention has the following effects.

By constructing a memory cell by connecting complementary MOS memory transistors and complementary MOS transistors of the same conductivity type in series in the substrate, the configuration can be simplified.
By providing the power source and the electrode of the bit line on the side of the transistor having a simple structure, a cell structure capable of easily forming a memory array is formed.

By configuring an AND circuit with a normally-on type memory transistor and a normally-off type transistor in a written state, selection and non-selection memory cells can be identified.

By supplying a current from the memory array side to the sense amplifier, the driving power of the sense amplifier using a current mirror circuit etc. is improved and high-speed read is possible, and as a result, it is easy to commercialize a large-capacity nonvolatile memory device. it can.

[Brief description of drawings]

FIG. 1 (a) is a circuit diagram of one embodiment of the nonvolatile semiconductor memory device of the present invention, FIG. 1 (b) is a circuit diagram of cells constituting the semiconductor memory device of FIG. 1, and FIG. A plan view and a cross-sectional view of a nonvolatile semiconductor memory device of the present invention on a semiconductor substrate,
FIG. 4 is a plan view and a sectional view of an embodiment of a nonvolatile semiconductor memory device of the present invention on a semiconductor substrate, FIG. 4 (a) is a view showing a conventional N-channel single memory cell, and FIG. 4 (b). Is a diagram showing a conventional floating gate shared N-channel P-channel memory cell, FIG. 5 (a) is a diagram showing IV characteristics of the floating gate shared N-channel P-channel memory cell, and FIG. It is a figure which shows the example of a cell array structure in a floating gate shared N channel P channel memory cell. 1 ... P-type silicon substrate, 2a, 2b, 2c, 2d ... n-type impurity diffusion layer, 3a, 3b, 3c, 3d ... P-type impurity diffusion layer, 4 ... floating gate electrode, 5 ... control gate Electrode (first word line), 6 ... N-type well, 7 ... Interlayer insulating film, 8a-8d ...
… Contact holes 9a, 12b, 12c …… 1st bit line metal wiring, 9b, 12a, 12f, 1
2g …… Second bit line metal wiring, 9c, 12d …… Low potential power metal wiring, 9d, 12c …… V _DD power metal wiring, 11 …… Field insulating film, Q _S11 , Q _S13 , Q _S15 , Q _S17 ... normally-on type N-channel transistor, Q _S12 , Q _S14 , Q _S16 , Q _S18 ... normally-off type P-channel transistor, Q _M11 , Q _M13 ,
Q _M15 , Q _M17 ...... N channel memory transistor, Q _M12 , Q
_M14 , Q _M16 , Q _M18 ...... P channel memory transistor, X _i ,
X _{i + 1} ... the first word line, B _i , B _{i + 1} ... the first bit line,

Claims (1)

[Claims] 1. A first MOS type memory transistor of one conductivity type having a floating gate electrode and a control gate electrode, and a first M type memory transistor.
A second MOS type memory transistor having a conductivity type opposite to that of the OS type memory transistor, wherein the floating gate electrode and the control gate electrode are respectively connected to the floating gate electrode and the control gate electrode of the first MOS type memory transistor; M of 1
The same conductivity type as the OS type memory transistor and the first MO
A normally-on type first MOS type transistor whose source is connected to the drain of the S type memory transistor;
Of the same conductivity type as the MOS type memory transistor of
Complementary memory cell having a normally-off type second MOS transistor whose source is connected to the drain of the MOS type memory transistor and whose gate electrode is connected to the gate electrode of the first MOS type transistor These are arranged in rows and columns, the control gate electrodes of the first and second MOS type memory transistors are commonly connected for each row to form a first word line, and the first and second MOS type transistors are formed. The gate electrodes are commonly connected to each row and the second
, The drain electrode of the first MOS type transistor is commonly connected to each column and the first bit line is configured, and the drain electrode of the second MOS type transistor is commonly connected to each column. To form a second bit line, and the source electrode and the substrate electrode of the first MOS type memory transistor and the substrate electrode of the first MOS type transistor are commonly connected to a first power supply line of a sufficiently small voltage, Second
The source electrode and the substrate electrode of the MOS type memory transistor and the substrate electrode of the second MOS type transistor are commonly larger than the absolute value of the threshold voltage at the time of erasing of the first and second memory transistors, and at the time of writing. A memory cell matrix connected to a second power supply line having a voltage lower than a threshold voltage.