JPH0720053B2 - Flip-flop circuit - Google Patents

Description

The present invention relates to a flip-flop circuit, and more particularly to a function of preventing data through of a master slave type flip-flop circuit having a vertical two-stage emitter coupled logic (ECL) configuration. And a flip-flop circuit having

[Conventional technology]

Conventionally, a flip-flop circuit of this type of ECL configuration has a differential circuit for inputting a data signal with respect to a high-potential-side reference potential, a differential circuit for holding that data, and a function for reading and holding data. To control the output voltage of the master latch side, two latch circuits with a vertical two-stage ECL configuration using a differential circuit in which a clock signal is input to the reference potential on the low potential side are used. A master slave type of so-called vertical two-stage ECL configuration that is read as a signal is well known. This master-slave flip-flop circuit causes the input data signal to have a rising or falling edge of the clock by alternately performing the function of reading and holding the data by the master side latch and the slave side latch according to the clock signal. It has the function of outputting as a trigger. In such a master slave type flip-flop circuit, when the clock signal moves in the direction opposite to the trigger edge, the place where the output signal of itself should be held is transiently read by both master and slave latch circuits. Therefore, there is a data through problem that the data signal is output as it is.

As a circuit that takes measures against the data through problem,
There is a circuit shown. In FIG. 6, this circuit is a master slave type flip-flop circuit having a vertical two-stage ECL configuration, and has a CK (clock) input terminal 1, a D (data) input terminal 2, a Q, output terminals 3 and 4, V _CC power supply terminal 5, V _EE power supply terminal 6 and npn transistors 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 2
1,22,23,24,25,26,27,28,29 and resistance 31,32,33,34,35,3
It comprises 6,38,39,40,41,42 and constant current sources 80,81. Here, transistors 12 to 17 are master side operating transistors, transistors 18 and 19 are master side emitter follower transistors, resistors 31 and 32 are master side collector load resistors, and resistors 33 and 34 are emitter follower resistors. , The constant power source 80 supplies a constant current I _CS1 , and the transistors 20 to 25 are slave side differential transistors.
26 and 27 are emitter follower transistors on the slave side,
Resistors 35 and 36 are collector load resistors on the slave side.
38 is an emitter follower resistor on the slave side, the constant current source 81 supplies a constant current I _CS2 , the base of the transistor 30 is connected to the reference potential (VR1), the transistor one-day input emitter follower transistor, and R41 the input emitter follower. Resistors, transistors 28 and 29 are output emitter follower transistors, resistors R31 and R40 are output emitter follower resistors, V _CC
A power supply voltage on the high potential side is applied to the power supply terminal 5, a power supply voltage on the low potential side is applied to the V _EE power supply terminal 6, and a constant current I _CS3 is supplied to the constant current source 83.

The operation of the conventional master slave type flip-flop circuit shown in FIG. 6 will be described. When a low (LO) level signal is being input to the CK (flock) signal input terminal 4, the differential circuit on the low potential side on the master side is the transistor 11
Is on, the transistor 16 is off, and the latch circuit has either the differential transistor 12 or 15 in operation according to the signal input to the D (data) signal input terminal 2 and the data reading function. Have. At this time, in the low potential side differential circuit on the slave side, the transistor 24 is in the ON state,
The transistor 25 is in the OFF state, the output signal state of the latch circuit is fed back by the emitter follower transistors 26 and 27, and one of the differential transistors 21 and 22 becomes the operating state, and the clock has the function of holding data. When the signal is high (HI) level, the reverse operation to the above operation is performed in each latch circuit on the master side and the slave side, the master side has a data holding function, and the slave side has a data reading function. Have.

Next, the operation of the master slave side flip-flop circuit of this conventional example to prevent data through will be described. As shown in FIG. 3, in the conventional example, the resistor R42 and the constant current source 80 are connected in series to the reference voltage generating circuit that is input to the low potential side differential circuit and is input to the reference potential side differential circuit. ,
The circuit configuration is such that the high potential side of the resistor 42 is connected to the base of the transistor 24 on the slave side, and the low potential side of the resistor 42 is connected to the base of the transistor 17 on the master side. With this circuit configuration, the reference potential of the differential circuit on the low potential side on the master side is generated by the constant current I _CS of the constant current source 80 flowing through the resistor 42 having a lower resistance value R42 than the reference potential on the slave side. Low potential drop [R42 × I _CS ]. Therefore, as shown in FIG. 3, when the clock signal changes from high to low level (HI → LO), the master side shifts from data holding to data reading operation, while the slave side shifts from data reading to data holding operation. Compared with, it is performed when the clock signal voltage is [R42 × I _CS ] lower, so the time difference Δ
T can occur and data through can be prevented.

[Problems to be Solved by the Invention]

The conventional master-slave flip-flop circuit of the conventional vertical two-stage ECL configuration uses the potential drop due to the resistance as the reference potential of the differential circuit that controls the data reading and holding functions of the master side and the slave side. Since the potential difference is provided, there is a drawback in that the amount of potential drop greatly changes due to variations in resistance manufacturing, temperature dependence, etc., and the noise margin for the clock input signal is greatly reduced.

An object of the present invention is to provide a flip-flop circuit which solves the above-mentioned drawbacks and prevents data through without reducing the noise margin with respect to a clock input signal due to manufacturing variations, temperature dependence and the like. .

[Means for Solving the Problems]

According to the configuration of the present invention, a first differential circuit which is located on the high potential side and receives data, a second differential circuit which holds the data, and the first differential circuit which is located on the low potential side are provided. Latch circuit on the master side having a third differential circuit for controlling the differential circuit, a fourth differential circuit located on the high potential side and receiving the output signal of the master section, and the fourth differential circuit. Slave side having fifth differential circuit for holding output signal data of differential circuit and sixth differential circuit located on the low potential side and controlling the fourth and fifth differential circuits In a master slave type flip-flop circuit including a vertical two-stage ECL equipped with the latch circuit of the above, as a transistor constituting the low potential side differential circuit operated by a clock signal, another low potential side differential circuit is used. That a transistor whose operating voltage is different from that of the transistor is used Characterize.

〔Example〕

 The present invention will now be described with reference to the drawings.

FIG. 1 shows a flip-flop circuit according to the first embodiment of the present invention, which is a master-slave type having a vertical two-stage ECL configuration,
(Clock) input terminal 1 and D (data) input terminal 2
, Q output terminal 3, output terminal 4, V _CC power supply terminal 5
, V _EE power supply terminal 6 and npn transistors 12, 13, 14, 15, 1
7,18,19,20,21,22,23,24,25,26,27,28,29 and resistance 31,3
2,33,34,35,36,37,38,39,40,41 and constant current source 80,81,
Three npn transistors 71, 72, 73 connected in parallel with each other
And a transistor group 16 composed of. Here, the transistors 12 to 17 are differential transistors on the master side, the transistors 18 and 19 are emitter follower transistors on the master side, the resistors 31 and 32 are collector load resistors, and the resistors 33 and 34 are emitter follower resistors. The current source 80 flows a constant current I _CS 1, the transistors 20 to 25 are slave side differential transistors, the transistors 26 and 27 are slave side emitter follower transistors, and the resistors 35 and 36 are collector load resistors. 37 and 38 are emitter follower resistors on the slave side, the constant current source 81 supplies a constant current I _CS2 , the base of the transistor 15 is connected to the reference potential (VR1) on the high potential side, and the transistor 11 is an input emitter follower transistor. Resistor 41 is an input emitter follower resistor, transistors 28 and 29 are output emitter follower transistors, and resistors 39 and 40 are output emitter follower resistors and transistors. 17,
The base of 24 is connected to the reference potential (VR2) on the low potential side.

Further, the transistors 12 and 15 have their emitters commonly connected and form a differential circuit to which a data signal is input, and the transistors 13 and 14 have their emitters commonly connected to form a differential circuit that holds a data signal. The transistors 17 and 16 whose collectors are commonly connected to the respective emitter junctions form a low-potential-side differential circuit for selectively controlling the function of reading or holding a data signal, the emitters of which are commonly connected. 12,15 have their collectors connected to the collectors of the transistors 13 and 14, respectively, and from the connection points to the bases of the differential transistors 14 and 13 for holding data via the emitter follower transistors 18 and 19, respectively. Feedback is performed to configure the master side latch circuit. The same emitter follower output signal is input to the bases of the differential transistors 20 and 23 as a data signal of a slave side latch circuit having the same circuit configuration as the master side latch circuit. At this time, among the four transistors forming the low potential side differential circuit, only the transistor 16 to which the clock signal of the master side differential circuit is input is the other reference potential side transistor 17 or the slave side differential transistor. Three transistors 71, 72, 73 and collector-base-emitter having the same shape and the same manufacturing method as 25, 24 are commonly connected to each other, and a circuit configuration for performing a common operation is adopted as one transistor.

The operation of the master slave type flip-flop circuit of this embodiment for preventing data through will be described.

Assuming that the constant current I _CS flows to the transistors 16, 17, 25, 24 by the constant current sources 80, 81 on the master side and the slave side, the transistor 16 has the same characteristics as the other transistors 17, 24, 25. Since the transistors 71, 72 and 73 are commonly connected, the current flowing through each of the transistors 71, 72 and 73 is I _CS / 3. The relationship between the operating voltage of the transistor and the current is as follows.

Here, I is the operating emitter current, V is the operating base-emitter voltage, I ₀ is the saturation current density, q is the charge amount, n is the emission coefficient, k is the Boltzmann constant, and T is the temperature.

As shown in FIG. 4, transistors 71, 72, 73, 17, 25, 24
The base-emitter voltage when a constant current I _CS flows through V _F
Then, since the current is shunted in the three transistors 71, 72, 73, the operating voltage becomes low by ΔV _F 28 mV.

As a result, when the clock signal goes from high to low (HI → LO), the master side shifts from data retention to data read operation as compared to the slave side from data read to data retention operation, as shown in Fig. 4. Since the reference potential VR2 on the low potential side is lower than the reference potential VR2 by ΔV _F , the time difference ΔT is delayed and data through can be prevented.

In FIG. 4, level 90 indicates transistors 71, 72, 73.
The operating voltage, level 91 is the operating voltage of the transistors 17, 25, 24.

In the master slave type flip-flop circuit of the present embodiment, transistors having the same characteristics are used for the low potential side differential circuits on the master side and the slave side, and only three transistors 16 to which the clock signal on the master side is input have three transistors. By connecting in parallel, the difference in operating voltage can be used to stabilize the operation of differential circuits on the low potential side between the master side and slave side, with stability against manufacturing variations and temperature changes. You can

FIG. 2 is a circuit diagram showing a master slave type flip-flop having a vertical two-stage ECL structure which is a flip-flop circuit according to the second embodiment of the present invention. In FIG. 2, the flip-flop circuit of this embodiment is the same as the transistor group of FIG.
It does not have 16 and instead has a transistor group 54 consisting of three transistors 51, 52, 53. Other parts are the same as in FIG. In this embodiment, the transistor group 54 to which the reference potential VR2 of the differential circuit on the slave side is input is the transistor 5 having the same shape and the same manufacturing method as the other transistor 25 on the clock signal input side and the differential transistors 16 and 17 on the master side.
Three 1,52,53 collectors, bases, and emitters are connected in common, and a circuit configuration is adopted in which one transistor operates in common.

In the master slave type flip-flop circuit of this embodiment, as shown in FIG. 5, the reference potential VR on the low potential side of the differential circuit on the slave side that controls the function of reading and holding data.
By lowering the operating voltage of the transistor group 54 input by 2 by ΔV _F , the slave side shifts from the data reading operation to the data holding operation for a time ΔT compared to the master side shifting from the data holding operation to the data reading operation. Data through can be prevented quickly.

In FIG. 5, level 92 is the operating voltage of the transistors 16 and 17, level 93 is the operating voltage of the transistors 51, 52 and 53, and level 94 is the operating voltage of the transistor 25.

The flip-flop circuits of the first and second embodiments of the present invention are
In the master-slave flip-flop circuit of the vertical two-stage ECL configuration, the transistors forming the differential circuit on the low potential side operated by the clock signal are different in operating voltage from other differential transistors on the low potential side. As a concrete means for changing the operating voltage of the transistor, a plurality of transistors of the same shape are connected in common (collectively connected in parallel) for collector, base and emitter, respectively, so that one transistor operates in common. There is.

〔The invention's effect〕

As described above, according to the present invention, in the master slave flip-flop circuit having the vertical two-stage ECL configuration, transistors having different operating potentials are used as the transistors configuring the second stage differential circuit to which the clock signal is input. The effect of stable data through can be prevented without reducing the noise margin of the clock input signal due to the variation in the resistance value due to the manufacturing variation of the resistance and the temperature dependence which are the drawbacks of the prior art.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a master-slave flip-flop circuit having a vertical two-stage ECL configuration according to the first embodiment of the present invention,
FIG. 2 is a circuit diagram of a master-slave flip-flop circuit having a vertical two-stage ECL structure according to a second embodiment of the present invention,
3, 4 and 5 are timing charts schematically showing the operation of preventing data through, and FIG. 6 is a circuit diagram of a conventional master-slave flip-flop circuit having a vertical 2-stage ECL configuration. Is. 1 …… Clock signal input terminal, 2 …… Data signal input terminal, 3,4 …… Output signal terminal, 5 …… High potential side power supply voltage terminal, 6 …… Low potential side power supply voltage terminal, 11 …… Input emitter follower transistor, 41 …… Input emitter follower resistor, 28,29 …… Output emitter follower transistor, 39,40 …… Output emitter follower resistor, 12 to 17…
… Master side differential transistors, 20 to 25 …… Slave side differential transistors, 18,19 …… Emitter follower transistors, 26, 27 …… Emitter follower transistors, 3
1,32 …… Collector load resistance, 35,36 …… Collector load resistance, 33,34 …… Emitter follower resistance, 37,38 …… Emitter follower resistance, 80,81,82 …… Constant current source.

Claims (3)

[Claims] 1. A first data input terminal located on the high potential side
Of the master side having a differential circuit of, a second differential circuit that holds the data, and a third differential circuit that is located on the low potential side and that controls the first and second differential circuits. The latch circuit, the fourth differential circuit located on the high potential side and receiving the output signal of the master section, the fifth differential circuit holding the output signal data of the fourth differential circuit, and the low differential circuit. A master-slave-type flip-flop composed of a vertical two-stage ECL having a slave-side latch circuit having a sixth differential circuit located on the potential side and controlling the fourth and fifth differential circuits. In the flip-flop circuit, a transistor whose operating voltage is different from that of another low potential side differential transistor is used as a transistor constituting the low potential side differential circuit which operates by a clock signal. 2. The transistor on the clock signal input side of the transistors forming the third differential circuit on the master side is a transistor in which a plurality of transistors having the same shape as the transistor on the reference potential side are connected in parallel. ) The described flip-flop circuit. 3. The transistor on the reference potential side of the transistors constituting the sixth differential circuit on the slave side is formed by connecting in parallel a plurality of transistors having the same shape as the transistors on the clock signal input side. ) The described flip-flop circuit.