JPH0736504B2 - Master-slave D-type flip-flop circuit - Google Patents

Description

The present invention relates to an electronic circuit, and more particularly to a master-slave type D-type flip-flop circuit.

[Conventional technology]

2 and 3 are circuit diagrams of a conventional master-slave type D-type flip-flop. In the figure, 1.6 is a power supply terminal, 2,3 are data input terminals, 4,5,32 are clock input terminals, 16,25 are constant current sources, 7,8,12,13,14,15,17,18, 21,2
2,23,24,26,27,33,34 are transistors, 10,11,19,20,28,
29, 35 and 36 are resistors, and 30 and 31 are data output terminals.

In Figure 2, when transferring data from master to slave,
In order not to saturate the input transistor of the slave part,
An emitter follower is added between the master and slave in order not to saturate the transistor that feedback of the master part takes,
The circuit configuration is such that an emitter follower is added in the latter stage of the slave in order not to saturate the feedback transistor in the slave section and to enable ECL output.

Further, in FIG. 3, when the data is transferred from the master to the slave, in order not to saturate the input transistor of the slave and not to saturate the transistors to which feedback is applied respectively in the master section and the slave section, the logic of the master section and the slave section are Since the amplitude is reduced, the circuit configuration does not require an emitter follower.

[Problems to be Solved by the Invention]

FIG. 2 shows a circuit in which one emitter follower is inserted after the master slave. The emitter follower in the latter stage of the master does not saturate the input transistors 17 and 18 of the slave when transferring data from the master to the slave, and when feedback is applied to the base of the master side transistor 11 and the base of the transistor 12, the transistor 12 And the transistor 13 is used to prevent saturation, and the slave part emitter follower is
It is used to prevent the transistors 21 and 22 from being saturated when feedback is applied to the base of 21 and the base of transistor 22, and to enable ECL output and facilitate the interface to the next stage. Since four are used, there is a drawback that the current consumption increases.

Further, FIG. 3 shows a circuit that does not use an emitter follower.
Although the circuit in FIG. 3 can reduce current consumption, when feedback is applied to the base of the transistor 12 and the base of the transistor 13 in the master section, the transistors 12 and 13 are not saturated, and data is transferred from the master section to the slave section. In order to prevent the transistors 17 and 18 in the slave section from being saturated when transferring, and to prevent the transistors 21 and 22 from being saturated when feedback is applied to the bases of the transistors 21 and 22 in the slave section, The logical amplitude of each is reduced. However, since the logical amplitude of the slave unit is small, there is a drawback that the interface to the next stage is limited.

An object of the present invention is to provide a master-slave type D-type flip-flop circuit that solves the above problems.

[Means for Solving the Problems]

In order to achieve the above object, the present invention provides an EC for a semiconductor integrated circuit.
In the master part of the master-slave type D-type flip-flop circuit composed of L, one end of the first resistor and one end of the second resistor that generate the logic amplitude are connected to the cathode of the diode, and the anode of the diode is used as the power supply. And the other end of the first resistor is connected to one base input of the feedback differential pair of the master part and the base input of the input differential pair of the slave part, and the other end of the second resistor is connected to the master part. Is connected to the other base input of the feedback differential pair and the base input of the input differential pair of the slave section.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In the figure, transistors 7, 8, 12 and 13 and the like form a differential pair in the master section, and transistors 17 and 18, 21 and 22 form a differential pair in the slave section. The present invention is the resistance of the master part
Connect one end of 10 and one end of the resistor 11 to the cathode of the diode 9, and connect the anode of the diode 9 to the power supply terminal 1.
The other end of the resistor 10 is connected to the base of the transistor 13 and the base of the transistor 17, and the other end of the resistor 11 is connected to the transistor 12
It is connected to the base of and the base of transistor 18. The other configuration is the same as the conventional one.

Next, the operation will be described. The voltage drop in the diode 9 is determined by the constant current source 16 and is always a constant value. Therefore, the potential of the data signal generated by the resistors 10 and 11 is constantly lowered by the voltage drop of the diode 9. Therefore, even if one end of the resistor 10 is connected to the base of the transistor 12 and one end of the resistor 11 is connected to the base of the transistor 13, the base potentials of the transistors 12 and 13 are always lower than the collector potential, so that saturation does not occur. . Also, connect one end of the resistor 10 and the base of the transistor 17,
Even if one end of the resistor 11 and the base of the transistor 18 are connected, the base potentials of the transistors 17 and 18 are always lower than the collector potential, so that saturation does not occur. Therefore, it is not necessary to interpose the emitter follower between the master and slave, and the current consumption for two emitter followers is reduced.

Even if the logic amplitude on the slave side is increased, the emitter follower on the slave side is attached, so
21, the transistor 22 is not saturated, and ECL output is possible.

〔The invention's effect〕

As described above, the present invention reduces the current consumption by reducing the potential of the data of the master section using the diode, thereby eliminating the need to insert the emitter follower between the master and slave, and adding the emitter follower to the slave section. Has the effect that can be output with ECL.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2, and FIG.
The figure shows a conventional master-slave type D-type flip-flop circuit. 1,6 …… Power supply terminal, 2,3 …… Data input terminal, 4,5,32 ……
Clock input terminal, 9 ... Diode, 7,8,12,13,14,1
5,17,18,21,22,23,24,26,27 …… Transistor, 10,11,1
9,20,28,29 …… Resistance, 16,25 …… Constant current source, 30,31 …… Data output terminal

Claims (1)

[Claims] 1. In a master section of a master-slave type D-type flip-flop circuit composed of ECL of a semiconductor integrated circuit, one end of a first resistor and one end of a second resistor for generating a logic amplitude are connected to a cathode of a diode. Connect the anode of the diode to the power supply, connect the other end of the first resistor to one of the base inputs of the feedback differential pair of the master section and the base input of the input differential pair of the slave section, and A master-slave type D-type flip-flop circuit characterized in that the other end of the resistor 2 is connected to the other base input of the feedback differential pair of the master section and the base input of the input differential pair of the slave section.