JPH0720055B2 - Digital time division multiple integration circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital time division multiplex integration circuit, and in particular,
The present invention relates to a digital time division multiple integration circuit capable of handling a plurality of signals with one circuit.

[Prior Art] A conventional multiple integration circuit of this type has been integrated using an RC analog circuit or a counter circuit. In such an RC analog circuit or counter circuit, one circuit must be provided corresponding to one signal, and therefore, a plurality of same circuits are required for a plurality of signals.

[Problems to be Solved by the Invention] Since the conventional multiple integration circuit described above needs to integrate one signal using one RC analog circuit or counter circuit, the same circuit is used when processing a large number of signals. Has to be provided for the number of signals, and the number of circuits increases as the number of signals increases.

[Means for Solving the Problems] The object of the present invention is to solve the above-mentioned problems of the prior art.
An object of the present invention is to provide a digital time division multiplex integration circuit capable of integrating a plurality of signals with one circuit.

The digital time division multiplex integration circuit of the present invention includes a synchronizing circuit for synchronizing input signals which are time-division multiplexed and input, an address generation circuit for generating an address corresponding to a time slot of the input signal, and an input signal. While active, continue to add the set number of bits in that time slot, hold the value as long as the input signal is active after reaching the set maximum value, and set the minimum value when the input signal becomes inactive Until it becomes, the arithmetic circuit that continues to subtract in that time slot, the circuit that activates the output signal until the maximum value after addition and the minimum value after subtraction, and the arithmetic result from the arithmetic circuit The storage circuit that stores the address at the address corresponding to the time slot of the input signal and the storage circuit that stores the calculation result from the calculation circuit in the storage circuit in a stable manner A latch circuit that holds the previous value that has been stored, and a circuit that integrates the calculation result from the calculation circuit on the storage circuit and outputs the result in time division multiplex or at an arbitrarily specified timing It is characterized by being.

[Embodiment] FIG. 1 is a circuit diagram of an embodiment in which the digital time division multiplex integration circuit according to the present invention is used as a chatter absorption circuit.

The timing output signal 101 outputs the timing of data sampling synchronized with the time slot or the timing of memory writing. The input signal input to the input terminal 117 is synchronized (sampled) by the synchronization circuit 116.

When “1” is input to the input terminal 117, the AND gate 106 selects the output of the NAND gate 104. NAND gate 104
If Q ₀ = Q ₁ = 1 then the output will be “1”, so Q ₀
The arithmetic unit 103 adds “1” to the values of Q ₀ and Q ₁ until = Q ₁ = 1. The adders S ₀ and S ₁ are connected to the R of the timing output circuit 101 via the buffers 111 and 112 with three-state gates.
It is written in the memory 115 at the timing specified by the signal. While writing to the memory, the previous value stored in the memory 115 is changed to the timing output circuit 101 so that the value does not change.
It is held in the latch circuit 102 at the timing designated by 0 of 0. When the values of Q ₀ and Q ₁ are added and Q ₀ = Q ₁ = 1 is reached, the output of the output terminal 118 becomes “1” and the output of the NAND gate 104 becomes “0”. As a result, the arithmetic unit 103 stops the addition operation, and as long as “1” is input to the input terminal 117 thereafter,
In ₀ = Q ₁ = _1, the output of the output terminal 118 is kept at "1".

Next, when “0” is input to the input terminal 117, the AND gate 107
Causes the output of the NAND gate 105 to be selected. NAND gate 1
The output of 05 is “1” unless Q ₀ = Q ₁ = 1.
103 subtracts 1 from the values of Q ₀ and Q ₁ . Output of calculator S ₀ , S
₁ is written in the memory 115 as at the time of addition, and the arithmetic unit Q ₀ =
Continue subtraction until Q ₁ = 1.

Incidentally, 109 is an AND gate, 108 and 110 are OR gates, and 113 is a buffer with a 3-state gate.

With the above operation, when a particular time slot is taken out, the integration result of the signal input from the input terminal 117 is output from the output terminal 118, as shown in FIG.
The input signal B is the output of the synchronizing circuit 116 shown in FIG. “R” and “0” are outputs of the timing output circuit 101 in FIG. 1, S ₀ and S ₁ are outputs of the subtractor 103, and Q
Similarly, ₀ and Q ₁ are outputs of the latch circuit 102, and the output signal is a signal appearing at the output terminal 118.

Also, as shown in FIG. 3, when viewed on the time axis, the input terminal
The input signal of 117 and the output signal of the output terminal 118 are time-division multiplexed into n time slots. The address generation circuit 114 generates an address corresponding to each time slot, and each time slot is independently integrated by this circuit.

[Effects of the Invention] As described above, the present invention has an effect that a single circuit can handle a plurality of signals by time division multiplexing and can reduce the hardware and the number of signal lines.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment using a digital time division multiplex integration circuit according to the present invention as a chatter absorption circuit. FIG. 2 is a timing chart showing the operation of this circuit viewed from a specific time slot. FIG. 3 is a time chart when the relationship between the input signal A at the input terminal and the output signal at the output terminal of the time division multiplex integration circuit of FIG. 1 is viewed on the time axis. 101 ... Timing output circuit 102 ... Latch circuit, 103 ... Computing unit 104, 105 ... NAND gate 106, 107, 109 ... AND gate 108, 110 ... OR gate 111, 112, 113 ... Buffer 114 ... … Address generation circuit 115 …… Memory, 116 …… Synchronization circuit 117 …… Input terminal, 118 …… Output terminal

Claims (1)

[Claims] 1. A synchronizing circuit for synchronizing input signals input in a time division multiplexed manner, an address generating circuit for generating an address corresponding to a time slot of the input signal, and setting while the input signal is active. The specified number of bits continues to be added in that time slot, and after reaching the set maximum value, that value is held as long as the input signal is active, and when the input signal becomes inactive, that value is held until the set minimum value is reached. An arithmetic circuit that continues to subtract in a slot, a circuit that activates an output signal until it reaches a maximum value after being added, and a subtraction becomes a minimum value; And a memory circuit for storing the arithmetic result from the arithmetic circuit in order to write the arithmetic result from the arithmetic circuit to the memory circuit in a stable manner. A latch circuit that holds the previous value and a circuit that integrates the calculation result from the calculation circuit on the storage circuit and outputs the result in time division multiplex or at an arbitrarily designated timing. A digital time division multiplex integrator circuit characterized in that