JPH0720334B2 - Circuit breaker - Google Patents
Circuit breakerInfo
- Publication number
- JPH0720334B2 JPH0720334B2 JP63224418A JP22441888A JPH0720334B2 JP H0720334 B2 JPH0720334 B2 JP H0720334B2 JP 63224418 A JP63224418 A JP 63224418A JP 22441888 A JP22441888 A JP 22441888A JP H0720334 B2 JPH0720334 B2 JP H0720334B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- trip
- long
- time
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Emergency Protection Circuit Devices (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] この発明は、回路しゃ断器、特に改良した長限時引外し
回路を備える電子式回路しゃ断器に関するものである。Description: TECHNICAL FIELD The present invention relates to a circuit breaker, and more particularly to an electronic circuit breaker having an improved long-time trip circuit.
[従来の技術] 第3図は周知の電子式回路しゃ断器の一例を示すブロッ
ク図であり、図において1は交流電源例えば3相交流電
源、2はこの交流電源1によって給電される負荷例えば
モータ、3はこれら交流電源1と負荷2の間に接続され
た回路しゃ断器である。この回路しゃ断器3は、開閉機
構部4を介して交流電源1に接続される3相導体5a,5b,
5cから成る主回路5と、この主回路5の各相導体5a,5b,
5cにそれぞれ接続された変流器CTa,CTb,CTcと、これら
変流器の2次側に接続された整流回路6と、この整流回
路6の出力側に個別に接続さた最大相選択兼ピーク値変
換回路7および最大相選択兼実効値変換回路8と、最大
相選択兼ピーク値変換回路7の出力側に個別に接続され
た瞬時引外し回路9および短限時引外し回路10と、最大
相選択兼実効値変換回路8の出力側に接続された長限時
引外し回路11と、これら瞬時引外し回路9、短限時引外
し回路10および長限時引外し回路11の出力側に接続され
たトリガ回路12と、このトリガ回路12を介して整流回路
6の両端間に接続される引外しコイル13と、長限時引外
し回路11に接続された過電流表示用LDE14とを備えてい
る。なお、上述した回路7〜11は専用ICで作られる。[Prior Art] FIG. 3 is a block diagram showing an example of a well-known electronic circuit breaker. In the figure, 1 is an AC power supply, for example, a three-phase AC power supply, and 2 is a load fed by the AC power supply 1, for example, a motor. Reference numeral 3 is a circuit breaker connected between the AC power supply 1 and the load 2. The circuit breaker 3 includes three-phase conductors 5a, 5b, which are connected to the AC power source 1 via the opening / closing mechanism section 4.
The main circuit 5 composed of 5c and the phase conductors 5a, 5b,
The current transformers CTa, CTb, and CTc respectively connected to 5c, the rectifier circuit 6 connected to the secondary side of these current transformers, and the maximum phase selection and individually connected to the output side of the rectifier circuit 6 The peak value conversion circuit 7 and the maximum phase selection / effective value conversion circuit 8, the instantaneous trip circuit 9 and the short time delay trip circuit 10 individually connected to the output side of the maximum phase selection / peak value conversion circuit 7, and the maximum The long time delay trip circuit 11 connected to the output side of the phase selection and effective value conversion circuit 8 and the output side of the instantaneous time trip circuit 9, short time delay trip circuit 10 and long time trip circuit 11 were connected. It is provided with a trigger circuit 12, a trip coil 13 connected across the rectifier circuit 6 via the trigger circuit 12, and an overcurrent display LDE 14 connected to the long-time trip circuit 11. The circuits 7 to 11 described above are made of dedicated ICs.
第4図は、第3図に示した回路しゃ断器3の過電流引外
し特性を示す曲線図である。FIG. 4 is a curve diagram showing an overcurrent trip characteristic of the circuit breaker 3 shown in FIG.
回路しゃ断器3は上述したように構成されており、その
動作を第3図および第4図について説明する。今、回路
しゃ断器3の開閉機構部4が閉じており、すなわち回路
しゃ断器3が引外されておらず、交流電源1から主回路
5を通して負荷2へ電流が流れているとしょう。変流器
CTa,CTb,CTcは、その2次側に主回路電流に比例する2
次電流を流す。整流回路6は、3相各相の交流2次電流
を整流する。最大相選択兼ピーク値変換回路7は、整流
回路6からの3相各相の整流信号のうち最大相の整流信
号を選択しかつこれをピーク値変換する。同様に、最大
相選択兼実効値変換回路8は、最大相の整流信号を選択
しかつこれを実効値変換する。ピーク値変換された直流
信号は第4図の過電流引外し特性のうち瞬時引外し特性
INST、短限時引外し特性STDを有するそれぞれ瞬時引外
し回路9、短限時引外し回路10に供給され、そして実効
値変換された直流信号は長限時引外し特性LTDを有する
長限時引外し回路11に供給される。主回路電流が定格電
流の例えば100%を超えると、長限時引外し回路11は実
効値変換された直流信号の値例えば定格電流の100%〜1
000%に応じて第4図に示す所定の時間後に出力を出し
てトリガ回路12をONさせると共に過電流表示用LED14を
点灯させる。トリガ回路12がONすると、引外しコイル13
は整流回路6の整流出力によって励磁され、開閉機構部
4を開いて主回路電流をしや断させる。同様に、主回路
電流が大きくなって定格電流の例えば1000%,1700%を
超えると、それぞれ短限時引外し回路10、瞬時引外し回
路9が出力を出し、主回路電流をしゃ断させる。The circuit breaker 3 is configured as described above, and its operation will be described with reference to FIGS. 3 and 4. Now, let us say that the switching mechanism section 4 of the circuit breaker 3 is closed, that is, the circuit breaker 3 is not tripped, and current is flowing from the AC power supply 1 to the load 2 through the main circuit 5. Current transformer
CTa, CTb, CTc are proportional to the main circuit current on the secondary side.
Apply the next current. The rectifier circuit 6 rectifies the alternating secondary current of each of the three phases. The maximum phase selection / peak value conversion circuit 7 selects the maximum phase rectified signal from the rectified signals of each of the three phases from the rectifier circuit 6 and performs peak value conversion thereof. Similarly, the maximum phase selection / effective value conversion circuit 8 selects the maximum phase rectified signal and converts it into an effective value. The DC signal with the converted peak value is the instantaneous trip characteristic of the overcurrent trip characteristic in Fig. 4.
INST and short time delay trip circuit 9 having short time delay trip characteristics STD, respectively, are supplied to the short time delay trip circuit 10, and the DC signals whose effective values have been converted are long time time trip circuit 11 having long time delay trip characteristics LTD. Is supplied to. When the main circuit current exceeds, for example, 100% of the rated current, the long time delay trip circuit 11 causes the value of the DC signal converted into an effective value, for example, 100% to 1% of the rated current.
Depending on 000%, an output is output after a predetermined time shown in FIG. 4, the trigger circuit 12 is turned on, and the overcurrent display LED 14 is turned on. When the trigger circuit 12 turns on, the trip coil 13
Is excited by the rectified output of the rectifying circuit 6 to open the opening / closing mechanism section 4 to cut or cut off the main circuit current. Similarly, when the main circuit current increases and exceeds, for example, 1000% and 1700% of the rated current, the short-timed trip circuit 10 and the instantaneous trip circuit 9 respectively output to cut off the main circuit current.
第5図は、第3図の回路しゃ断器3に使用される従来の
長限時引外し回路11を一部ブロック図で示す回路図であ
る。この長限時引外し回路11は、一方の入力端子−が最
大相選択兼実効値変換回路8の出力側に接続されかつ他
方の入力端子+が例えば定格電流100%に相当する基準
電圧を設定する第1基準電圧設定回路111に接続された
長限時引外しピックアップ用の第1比較器112と、最大
相選択兼実効値変換回路8からの実効値電圧を定電流に
変換する電圧−電流変換回路113と、コレクタがこの電
圧−電流変換回路113の出力側に接続され、エミッタが
接続されかつベースが第1比較器112の出力端子に接続
されたスイッチング・トランジスタ114と、このスイッ
チング・トランジスタ114のコレクタ−エミッタ回路と
並列にかつ電圧−電流変換回路113の出力側と接地の間
で互いに直列に接続された逆流防止用ダイオード115お
よび長限時引外し用コンデンサ116と、このコンデンサ1
16と並列に接続されてその熱時定数に合わせた大抵抗値
の抵抗器117と、一方の入力端子−がダイオード115,コ
ンデンサ116,抵抗器117の接続点に接続されかつ他方の
入力端子+が長限時引外し動作時間に相当する基準電圧
を設定する第2基準電圧設定回路118に接続された長限
時引外し信号発生用の第2比較器119とを備えている。FIG. 5 is a circuit diagram showing, in a partial block diagram, a conventional long-time trip circuit 11 used in the circuit breaker 3 of FIG. In this long time delay trip circuit 11, one input terminal − is connected to the output side of the maximum phase selection / effective value conversion circuit 8 and the other input terminal + sets a reference voltage corresponding to, for example, a rated current of 100%. A first comparator 112 for a long time delay trip pickup connected to a first reference voltage setting circuit 111, and a voltage-current conversion circuit for converting the effective value voltage from the maximum phase selection / effective value conversion circuit 8 into a constant current. 113, a switching transistor 114 whose collector is connected to the output side of this voltage-current conversion circuit 113, whose emitter is connected and whose base is connected to the output terminal of the first comparator 112, and of this switching transistor 114. A backflow prevention diode 115 and a long-time trip capacitor 116, which are connected in parallel with the collector-emitter circuit and in series with each other between the output side of the voltage-current conversion circuit 113 and the ground, and this capacitor. Capacitors 1
A resistor 117 having a large resistance value that is connected in parallel with 16 and has a thermal time constant, and one input terminal − of which is connected to the connection point of the diode 115, the capacitor 116, and the resistor 117 and the other input terminal + Includes a second comparator 119 for generating a long time delay trip signal, which is connected to a second reference voltage setting circuit 118 for setting a reference voltage corresponding to the long time delay trip operation time.
このように構成された長限時引外し回路11において、実
効値電圧の方が第1基準電圧設定回路111の基準電圧よ
りも低い間は、第1比較器112の出力レベルが高いの
で、スイッチング・トランジスタ114はターン・オンさ
れ、従ってコンデンサ116は短絡されて充電されず、そ
のため長限時引外し回路11の出力端子120から外部へ引
外し信号が供給されない。しかしながら、実効値電圧が
上述の基準電圧を超えると、第1比較器112の出力レベ
ルが低くなってスイッチング・トランジスタ114はター
ン・オフされる。そうすると、今度は、コンデンサ116
がダイオード115を通して電圧−電流変換回路113からの
定電流で徐々に充電され、その充電々圧が第2基準電圧
設定回路118の基準電圧を超えると、第2比較器119は出
力端子120から第3図のトリガ回路12およびLED14へ引外
し信号を供給する。これと同時に、コンデンサ116は抵
抗器117を通して放電するが、その放電定数が極めて長
いので、完全に放電しきらないうちに、再び充電される
事態が生じる。In the long time delay trip circuit 11 configured as above, the output level of the first comparator 112 is high while the effective value voltage is lower than the reference voltage of the first reference voltage setting circuit 111, so that switching Transistor 114 is turned on and thus capacitor 116 is shorted and not charged, so that no trip signal is provided externally from output terminal 120 of long time trip circuit 11. However, when the RMS voltage exceeds the reference voltage described above, the output level of the first comparator 112 becomes low and the switching transistor 114 is turned off. Then, the capacitor 116
Is gradually charged by the constant current from the voltage-current conversion circuit 113 through the diode 115, and when the charging voltage exceeds the reference voltage of the second reference voltage setting circuit 118, the second comparator 119 outputs the first voltage from the output terminal 120. A trip signal is supplied to the trigger circuit 12 and the LED 14 shown in FIG. At the same time, the capacitor 116 is discharged through the resistor 117, but its discharge constant is so long that it may be charged again before it is completely discharged.
[発明が解決しょうとする課題] 上述した従来の長限時引外し回路では、コンデンサの放
電時定数が極めて長いので、長限時引外し試験を何回
も、何回も続けて行うと、コンデンサが完全に放電しき
らないうちに再び充電されて電荷が貯まり、時間誤差が
生じてしまうという課題があった。[Problems to be Solved by the Invention] In the above-described conventional long-time-delay trip circuit, the discharge time constant of the capacitor is extremely long. Therefore, if the long-time trip test is continuously performed many times, the capacitor becomes There was a problem in that a charge was accumulated and charges were accumulated before the discharge was completed, resulting in a time error.
そこで、この発明は、このよう課題を解決するためにな
されたもので長限時引外し試験を続行しても時間誤差を
生じない改良した長限時引外し回路を備える回路しゃ断
器を得ることを目的とする。Therefore, the present invention has been made in order to solve the above problems, and an object thereof is to obtain a circuit breaker having an improved long-duration trip circuit that does not cause a time error even if a long-duration trip test is continued. And
[課題を解決するための手段] この発明に係る回路しゃ断器は、長限時引外し用コンデ
ンサと並列にコレクタ−エミッタ回路が接続されたトラ
ンジスタを有する改良した長限時引外し回路を設けたも
のである。[Means for Solving the Problems] A circuit breaker according to the present invention is provided with an improved long-time trip circuit having a transistor having a collector-emitter circuit connected in parallel with a long-time trip capacitor. is there.
[作用] この発明では、長限時引外し回路が引外し信号を発生す
ると同時に、この引外し信号がトランジスタをターンオ
ンさせるので、このトランジスタと並列に接続されたコ
ンデンサの充電々荷はすぐに放電される。[Operation] In the present invention, since the long-timed trip circuit generates the trip signal and at the same time the trip signal turns on the transistor, the charge load of the capacitor connected in parallel with the transistor is immediately discharged. It
[実施例] 第1図はこの発明に使用される長限時引外し回路を一部
ブロック図で示す回路図である。図において、111〜120
は第5図に示したものと全く同じである。この発明に使
用される長限時引外し回路11Aは、第5図の長限時引外
し回路11に、コンデンサ116の放電々荷をすぐに放電さ
せるためのトランジスタ121を設けたものである。この
トランジスタ121は、そのコレクタ−エミッタ回路がコ
ンデンサ116と並列に接続されかつそのベースが駆動回
路122を介して第2比較器119の出力側すなわち出力端子
120に接続されている。[Embodiment] FIG. 1 is a circuit diagram showing a partial block diagram of a long time delay trip circuit used in the present invention. In the figure, 111 to 120
Is exactly the same as that shown in FIG. The long-time trip circuit 11A used in the present invention is the long-time trip circuit 11 of FIG. 5 provided with a transistor 121 for immediately discharging the discharge load of the capacitor 116. This transistor 121 has its collector-emitter circuit connected in parallel with the capacitor 116 and its base via the drive circuit 122 at the output side of the second comparator 119, that is, the output terminal.
Connected to 120.
このように構成された長限時引外し回路11Aにおいて
は、第2比例器119が引外し信号を出力すると同時に、
この引外し信号が駆動回路122へ供給され、その結果こ
の駆動回路122からトランジスタ121のベースへ駆動信号
が供給されてトランジスタ121をターンオンするので、
コンデンサ116の電荷は放電され、時間誤差を生じるこ
となく、すぐに長限時引外し試験を行える。In the long-time delay trip circuit 11A configured as described above, at the same time that the second proportional circuit 119 outputs the trip signal,
The trip signal is supplied to the drive circuit 122, and as a result, the drive signal is supplied from the drive circuit 122 to the base of the transistor 121 to turn on the transistor 121.
The charge of the capacitor 116 is discharged, and the long-timed trip test can be immediately performed without causing a time error.
また、第1比例器112の出力側を外部接続123によりトラ
ンジスタ121のベースに接続すると、第2図から明らか
なように主回路電流が定格電流の100%以下に減って第
1比例器112の出力レベルが高レベルに戻った場合に、
トランジスタ121がターンオンされるのでコンデンサ116
の電荷はすぐに放電され断続負荷に対する特性をすぐに
変えれる。When the output side of the first proportional circuit 112 is connected to the base of the transistor 121 by the external connection 123, the main circuit current is reduced to 100% or less of the rated current as shown in FIG. When the output level returns to high level,
Since the transistor 121 is turned on, the capacitor 116
The electric charge of is immediately discharged, and the characteristics with respect to an intermittent load can be changed immediately.
[発明の効果] 以上、詳しく説明したように、この発明は、長限時引外
しコンデンサと並列にコレクタ−エミッタ回路が接続さ
れたトランジスタを有する改良した長限時引外し回路を
備えているので、引外し信号の発生と同時にコンデンサ
が完全に放電され、時間誤差を生じることなく、再試験
をすぐに行えるという効果を奏する。EFFECTS OF THE INVENTION As described above in detail, since the present invention includes the improved long-time trip circuit having the transistor in which the collector-emitter circuit is connected in parallel with the long-time trip capacitor, The capacitor is completely discharged at the same time as the generation of the disconnection signal, and the retest can be performed immediately without causing a time error.
第1図はこの発明に使用される長限時引外し回路を一部
ブロック図で示す回路図、第2図は第1図でに示した長
限時引外し回路の動作説明用波形図、第3図は周知の電
子式回路しゃ断器の一例を示すブロック図、第4図は第
3図に示した回路しや断器の過電流引外し特性を示す曲
線図、そして第5図は従来の長限時引外し回路を一部ブ
ロック図で示す回路図である。 図において、1は交流電源、2は負荷、3は回路しゃ断
器、11Aは長限時引外し回路、116は長限時引外し用コン
デンサ、121はトランジスタ、122は駆動回路である。 なお、各図中、同一符号は同一又は相当部分を示す。FIG. 1 is a circuit diagram showing a partial block diagram of a long time delay trip circuit used in the present invention, FIG. 2 is a waveform diagram for explaining the operation of the long time delay trip circuit shown in FIG. 1, and FIG. FIG. 4 is a block diagram showing an example of a known electronic circuit breaker, FIG. 4 is a curve diagram showing the overcurrent trip characteristics of the circuit breaker and circuit breaker shown in FIG. 3, and FIG. It is a circuit diagram which shows a part of block diagram of a time delay trip circuit. In the figure, 1 is an AC power supply, 2 is a load, 3 is a circuit breaker, 11A is a long-time trip circuit, 116 is a long-time trip capacitor, 121 is a transistor, and 122 is a drive circuit. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
電流を検出して前記主回路をしゃ断させる長限時引外し
回路を備えた回路しゃ断器において、前記長限時引外し
回路中の長限時引外し用コンデンサと並列にコレクタ−
エミッタ回路が接続されたトランジスタを有し、このト
ランジスタを前記長限時引外し回路から出力される引外
し信号で駆動するようにしたことを特徴とする回路しゃ
断器。1. A circuit breaker having a long-time trip circuit for detecting an overcurrent flowing in a main circuit between an AC power supply and a load to shut off the main circuit. Collector in parallel with long time delay trip capacitor
A circuit breaker having a transistor to which an emitter circuit is connected, the transistor being driven by a trip signal output from the long-time trip circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63224418A JPH0720334B2 (en) | 1988-09-09 | 1988-09-09 | Circuit breaker |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63224418A JPH0720334B2 (en) | 1988-09-09 | 1988-09-09 | Circuit breaker |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0274121A JPH0274121A (en) | 1990-03-14 |
| JPH0720334B2 true JPH0720334B2 (en) | 1995-03-06 |
Family
ID=16813466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63224418A Expired - Lifetime JPH0720334B2 (en) | 1988-09-09 | 1988-09-09 | Circuit breaker |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0720334B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001169457A (en) * | 1999-12-02 | 2001-06-22 | Mitsubishi Electric Corp | Electronic circuit breaker |
-
1988
- 1988-09-09 JP JP63224418A patent/JPH0720334B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0274121A (en) | 1990-03-14 |
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