JPH0789703B2 - Circuit breaker - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a circuit breaker and a circuit breaker, and more particularly to an electronic circuit breaker and a circuit breaker having an improved peak value conversion holding circuit.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a well-known electronic circuit breaker and circuit breaker. In the figure, 1 is an AC power source, for example, a three-phase AC power source, 2 is a load fed by the AC power source 1, for example, a motor, Reference numeral 3 is a circuit breaker or a breaker connected between the AC power source 1 and the load 2. This circuit breaker 3 is a three-phase conductor 5a, 5b, which is connected to the light current power supply 1 via the opening / closing mechanism 4.
The main circuit 5 composed of 5c and the phase conductors 5a, 5b,
The converters CTa, CTb, CTc respectively connected to 5c, the rectifier circuit 6 connected to the secondary side of these current transformers, and the maximum phase selection and peak individually connected to the output side of this rectifier circuit 6 The value conversion circuit 7 and the maximum phase selection / effective value conversion circuit 8, the instantaneous trip circuit 9 and the short trip circuit 10 individually connected to the output side of the maximum phase selection / peak value conversion circuit 7, and the maximum phase A long time delay trip circuit 11 connected to the output side of the selection and effective value conversion circuit 8, and a trigger connected to the output side of these instantaneous time trip circuit 9, short time delay trip circuit 10 and long time trip circuit 11. A circuit 12, a trip coil 13 connected between both ends of the rectifier circuit 6 via the trigger circuit 12, and an overcurrent display LED 14 connected to the long-time trip circuit 11 are provided. The circuits 7 to 11 described above are made of dedicated ICs.

FIG. 4 is a curve diagram showing the overcurrent trip characteristic of the circuit breaker and the circuit breaker 3 shown in FIG.

The circuit breaker and the circuit breaker 3 are configured as described above, and the operation thereof will be described with reference to FIGS. 3 and 4. Now, the switching mechanism part 4 of the circuit breaker 3 is closed, that is, the circuit breaker 3 is not tripped, and current is flowing from the AC power source 1 to the load 2 through the main circuit 5. Try. Current transformer
CTa, CTb, CTc are proportional to the main circuit current on the secondary side.
Apply the next current. The rectifier circuit 6 rectifies the alternating secondary current of each of the three phases. The maximum phase selection / peak value conversion circuit 7 selects the maximum phase rectified signal from the rectified signals of each of the three phases from the rectifier circuit 6 and performs peak value conversion thereof. Similarly, the maximum phase selection / effective value conversion circuit 8 selects the maximum phase rectified signal and converts it into an effective value. The DC signal with the converted peak value is the instantaneous trip characteristic of the overcurrent trip characteristic in Fig. 4.
INST and short-duration trip circuit 9 each having a short-duration trip characteristic STD are supplied to an instantaneous trip circuit 9 and a short-duration trip circuit 10, respectively, and the rms-value converted DC signals are long-duration trip circuit 11 having a long-duration trip characteristic LTD. Is supplied to. When the main circuit current exceeds, for example, 100% of the rated current, the long time delay trip circuit 11 causes the value of the DC signal converted into an effective value, for example, 100% to 1% of the rated current.
Depending on 000%, an output is output after a predetermined time shown in FIG. 4 to turn on the trigger circuit 12 and turn on the LED 14 for overcurrent display. When the trigger circuit 12 turns on, the trip coil 13
Is excited by the rectified output of the rectifier circuit 6 to open the opening / closing mechanism section 4 to cut off the main circuit current. Similarly, when the main circuit current becomes large and exceeds, for example, 1000% or 1700% of the rated current, the short time delay trip circuit 10 and the instantaneous trip circuit 9 respectively output to turn off the main circuit current.

FIG. 5 is a circuit diagram showing a conventional peak value conversion holding circuit used as a part of the maximum phase selection / peak value conversion circuit in the circuit shown in FIG. 3 and the circuit breaker. FIG. 6 is a curve diagram showing the input / output characteristics of such a peak value conversion holding circuit.

As shown in FIG. 5, the conventional peak value conversion holding circuit 7A
Is an operational amplifier OA having one input terminal + connected to the output side of the rectifier circuit 6, and a backflow blocking diode D connected between the output terminal of the operational amplifier OA and the other input terminal −. A resistor R1 having a resistance value of 100 kΩ, which is connected between the cathode of the diode D and the ground, and this resistor
It is connected in parallel with R1 and its non-grounded end is connected to the instantaneous trip circuit 9 and the short time delay trip circuit 10, for example, 2.
Peak value conversion holding capacitor C1 having a capacitance of 2 μF
It consists of and.

When the peak value conversion holding circuit 7A configured as described above receives the input, that is, the signal a shown in FIG. 6 from the rectifying circuit 6,
The peak value conversion holding circuit 7A produces an output, that is, a peak value conversion holding signal b.

[Problems to be Solved by the Invention]

In the conventional peak value conversion holding circuit 7A described above, the followability when the input signal increases is good, but the followability when the input signal decreases has a time constant of 100 KΩ (R1) × 2.2 μF (C1) = 220
There was a problem that it was long and bad with msec.

Therefore, the present invention has been made to solve such a problem, and when the main circuit current and thus the above-mentioned input signal decreases, the output, that is, the peak value conversion hold signal immediately follows and decreases so as to return. It is an object of the present invention to obtain a circuit and a breaker equipped with an improved peak value conversion holding circuit that shortens the possible time.

[Means for solving the scale]

In the circuit or breaker according to the present invention, the peak value conversion holding capacitor is connected in parallel, and the sudden decrease tracking capacitor and the first sudden decrease tracking capacitor are connected in series.
A first means composed of a transistor, a second means composed of a second transistor and a resistor connected in parallel with the peak value conversion holding capacitor, and a resistor connected in series with the second transistor; A third means comprising a plurality of resistors connected in parallel with the capacitor;
Connected to the output side of the first means and the third means,
A sudden decrease tracking circuit including fourth means for turning on the second transistor is provided in the peak value conversion holding circuit.

[Work]

In the present invention, it is noted that when the input signal decreases, the charge flow from the first transistor to the rapid decrease tracking capacitor disappears for a moment, this is detected by the comparator, and the second transistor is turned on. Since the electric charge of the peak value conversion holding capacitor is rapidly discharged through the second transistor so that the recoverable time is shortened, the peak value conversion holding signal immediately follows the decrease of the input signal.

[Embodiment] FIG. 1 is a circuit diagram showing a peak value conversion holding circuit used in the present invention, and FIG. 2 is a waveform diagram for explaining the operation of such a peak value conversion holding circuit.

As shown in FIG. 1, the peak value conversion holding circuit 7B used in the present invention includes an operational amplifier OA, a reverse current blocking diode D and a peak value conversion holding capacitor which are the same as those in the conventional example.
In addition to C1, a sudden decrease tracking circuit that shortens the recoverable time of the peak value conversion holding capacitor C1 so that the peak value conversion holding signal immediately follows and decreases when the input signal decreases.
Contains the RRF. This rapid decrease follow-up circuit RRF is composed of series-connected resistors R2 and R3 of 100 KΩ, which is an alternative to the conventional resistor R1 of 100 KΩ, a first transistor T1 to which an emitter base circuit is connected in parallel with a diode D, and a first transistor T1. A capacitor C2 for rapid decrease tracking connected between the collector of the transistor T1 and ground, a resistor R4 connected in parallel with the capacitor C2 for rapid decrease tracking, and one input terminal + connected in series to the connection point of resistors R2 and R3. And the other input terminal is connected to the non-grounded end of the capacitor C2 for rapid decrease tracking C2 and its parallel resistor R4, and the collector-emitter circuit is connected to the peak value conversion holding capacitor via the collector resistor R5.
It is composed of a second transistor T2 which is connected in parallel with C1 and whose base is connected to the output side of the comparator CO. It should be noted that the rapid decrease tracking capacitor C2 and the first transistor T1
Form the first means, the second transistor T2 and the collector resistor R5 form the second means, and the series connection resistors R2 and R3
Forms the third means, and the comparator CO becomes the fourth means.

When the input signal a shown in FIG. 2 is supplied from the rectifier circuit 6 to the peak value conversion / holding circuit 7B configured as described above, the input signal a is amplified by the operational amplifier OA, and then the peak value is passed through the diode D. The conversion holding capacitor C1 is discharged to generate the peak value conversion holding signal b. For a short time during the input signal period, the first transistor T1 is turned on to flow a charging current c into the rapid decrease tracking capacitor C2, whereby the rapid decrease tracking capacitor C2 repeats charging / discharging d to the negative input terminal of the comparator CO. The input d is supplied, and the series connection resistors R2 and R3 supply the input e having a value proportional to the peak value conversion holding signal b to the + input terminal of the comparator CO. Input d is input e
, The comparator CO does not produce an output, and thus the second transistor T2 remains turned off. Therefore, the peak value conversion holding capacitor C1 is discharged through the 100 KΩ series connection resistors R2 and R3 as in the conventional example.

However, when the input signal a is suddenly decreased, the first transistor T1 is not reverse-biased by the peak value conversion holding signal b, so that the first transistor T1 does not turn on and accordingly does not flow a charging stream for a moment. Therefore, the rapid decrease tracking capacitor C2 continues to be discharged through the parallel resistor R4, and eventually the input d becomes smaller than the input e. Then, the comparator CO outputs the output f to turn off the second transistor T2, and the peak value conversion holding capacitor C1 is discharged rapidly through the collector resistor R5 and the second transistor T2 having a small resistance value unlike the conventional example. To do.

Thus, in the present invention, when the input signal decreases,
Paying attention to the fact that the charge flow from the first transistor to the capacitor for rapid decrease disappears for a moment, this is detected by the comparator, the second transistor is turned on, and the peak value conversion holding capacitor is turned on through the turned-on second transistor. Since the electric charge is discharged rapidly and the recoverable time is shortened, the peak value conversion hold signal immediately follows the decrease of the input signal.

〔The invention's effect〕

As described above in detail, according to the present invention, there is provided a first means which is connected in parallel with the peak value conversion holding capacitor, and which includes the rapid decrease tracking capacitor and the first transistor connected in series with the rapid decrease tracking capacitor, A second means connected in parallel with the peak value conversion holding capacitor and comprising a second transistor and a resistor connected in series with the second transistor; and a second means connected in parallel with the peak value conversion holding capacitor, A third means consisting of individual resistors,
Connected to the output side of the first means and the third means,
Since the peak value conversion holding circuit is provided with the rapid decrease tracking circuit including the fourth means for turning on the second transistor, the peak value conversion holding signal immediately follows and decreases when the input signal decreases, and Thus, by shortening the recoverable time, the range in which selective cooperation can be taken is widened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a peak value conversion holding circuit used in the present invention, FIG. 2 is a waveform diagram for explaining the operation of the peak value conversion holding circuit shown in FIG. 1, and FIG. 3 is a well-known electronic type. A block diagram showing an example of a circuit breaker and a circuit breaker, FIG. 4 is a curve diagram showing an overcurrent trip characteristic of the circuit breaker and circuit breaker shown in FIG. 3, and FIG. 5 is a conventional peak value conversion holding circuit. Circuit diagram,
FIG. 6 is a waveform diagram for explaining the operation of the conventional circuit. In the figure, 1 is an AC power supply, 2 is a load, 3 is a circuit breaker, 7B is a peak value conversion holding circuit, 9 is an instantaneous trip circuit,
10 is a short time delay trip circuit, C1 is a capacitor for holding peak value conversion, C2 is a capacitor for following a rapid decrease, T1 is a first transistor, T2 is a second transistor, R2 and R3 are series connection resistors, R5
Is a collector resistance and CO is a comparator. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A peak value conversion holding circuit for operating a trip circuit that detects an overcurrent flowing in a main circuit between an AC power supply and a load and shuts off the main circuit. A circuit breaker having an operational amplifier connected to a main circuit and a diode and a peak value conversion holding capacitor connected in series on the output side of the operational amplifier, having a control current path connected in parallel with the diode. First transistor and this first
First means, which is connected in series with the main current path of the transistor and which is connected in parallel with each other, is composed of a rapid-decreasing follow-up capacitor and a resistor, and is connected in parallel with the peak value conversion holding capacitor. A second means formed of a resistor connected in series with two transistors, a third means formed of a plurality of resistors connected in parallel with the peak value conversion holding capacitor, and the first means and the third means. Connected to the element connection point of, and when the charging / discharging current of the rapid decrease tracking capacitor becomes smaller than a value proportional to the holding signal of the peak value conversion holding capacitor due to a rapid decrease of the input signal, the second transistor is turned on. A circuit breaker, characterized in that it is provided with a sudden decrease follow-up circuit including four means.