JPH0721746B2 - Data memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data memory device for selectively thinning converted data output from an A / D converter and storing the converted data in a memory. The present invention relates to improvement of point data acquisition.

(Prior Art) A type of waveform observation device, in which an analog measurement signal is added to an A / D converter, converted into a digital signal, and then temporarily stored in a memory, and the data stored in this memory is read at a desired time. Some are configured to be displayed on the display unit.

By the way, in observing an analog signal having a relatively low frequency in such a device, in order to enable measurement for a relatively long time with a limited memory capacity, A /
The conversion data output from the D converter is selectively thinned and stored in a memory.

FIG. 5 is a timing chart showing an example of a conventional data storage operation in such a memory.

In FIG. 5, (a) is analog data AD related to the analog measurement signal, and these analog data AD are digital data as shown in (c) according to the conversion clock CC of the A / D converter shown in (b). Converted to DD. In this example, there is a time difference of four conversion clocks between the input data AD and the output data DD of the A / D converter.
(D) is a sample clock SC for selectively thinning out the digital data DD and loading it into the memory, and its cycle is 10 times that of the conversion clock CC, and the output data DD of the A / D converter is It can be thinned out and taken in every 10 pieces. (E) shows the digital data DD 'fetched in the memory at the sample clock SC. In this example, 0
The 0th analog clock AD is fetched by the 1st sample clock SC and the 1st sample clock SC
The 10th analog data AD is fetched, and the 20th analog data AD is fetched by the second sample clock SC.

In this way, a plurality of data that have been selectively thinned out are stored in the memory, but when reading out these stored data and displaying the waveform, the trigger point data related to the trigger input is stored. Also store,
It is necessary to manage the time relationship with the trigger in the displayed waveform based on the stored trigger point data.

(Problems to be Solved by the Invention) Such trigger point data is taken in at the first rising edge of the sample clock after the trigger input,
If the data is captured at the first rising edge of the sample clock after the trigger input, the data before the trigger input may be captured as the trigger point data.

(F) is a trigger TG, which is added at the timing corresponding to the eighth analog data AD. (G) is the trigger point data TD, which is the rising edge of the first sample clock SC after the trigger TG is input, that is, the converted digital data DD corresponding to the 10th analog data AD at the timing corresponding to the 14th analog data AD. It has been captured. The trigger point data TD in this case corresponds to the analog data AD after the trigger TG is input, and there is no inconvenience.

(H) is also the trigger input and the 12th analog data AD
Is added at the timing corresponding to. (I) is also the trigger point data TD, but similar to (g), the trigger TG
At the rising edge of the first sample clock SC after input, that is, at the timing corresponding to the 14th analog data AD
Converted digital data DD corresponding to the 10th analog data AD is captured. However, the trigger point data TD in this case corresponds to the analog data AD before the trigger TG is input, and is not preferable as the original trigger point data TD.

The present invention focuses on such a point, and an object thereof is to provide a data memory device capable of capturing only analog data after a trigger input as trigger point data.

(Means for Solving Problems) A data memory device according to the present invention converts analog data into digital data in accordance with a conversion clock having a constant cycle, and converts the analog data into digital data n cycles after the conversion clock. Through the A / D converter that outputs data, the sample clock generation circuit that outputs the sample clock synchronized with the conversion clock, the latch that selectively captures the output data of the A / D converter according to the sample clock, and the latch The memory that stores the captured A / D converter output data, the conversion clock, the sample clock, and the trigger are input, and the trigger is delayed by n-0.5 cycles of the conversion clock from the first conversion clock after the trigger is input. After that, the trigger point data is written according to the first sample clock added after that. A trigger address latch signal generation circuit that outputs a trigger address latch signal that latches the memory address that is stored, and a memory address holding unit that holds the memory address to which the trigger point data is written according to the trigger address latch signal output from the trigger address latch signal generation circuit. And a memory address controller for changing the memory address according to the sample clock.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, reference numeral 1 is an A / D converter, which converts analog data AD into digital data DD according to a conversion clock CC with a constant cycle, and is converted n cycles after the conversion clock CC after the analog data AD is input. Output digital data DD. Reference numeral 2 is a sample clock generation circuit that outputs a sample clock SC synchronized with the conversion clock CC, 3 is a latch that selectively captures the output data DD of the A / D converter 1 according to the sample clock SC, and 4 is a latch via the latch 3. It is a memory for storing the output data DD of the A / D converter 1 that has been stored. 5 is a trigger address latch signal generation circuit,
The conversion clock CC, the sample clock SC and the trigger TG are input, and the trigger TG is delayed by n−0.5 cycles of the conversion clock CC from the first conversion clock CC after the trigger TG is input, and then added first. Trigger address latch signal that latches the memory address MA to which the trigger point data TD is written according to the sample clock SC of
Output as TL. Reference numeral 6 denotes a memory address controller, which has memory address holding means such as a register for holding a memory address to which the trigger point data TD is written according to the trigger address latch signal TL output from the trigger address latch signal generation circuit 5, and according to the sample clock SC. Change the memory address MA.

FIG. 2 is a circuit diagram showing a specific example of the trigger address latch signal generation circuit 5. 51-53 are flip-flops, 54
Is an inverter. Flip-flops 51 _{1 to} 51 _n are A / D
The number of stages corresponding to the number n of cycles of the conversion clock CC corresponding to the delay time of the input data and the output data due to the conversion processing of the converter 1 is provided, and the conversion clock CC is directly added to each clock terminal, and the first stage Flip flop 51 ₁
Data output terminals Q is applied the trigger TG in D is connected to a data terminal D of the next flip-flop 51 _2, and so the previous stage of the output terminal Q of the flip-flop is a data terminal of the subsequent flip-flop of It is continuously connected to D. The conversion clock CC is applied to the clock terminal of the flip-flop 52 via the inverter 54, and the output terminal Q of the flip-flop 51 _n is connected to the data terminal D. A sample clock SC is applied to the clock terminal of the flip-flop 53, and the output terminal Q of the flip-flop 52 is connected to the data terminal D.

In such a configuration, the first stage flip-flop 51 ₁
A trigger TG is latched by the conversion clock CC and output as a trigger TGS synchronized with the exchange clock CC from the output terminal Q of the above, and is applied to the data terminal D of the next flip-flop 51 ₂ . Trigger TGD ₁ applied from output terminal Q of flip-flop 51 _n to data terminal D of flip-flop 52
Become those n-1 cycle delay conversion clock CC for each trigger TGS output from the flip-flop 51 _1,
From the output terminal Q of the flip-flop 52 to the flip-flop
The trigger TGD ₂ applied to the data terminal D of 53 is further 1 for the conversion clock CC for the output signal of the flip-flop 51 _n.
/ It will be delayed by 2 cycles. From the output terminal Q of the flip-flop 53, the trigger TGD ₂ output from the flip-flop 52 is latched by the sample clock SC and output as a trigger address latch signal TL synchronized with the sample clock SC. Here, the trigger TGD ₂ applied from the output terminal Q of the flip-flop 52 to the data terminal D of the flip-flop 53 is the trigger TGS output from the flip-flop 51 _1.
In contrast, the replacement clock CC is delayed by n-0.5 cycles. This is because the cycle of the sample clock SC is the conversion clock CC
If equal maximum sample rate trigger address latch signal TL in case of but rises after n periods of exchange clock CC for each trigger TGS output from the flip-flop 51 _1, trigger TGD timing at that time it is outputted from the flip-flop 52 _This is to prevent malfunction due to bidding with ₂ .

The operation of the apparatus configured as described above will be described with reference to FIGS.
This will be described with reference to the timing chart in the figure.

In FIG. 3, the conversion delay time in the A / D converter 1 is four times the cycle tcc of the conversion clock CC shown in (b) (n =
4), the cycle of the sample clock SC shown in (c) is set to have a 1: 1 relationship with the cycle tcc of the conversion clock CC. As a result, the 0th analog AD shown in (a) is converted and output as the 0th digital data DD after 4tcc has elapsed, as shown in (d). On the other hand, when the trigger TG shown in (f) is input, the conversion clock CC immediately after that is input.
Trigger TGS as shown in (g) at the rising edge of
Is output, and when the time 3.5tcc has elapsed from this trigger TGS, the trigger TGD ₂ is output as shown in (h), and is shown in (i) in synchronization with the sample clock SC immediately after this trigger TGD ₂ is generated. As described above, the signal TL for latching the memory address MA to which the trigger point data is written is output. In FIG. 3, the memory address of #K is latched in the register of the memory address controller 6 by the rise of the trigger address latch signal TL, and the 0th analog data AD converted to the address #K of the memory 4 as the trigger point data is converted into 0. Th digital data DD
Will be stored.

In FIG. 4, A / D indicates that the conversion time in the converter 1 is four times the cycle tcc of the conversion clock CC shown in (b) (n =
4). The cycle of the sample clock SC shown in (c) is set to have a 10: 1 relationship with the cycle tcc of the conversion clock CC. As a result, the digital data DD ′ that is latched at the rising edge of (0) of the sample clock SC and stored in the memory 4 is obtained by converting and outputting the 0th analog data AD of 4tcc past as shown in (d). become. Here, the condition that such 0th digital data DD ′ can be used as trigger point data is that the sample clock SC that latches 0th digital data DD ′ is used.
4tcc from the point 14tcc past the start of (0)
This is the case where the trigger TG has been input up to the past time point. That is, in cases 1 and 2, the trigger TG is (f),
As shown in (j), since the 0th analog data AD is input before, the 0th analog data AD is a trigger.
It is the first sampling data after TG input. Therefore, in any case, the memory address of #K is latched in the register of the memory address controller 6 by the rising edge of the trigger address latch signal TL shown in (i) and (m), and 0 is stored as the trigger point data in the address #K of the memory 4. The 0th digital data DD obtained by converting the 9th analog data AD is stored. On the other hand, in case 3, the trigger TG is 0 as shown in (n).
Although input after the th analog data AD, the 0th analog data AD is the first sampling data after the trigger TG is input. However, since the rising edge of the trigger TGD ₂ shown in (p) is delayed from the rising edge of (0) of the sample clock SC in the vicinity thereof, it is not treated as the data before the trigger input and does not become the trigger point data. The trigger point data in this case 3 is the first digital data obtained by converting the first analog data AD input after the trigger input.
The address #K of the memory 4 which is DD 'and is latched by the rising edge of the sample clock SC (1) and latched by the rising edge of the trigger address latch signal TL.
It will be stored in +1.

With this configuration, the trigger point data can always be the first sample data after the trigger input.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a data memory device that can capture only analog data after trigger input as trigger point data, and is practically used for trigger point management in a digital oscilloscope. Has a great effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a concrete example of the trigger address latch signal generating circuit of FIG. 1, and FIGS. 3 and 4 show the operation of FIG. FIG. 5 is a timing chart for explaining, and FIG. 5 is a timing chart for explaining the operation of the conventional device. 1 ... A / D converter, 2 ... Sample clock generation circuit,
3 ... Latch, 4 ... Memory, 5 ... Trigger address signal generation circuit, 6 ... Memory address controller.

Claims (1)

[Claims] 1. An A / D converter for converting analog data into digital data according to a conversion clock having a constant cycle, and outputting the converted digital data n cycles after an exchange clock after the analog data is input, and a conversion clock. A sample clock generation circuit that outputs a sample clock that is synchronized with, a latch that selectively captures the output data of the A / D converter according to the sample clock, and the output data of the A / D converter that is captured via the latch are stored. Memory and the conversion clock, sample clock, and trigger that are input, and the trigger is delayed by n-0.5 conversion clock cycles from the first conversion clock after the trigger is input, and then the first sample clock that is added after that. Address to latch the memory address where the trigger point data is written according to It has a trigger address latch signal generation circuit that outputs as a latch signal and a memory address holding unit that holds the memory address to which the trigger point data is written according to the trigger address latch signal output from the trigger address latch signal generation circuit. A data memory device comprising: a memory address controller for changing.