JPH0721782B2 - Storage device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device that returns an error reply to a system control device, and particularly error control when an error which does not meet the error reply timing occurs in a write operation. Regarding

[Prior Art] Conventionally, in this type of storage device, when an error which does not meet the error reply timing occurs in the write operation,
The diagnostic control device reports an error to the diagnostic control device, and the diagnostic control device receives the error, determines what kind of error it is, and then stops the system. On the other hand, the storage device has implemented writing if it can be prohibited.

[Problems to be Solved by the Invention] The above-mentioned conventional storage device reports an error to the diagnostic control device in time for the error reply timing.
Hundreds of instructions work. During this time, if the address data of the error is read, the error is not detected, and there is a drawback that the data becomes garbled.

[Means for Solving the Problems] The storage device according to the present invention executes write, read, and partial write operations in response to write, read, and partial write commands from the system controller, and when an error occurs. Detects the error and returns an error reply to the system control unit, and when a serious failure error which does not meet the timing of the error reply is detected during a write or partial write operation, the An error register that holds a failure error and outputs a serious failure error, an error address holding unit that holds an address when the serious failure error is detected and outputs an error address, a read address and an error address during a read operation Error is reported regardless of the first mode and the error address when the error matches Second to report
Mode register for outputting a mode signal indicating one of the first mode and the second mode, and the address and the error sent from the system controller during a read operation. An address is compared and a match circuit that outputs a match signal when the comparison results match, and a comparator circuit that outputs a match signal when the mode register outputs a mode signal indicating the first mode Further, when the error register outputs an error report instruction signal for instructing an error report when the error register outputs a serious failure error, and when the mode register outputs a mode signal indicating the second mode, the comparator circuit The error report instruction signal when the error register outputs a serious failure error regardless of whether the error register outputs a coincidence signal or not. A gate circuit which outputs, when receiving the error report indication signal, characterized in that it has a, and sending means for sending said error reply to the system controller.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, a storage device according to an embodiment of the present invention.
Reference numeral 30 denotes a write, read, and partial write operation for the write, read, and partial write commands from the system controller 1, executes write, read, and partial write operations. It will be returned to 1.

The storage device 30 includes a main control circuit 3, an address control circuit 4, an error control circuit 5, a timing control circuit 6, a comparison circuit 7,
It has an error register 8, an AND circuit 9, a memory matrix circuit 10, a mode register 50, and an OR circuit 51.

Next, the operation of this embodiment will be described with reference to the timing chart shown in FIG.

In a normal write operation, when a request or command 11 is sent from the system controller 1, it is sent by the main control circuit 3
Then, the control signal for writing operation is sent to various circuits. The timing control circuit 6 generates the RAS, CAS, and WE timing signals 18 from the control signal 12 from the main control circuit 3 and sends them to the memory matrix circuit 10. This time,
The write data (not shown in FIG. 1) and the address 17 from the address control circuit 4 are also sent to the memory matrix circuit 10, and the address of the memory matrix circuit 10 is sent.
Write data is written to 17. If an error such as an address parity error, which is in time for the reply 15, is detected, the error reply 26 is returned from the error control circuit 5 to the system controller 1. But,
When the timing signal 18 error occurs, the error control circuit 5
If a timing error is detected in, 22
Are held in the error register 8. Further, the address in this operation is held in a register (not shown) in the error control circuit 5. The error reply 26 cannot be returned to the system controller 1 at the timing of occurrence of the serious failure error 22. Therefore, the system control device 1 determines that the writing operation is completed normally and continues the processing.

Next, when a normal read operation is executed, data is read from the address of the memory matrix circuit 10 designated by the address 17 output from the address control circuit 4, and this read data is shown in FIG. To the system controller 1 via the missing data line. At this time, the mode signal 52 output from the mode register 50 is logical “0”.
Then, if the comparison circuit 7 compares the error address 23 held during the write operation with the address 17 from the system control device 1 via the address control circuit 4, if they match,
The error reply 26 is returned to the system control device 1 via the OR circuit 51, the AND circuit 9, and the error control circuit 5. If the addresses do not match, the error reply 26 will not be returned.

Further, when the mode signal 52 becomes logic "1", whether or not the addresses match each other, if the read operation is executed with the serious failure error generated in the previous write operation, the OR circuit 51 The error reply 26 is returned to the system controller 1 via the AND circuit 9 and the error control circuit 5.

[Effects of the Invention] As described above, the present invention holds a serious failure error and an address for a serious failure error during a write or partial write operation, but does not report the error to the system controller. During a read operation, the reliability of the system can be changed by comparing the error addresses according to the value in the mode register and switching between reporting an error to the system controller if they match or reporting an error regardless of the error address. Not only is it effective, but it also has the effect of enabling dynamic diagnosis.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a storage device according to an embodiment of the present invention together with a system control device, and FIG. 2 is a timing chart for explaining the operation of the present invention. 1 ... System control device, 3 ... Main control circuit, 4 ... Address control circuit, 5 ... Error control circuit, 6 ... Timing control circuit, 7 ... Comparison circuit, 8 ... Error register, 9 ... AND circuit, 10 ... Memory matrix circuit, 11 ... Request, command, 15 ... Reply, 1
6,17,19 …… Address, 18 …… Timing signal, 22 ……
Serious failure error, 23 ... Error address, 26 ... Error reply, 30 ... Storage device, 50 ... Mode register, 51 ...
… Or circuit, 52 …… Mode signal.

Claims (1)

[Claims] 1. Writing and reading from a system controller,
And a partial write command, write, read, and partial write operations are performed, and when an error occurs, the error is detected, and an error reply is returned to the system control unit. Alternatively, during a partial write operation, when a serious fault error that is not in time for the error reply is detected, the serious fault error is held and an error register for outputting the serious fault error, and a time when the serious fault error is detected. An error address holding means for holding an address and outputting an error address, and a second mode for reporting an error regardless of the first mode and the error address for reporting an error when the read address and the error address match during a read operation. One of the first mode and the second mode for switching between modes. A mode register that outputs a mode signal indicating one of the two, a comparison circuit that compares the address sent from the system controller during the read operation with the error address, and outputs a match signal when the comparison results match. An error report indicating an error report when the comparison circuit outputs a coincidence signal and the error register outputs a serious failure error when the mode register outputs a mode signal indicating the first mode. When the instruction signal is output and the mode register outputs a mode signal indicating the second mode, the error register outputs a serious failure error regardless of whether the comparison circuit outputs a coincidence signal or not. And a gate circuit that outputs the error report instruction signal when the error report instruction signal is received. Storage apparatus characterized by comprising: a sending means for sending a line to the system control device.