JPH0721785B2 - Peripheral control device - Google Patents

Description

The present invention relates to a peripheral control device, and more particularly to a peripheral control device sharing controlled devices with each other.

[Conventional technology]

In an information processing system, a system is often configured by using a plurality of peripheral control devices in order to improve the performance and reliability of the peripheral device subsystem.

Conventionally, for this type of peripheral control device, a method of performing load distribution processing only by software and a data transfer path between a plurality of peripheral control devices sharing a controlled device to distribute the load only between the peripheral control devices are provided. There was a way to do.

[Problems to be solved by the invention]

In the conventional load balancing method using only software, when a plurality of host devices without communication means are connected to each peripheral control device, the software of each host device can accurately determine the load status of each peripheral control device. I couldn't know. Further, in the peripheral control device having a data buffer, when data transfer or the like is performed with the controlled device asynchronously with the data transfer with the host device, the software cannot accurately know the load condition.

Further, the conventional method of providing the data transfer path between the peripheral control devices has a problem that the amount of hardware of the peripheral control devices increases.

The present invention is intended to solve such a problem of the conventional one, and it is possible to appropriately perform load distribution even when connected to a plurality of host devices or when a large amount of processing is performed asynchronously with the host devices. Provided is a peripheral control device capable of realizing processing with a small amount of hardware.

[Means for solving problems]

According to the present invention, in a peripheral control device that shares a controlled device with another peripheral control device and is connected to the same higher-level device, means for storing the operation status, and the operation status to the other peripheral control device. A means for notifying each other and the stored operating condition and the operating condition notified from the other peripheral control device should be compared, and which peripheral control device should perform new processing instructed by the host device. And a means for determining whether or not a new process should be processed by the other peripheral control device, the higher device is requested to retry via the other peripheral control device. And a peripheral control device.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a magnetic tape subsystem which is an embodiment of the present invention.

A magnetic tape control device (hereinafter abbreviated as MTC) 1 includes a host connection unit (hereinafter CHA) 10 and a device connection unit (hereinafter MTA) 11
Via a host machine 2 and a plurality of streamer type magnetic tape units (hereinafter referred to as MTUs) 3, respectively. Each M
TU3 is connected so that it is shared by two MTC1s.

The data buffer 12 of MTC1 is divided corresponding to each MTU3, and C
Temporarily stores the data transferred between HA10 and MTA11,
Enables asynchronous operation of CHA10 and MTA11. The microprocessor 13 controls each part of the MTC 1. The control information storage unit 14 stores various information including control information of the microprocessor 13. The load information storage unit 15 stores the status of data transfer in the CHA 10 or MTA 11 (the number of data transfers or the number of data transfer waits) and the usage status of the data buffer 12.
The data of the load information storage unit 15 is the data of the other system to which it is connected.
The MTC1 microprocessor 13 can also read from each other. After the processing requested by the host machine 2 is completed, the status storage unit 16 temporarily stores the status edited by the microprocessor 13 as its execution result and sends it to the host machine 2 via the CHA 10.

FIG. 2 shows the information stored in the load information storage unit 15 in FIG. The number of in-process instructions 101 indicates the number of instructions being executed from the host machine 2 to the MTU 3 in each MTC.
The buffer use information 102 is assigned with a bit corresponding to each MTU 3, and indicates whether or not the buffer is used in the processing of each MTU 3.

Next, the operation of the apparatus of this embodiment will be described with reference to the drawings.

The microprocessor 13 shown in FIG. 1 controls each part in the MTC 1 by a micro program, and particularly the host machine 2
In response to a READ command, a WRITE command, etc., the CHA 10, MTA 11, and data buffer 12 are controlled to read data from the MTU 13 and write data to the MTU 3.

When the microprocessor 13 receives an instruction from the host machine 2 via the CHA 10, it decodes the instruction and determines whether it can be immediately executed in the MTC 1 without accessing the MTU 3. MT
If it can be executed immediately in C1, this instruction is executed, stored in the status storage unit 16 showing the result, and then reported via CHA 10, or the next instruction is requested.

The command sent from the host machine 2 to the ATC MTC1 is the first MT
In the case of an instruction to access U3, the microprocessor 13 reads out respective load information from the load information storage unit 15 of its own system (A system) and the load information storage unit 15 of another system (B system) and compares them. As a result of the comparison, when it is judged that it is appropriate to process the instruction in the own system, the number 101 of the instructions being processed in the load information storage unit 15 in the own system shown in FIG. 2 is incremented by one. Next, when the buffer is used in the processing of the instruction, MTU3 is also set in the data buffer use information 102 of the load information storage unit 15 of the own system.
Set the in-use bit of the data buffer, which is assigned one bit for each.

When the instruction received from the host machine 2 is a WRITE instruction, the microprocessor instructs the CHA 10 and the data buffer 12 to start data transfer. The data sent from the host machine 2 is sequentially stored in the data buffer 12. When the amount of data sent is less than the standard, the operation for MTU3 does not start,
The end report or the next command request is issued to the host machine 2. At this time, the load information storage unit 15 of its own system is decremented by the number of in-process instructions 101 shown in FIG.

Next, when a WRITE command is issued again from the host machine 2 to the same MTU3, since the buffer busy bit 102 of the load information storage unit 15 is set, it is decided to process the command by its own system and transfer the data. Start and store in data buffer 12. When the total amount of data in the data buffer 12 with the previously stored data block exceeds the reference value, the microprocessor 13 instructs the MTA 11 to send W to the MTU 3 concerned.
Sends RITE instruction and instructs data transfer. When the data transfer with the data buffer 12 of the host machine 2 is completed, the microprocessor 13 carries out the end processing in the same manner as the previous WRITE instruction. At this time, the data buffer 12 and the MT
WRITE processing is being executed between U3.

Next, the command issued from the host machine 2 is the WRITE command for the second MTU3, and at this time, the data buffer 12 and the first MTU3.
Assuming that the WRITE processing is being performed between TU3, the microprocessor 13 reads the respective load information from the load information storage units 15 of the own system and the other system and compares them. As a result,
If the buffer of the local system is not used for MTU3, and the number of in-process instructions 101 of the other system and the number of drives in the buffer indicated by the buffer usage information 102 are smaller than that of the local system, the buffer from the other system is re-used. The status requesting the trial is set in the status storage unit 16.

Alternatively, if the data buffer 12 is being used for the MTU 3 in another system, the same status is set in the status storage unit 16 of the own system. Status is CHA1 of system A
It is sent to the host machine 2 via 0, and the host machine 2 which received it reissues the command to the B system MTC 1. This keeps the load of MTC1 in both systems balanced.

In the A-system MTC1, when the WRITE processing involving data transfer between the data buffer 12 and the first MTU3 is completed and there is no data for the MTU3 in the data buffer 12, the microprocessor 13 causes the load information storage unit 15 Clear the bit corresponding to the MTU3 of the buffer usage information of.

The WRITE command has been described above, but the same applies to other commands.

In addition, as shown in Fig. 1, when two host machines 2 are connected to each MTC1, load can be distributed by instructions from each MTC1 without communication means between the host machines. Can be easily analogized.

〔The invention's effect〕

As described above, according to the present invention, it is more efficient to provide a means for comparing the load statuses of the peripheral control devices that share the controlled device with each other and perform the processing by the peripheral control devices of other systems. In some cases, by providing a means for requesting a retry from the peripheral control device of another system to the host device, even when a plurality of host devices are connected or a large amount of processing is performed asynchronously with the host device. There is an effect that an appropriate load distribution process can be realized with less hardware.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a magnetic tape controller according to an embodiment of the present invention, and FIG. 2 is a diagram showing types and forms of information stored in the load information storage section shown in FIG. Explanation of symbols: 1 …… Magnetic tape controller (MTC), 2 …… Host machine, 3 …… Magnetic tape unit (MTU), 10 …… Host connection part (CHA), 11 …… Device connection part (MTA) , 12 ... Data buffer, 13 ... Microprocessor, 14 ... Control information storage section, 15 ... Load information storage section, 16 ... Status storage section.

Claims (1)

[Claims] 1. In a peripheral control device that shares a controlled device with another peripheral control device and is connected to the same higher-level device, means for storing the operating condition and said operating condition to the other peripheral control device. A means for notifying each other and the stored operating condition and the operating condition notified from the other peripheral control device should be compared, and which peripheral control device should perform new processing instructed by the host device. And a means for deciding whether or not a new process should be processed by the other peripheral control device, and requests the host device to retry via the other peripheral control device. And a peripheral control device.