JPH0722169B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly, to a mounting structure of a semiconductor chip on a package.

(Prior Art) Semiconductor integrated circuits have become highly integrated in recent years. Along with this, a package that accommodates a semiconductor chip is also enlarged, and the number of electrodes on the package reaches 300.

2A and 2B show a general mounting structure of a semiconductor integrated circuit chip. Reference numeral 21 is a chip, and 23 is a package base on which the chip is mounted. The electrode pads 22 on the chip 21 and the electrodes 24 on the package base 23 are connected by bonding wires 25. With the high integration and the increase in the number of pins of integrated circuits, the area and the interval of the electrode pad row on the chip and the electrode row on the package base tend to be further reduced in the future. However, there is a technical limit to this reduction.

FIGS. 3 (a) and 3 (b) show a mounting structure designed to solve this problem. Electrode pad 32 of integrated circuit chip 31
Are provided in two rows along each side, and the electrodes 34 on the package base 33 are also arranged in two steps in a stepwise manner.
The bonding wire 35 connects between the electrode 32 and the electrode 34. By such multi-step bonding, it is intended to cope with the increase in the number of pins without extremely reducing the electrode interval or the like.

(Problems to be Solved by the Invention) When the multi-stage wire bonding technique is applied as shown in FIG. 3, there is a high possibility of a short circuit due to the overcrowding of the bonding wires. On the other hand, a proposal has been made to prevent short circuits by alternating the wire bonding directions next to each other (Japanese Patent Laid-Open No. 59-195856), but it has not been a fundamental solution. Further, if the electrode is made into a high density multi-stage electrode, it becomes difficult to perform wire bonding itself. Further, as the density of the bonding wires tends to decrease, the thickness of the wires tends to decrease, so that there is a problem that a plurality of wires must be provided in a portion such as a power supply line through which a relatively large current flows. Occurs.

It is an object of the present invention to provide a semiconductor device which solves the above problems and realizes a highly reliable mounting structure for a multi-pin package.

[Structure of the Invention] (Means for Solving Problems) The present invention relates to a semiconductor device having a semiconductor chip and a package in which the chip is mounted, and in the electrode pad on the semiconductor chip and on the package base. Of the electrode of the semiconductor chip and the electrode of the package base are connected to each other by wire bonding and wireless bonding. It is characterized in that they are connected by bonding.

Here, the large current refers to a current of a magnitude such that one wire is melted by one wire and a necessary current capacity cannot be secured.

(Operation) According to the present invention, wire bonding and wireless
By combining bonding, the pitch between bonding wires can be kept larger than before even in the case of a multi-pin mounting structure. In particular, if the package-side electrode has a two-stage structure and the lower stage is almost at the same height as the surface of the semiconductor chip, the lower electrode and the chip upper electrode pad are first connected collectively by wireless bonding such as tape lead or beam lead. Then, wire bonding is performed between the upper electrode and the remaining electrode pads on the chip to reduce the risk of short circuit between the bonding wire and the lead and facilitate the bonding connection. it can. Moreover, since the wireless bonding is preferentially used in a portion such as a power supply line where a relatively large current flows, a sufficient current capacity can be secured without providing a thin bonding wire.

(Embodiment) FIGS. 1A and 1B show an integrated circuit chip mounting structure of an embodiment of the present invention. Reference numeral 11 denotes an integrated circuit chip, the electrode pads 12 of which are divided into two rows along each side and arranged in a zigzag pattern. Reference numeral 13 denotes a package base on which the chip 11 is mounted, and the electrodes 14 on the package base 13 are arranged in two steps at positions of different heights. The lower electrode arrangement and the upper electrode arrangement have a zigzag pattern, which is shifted by half a pitch. In this embodiment, the electrode pad 12 on the chip 11 and the electrode 14 on the package base 13 are connected by a combination of the TAB (Tape Automated Bonding) method and the wire bonding method. That is, the height position of the lower electrode portion of the package base 13 is substantially equal to the surface position of the chip 11, and first, the lower portion of the electrode 14 on the package base 13 and the outer portion of the electrode pad 12 on the chip 11 are arranged. Is connected by a tape lead 16 by the TAB method, and then an upper part of the electrode 14 on the package base 13 and an inner part of the electrode pad 12 on the chip 11 are connected by a bonding wire 15. is doing. In this embodiment, as the TAB method, a case where a tape called a BTAB (Bunped TAB) method with a protruding electrode 17 is used is shown. Further, in this embodiment, the tape lead 16 having a larger current capacity than the bonding wire 15 is used in a portion such as a power supply line where a relatively large current flows.

With such a structure, it is possible to eliminate the overcrowding of the bonding wires 15 and prevent a short circuit between the bonding wires 15. Further, since the bonding wire 15 and the tape lead 16 have different heights, and the tape lead 16 has no slack, the bonding wire 15
The probability of a short circuit between 15 and tape lead 16 is also very low. Therefore, highly reliable multi-pin mounting is possible. By separately using the tape lead for the portion where the current is large, it is possible to eliminate the troublesomeness of providing two thin bonding wires. The bonding process is very simple because half of the bonding connections are connected together using the TAB method.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the electrodes on the package base have a two-stage structure, but there are three or more stages and only the first stage is wireless and the other stages are bonding wires, or the second stage is wireless and more. Various combinations such as bonding wires are possible. Further, even when the electrodes on the package base are not arranged in a staircase, a sufficient effect can be obtained by the combination of wire bonding and wireless bonding. Although the TAB method is used as an example of wireless bonding in the above embodiment, a beam lead or the like can also be used.

Others The present invention can be variously modified and implemented without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, it is possible to obtain a semiconductor device that realizes highly reliable mounting in a multi-pin package.

[Brief description of drawings]

1 (a) and 1 (b) are a plan view and a sectional view showing an integrated circuit chip mounting structure of an embodiment of the present invention, and FIGS. 2 (a) and 2 (b).
3 (a) and 3 (b) are a plan view and a sectional view showing a conventional mounting structure. 11 ... Integrated circuit chip, 12 ... Electrode pad, 13 ... Package base, 14 ... Electrode, 15 ... Bonding wire, 16 ... Tape lead, 17 ... Projection electrode.

Claims (3)

[Claims] 1. In a semiconductor device having a semiconductor chip and a package on which the chip is mounted, wire bonding and wireless bonding are performed between electrode pads on the semiconductor chip and electrodes on the package base. And a portion of the electrode on the semiconductor chip and an electrode on the package base where a large current flows are connected by wireless bonding. 2. The electrode pads on the semiconductor chip are arranged in two or more rows on one side of the chip, and the electrodes on the package base are formed in two or more rows at different heights in a step shape. An example of the outer electrode pads on the chip and the lower electrode row on the package base are connected by tape leads or beam leads, and the inner electrode pad row on the semiconductor chip and the upper row on the package base are connected. The semiconductor device according to claim 1, wherein the electrode array is connected by a bonding wire. 3. The semiconductor device according to claim 1, wherein the wireless bonding is based on the BTAB method.