JPH0722261B2 - MOS drive circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a MOS drive circuit which is composed of MOS transistors and drives a load with low power consumption.

[Prior Art] Conventionally, as a technology in such a field, there is Japanese Patent Laid-Open No. 58-1889.
Some were described in Japanese Patent No. 31. The configuration will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing a configuration example of a conventional MOS drive circuit.

This MOS drive circuit has an input terminal 1 for inputting an input signal V1, an output terminal 2 for outputting an output signal V2, and a high power supply potential VCC.
And a power supply terminal 4 to which a low power supply potential VSS is applied. An inverter 6 having a long fall time of an output signal and an inverter 6 having a long rise time of an output signal are connected in parallel to the input terminal 1. Complementary MO composed of a P-channel type MOS transistor (hereinafter referred to as PMOS) 7 and an N-channel type MOS transistor (hereinafter referred to as NMOS) 8 between the power supply terminals 3 and 4.
An S-transistor (hereinafter referred to as CMOS) inverter is connected. PMOS7 is the output signal V5 of the inverter 5 and NMO
The S8 is on / off controlled by the output signal V6 of the inverter 6, and the output signal V2 is output from the output terminal 2 connected between the PMOS 7 and the NMOS 8.

FIG. 3 is a signal waveform diagram of each part in FIG. Input signal V1
Is applied to the input terminal 1, the input signal V1 is inverted by the inverters 5 and 6 to become signals V5 and V6. The PMOS 7 and the NMOS 8 are turned on and off by the signals V5 and V6, and the output signal V2 slightly delayed from the input signal V1 is output from the output terminal 2.

Here, with respect to the signal V5, the PMOS 7 is configured to be off during the periods ta to tc, on during the periods tc to td, and off during the periods td to tf. Similarly, for signal V6, NMOS8
Is on during the period ta to tb, off during the period tb to te, and
It is configured to turn on between te and tf. Therefore, during the periods tb to tc and the periods td to te, a period in which both the PMOS 7 and the NMOS 8 are off can be taken. Therefore, there is no period in which both the PMOS 7 and the NMOS 8 are turned on, and it is possible to simply and accurately prevent the through current flowing between the power supply terminals 3 and 4 via the POMS 7 and the NMOS 8 during the transition.

[Problems to be Solved by the Invention] However, in the circuit having the above configuration, since the PMOS 7 and the NMOS 8 are both turned off at the transition of the rising and falling of the input signal V1, the output terminal 2 is in a floating state (high impedance). Status) Not only FT but inverter 5,
Since 6 has a delay at the time of rising and falling, there is a problem that this delay appears in the output signal V2.

Due to these problems, when driving, for example, a liquid crystal (hereinafter referred to as LCD) as a load, there is a disadvantage that crosstalk (leakage) or the like occurs in the LCD.

That is, the LCD has, for example, a structure in which a liquid crystal material is interposed between a large number of segments and a plurality of common terminals. When such an LCD is driven by a conventional circuit, not only the output waveform rise and fall delays are uneven between segment terminals, but also when the duty ratio is high, the output waveform rises and falls between common terminals. The delay becomes uneven, and the delay of the output waveform becomes uneven between the common terminal and the segment terminal. Furthermore, except for the terminal that operates the fastest among these common terminals and segment terminals, the output waveform is still in the floating state FT, which causes crosstalk in the LCD, making it difficult to obtain contrast and making the display surface unclear. There is.

Therefore, it is conceivable to use the techniques disclosed in JP-A-52-39354 and JP-A-58-196726, but it has not been possible to obtain a MOS drive circuit which is technically sufficiently satisfactory.

The present invention has the problems that the above-mentioned conventional technology has, such as a floating state FT of an output terminal at a transition at the time of rising and falling of an input signal and a delay of the output signal at the time of rising and falling of the input signal. MO that solved the point
An S drive circuit is provided.

[Means for Solving the Problems] In order to solve the above problems, the first invention is a MOS drive for changing the potential level of an output terminal according to an input signal having a first or second input level. The circuit includes a switch circuit and a timing circuit. here,
In the switch circuit, the first switch means including a MOS transistor having a small resistance value in the on state and the second switch means including a MOS transistor having a large resistance value in the on state have the output terminal and the first potential level. Is connected in parallel with the first power supply terminal for supplying the voltage, and another switch means composed of a MOS transistor for performing on / off operation opposite to the second switch means is connected to the output terminal and the second potential level. Is a circuit connected between the second power supply terminal and the second power supply terminal.

Further, the timing circuit is configured to shift the output terminal substantially from the second potential level to the first potential level in accordance with the shift of the input level of the input signal. Switch-on means at substantially the same time to switch the output terminal from the first potential level to the second potential level substantially from the first input level of the input signal. The first switch means is turned off in response to the transition to the second input level, and then the first input signal is changed from the second input level to the first input level.
Is a circuit for turning off the second switch means in response to the shift to the input level of.

A second invention is a MOS that shifts the potential level of an output terminal according to an input signal having the first or second input level.
The drive circuit includes a switch circuit and a timing circuit. Here, in the switch circuit, the first switch means composed of a MOS transistor having a small resistance value in the on state and the second switch means composed of a MOS transistor having a large resistance value in the on state are the output terminal and the first switch means. Connected in parallel with the first power supply terminal for supplying the potential level of the third switch means, which is composed of a MOS transistor having a small resistance value in the ON state and a MOS transistor having a large resistance value in the ON state. The fourth switch means is a circuit connected in parallel between the output terminal and the second power supply terminal that supplies the second potential level.

Further, the timing circuit changes the output terminal from the first input level of the input signal to the second input level so as to substantially shift the output terminal from the second potential level to the first potential level. In response to the transition of the third switch means to the off state, and in response to the transition of the input signal from the second input level to the first input level. The switch means being turned on at substantially the same time and the fourth switch means being turned off to cause the output terminal to transition substantially from the first potential level to the second potential level; The first switch means is turned off in response to the transition of the input signal from the first input level to the second input level, and then the first input device is switched from the second input level of the input signal to the first input means. Corresponding to the input level of And a circuit for the switching means of the second off state while substantially simultaneously turned on and the fourth switching means.

[Operation] According to the first and second inventions, since the MOS drive circuit is configured as described above, the timing circuit responds to the transition of the input level of the input signal having the first or second input level. The switch circuit composed of the first switch means having a small ON resistance value and the second switch means having a large ON resistance value is operated as follows. That is, the timing circuit turns off the first switch means having a small on-resistance value before the second switch means having a large on-resistance value when the potential level of the output terminal is shifted to another potential level, and then , The second switch means having a large on-resistance value is turned off. In addition, this timing circuit includes the first and second timing circuits.
The switch means are turned on at substantially the same time. In this way, by operating the switch circuit by the timing circuit, the potential level of the output terminal is moved at high speed without reducing the output terminal, and the shoot-through current generated in the switch circuit is reduced. Therefore, the above problems can be eliminated.

[Embodiment] FIG. 1 is a circuit diagram of a MOS drive circuit showing an embodiment of the present invention.

In this MOS drive circuit, the switch circuit 30 is operated by the output signal of the timing circuit 10.

The timing circuit 10 has an input terminal 11 to which an input signal V11 is input and output terminals 12, 13 and 14 which output output signals V12, V13 and V14, respectively. Input terminals 11 are connected to input terminals of T-type flip-flops (hereinafter, referred to as T-FF) 20, 21. The input side of the NOT gate 22 for outputting the output signal V12 is connected to the output terminal Q for outputting the output signal V1 of the T-FF21. The output terminal Q for outputting the output signal V20 of the T-FF20 and the output terminal Q of the T-FF21 have a 2-input NO
The R gate 23 and the 2-input NAND gate 24 are connected to each other.

T-FF20 operates at the leading edge of input signal V11 and
F21 is a flip-flop that operates on the trailing edge of the input signal V11. Further, the NOT gate 22 inverts the output signal V21 of T-FF21, and the NOR gate 23 outputs the output signal V20, T20 of T-FF20, 21.
The NAND gate 24 has a function of taking the NAND of the V21 and the NAND of the output signals V20 and V21 in the T-FFs 20 and 21, respectively, and giving the NAND to the switch circuit 30 at a predetermined timing.

The input side of the switch circuit 30 is connected to the output terminals 12 to 14 of the timing circuit 10, respectively, and the output terminal 31 that outputs the output signal V31 and the first potential level (for example, the high power supply potential VCC) are applied. It has a first power supply terminal 32 and a second power supply terminal 33 to which a first potential level (for example, low power supply potential VSS) is applied. Between the power terminals 32 and 33,
The resistance value in the ON state is, for example, 10 KΩ to 50 KΩ, which is large, and the series circuit of the PMOS 40 and the NMOS 41, which is the fourth switch means, and the resistance value in the ON state is, for example, 1 KΩ to 5 KΩ. So each small first
And a series circuit of a PMOS 42 as a switch means and an NMOS 43 as a third switch means are connected in parallel.

The sources of the PMOS 40 and 42 are the power supply terminals 32, and the drains are NMOs.
They are connected to the drains of S41 and S43 and the output terminal 31, respectively. The gate of the PMOS 40 is connected to the output terminal 12, and the gate of the PMOS 42 is connected to the output terminal 14. Also, NMOS
The sources of 41 and 43 are connected to the power supply terminal 33, and
The gate of S41 is connected to the output terminal 12, and the gate of the NMOS 43 is connected to the output terminal 13.

FIG. 4 is a timing chart showing the signal waveform of each part of FIG. 1, and the operation of the circuit of FIG. 1 will be described with reference to this figure.

Incidentally, the in FIG. 4, the time t ₁ is the clock signal is the input signal V11 is at a low level when it is (hereinafter, "L" level hereinafter), the time t ₂ is high the signal V11 is initially I rising (Hereinafter referred to as “H” level), at time t ₃ at the fall of the same “H” level, at time t ₄ at the next rise of the signal V11, and at time t ₅ of the signal V11. Each of the following fall times are shown.

First, at time t _1, when the input signal V11 is input to the input terminal 11 is "L" level, the output signal V20 of the T-FF20 becomes "L" level. At the same time, in T-FF21, input signal V11
Is inverted and input, the output signal V21 is "L".
It becomes a level. The output signal V21 is inverted by the NOT gate 22 to become the "H" level signal V12, and the PMOS4
0 and sent to each gate of NMOS41. Further, the “L” level signals V20 and V21 become the “H” level signal V13 at the NOR gate 23, and are sent to the gate of the NMOS 43 via the terminal 13. Furthermore, the “L” level signals V20 and V21 become the “H” level signal V14 at the NAND gate 24, and are given to the PMOS 42 via the terminal 14.

Then, the PMOSs 40 and 42 are turned off and the NMOSs 41 and 43 are turned on, and the low power supply potential VSS is output from the output terminal 31. At this time, a through current does not flow between the power supply terminals 32 and 33 and the output terminal
31 is not a floating state FT either.

When the input signal V11 at time t ₂ becomes "H" level, signal V13 becomes the signal V20 is at the "H" level to the "L" level. Therefore, PMOS40, 42 and NMOS43 are off and NMOS4
1 is on. Therefore, the low power supply potential VSS is output from the output terminal 31 through the NMOS 41. At this time, a through current does not flow and the output terminal 31 is not in the floating state FT, as at the time t ₁ .

Then, the input signal when V11 is falls to "L" level at time t _3, with signal V12 becomes the signal V21 is at the "H" level to "L" level, signal V14 becomes "L" level . Therefore, the NMOSs 41 and 43 are turned off and the PMOSs 40 and 42 are turned on. Therefore, the high power supply potential Vcc is applied to the output terminal 31 through the PMOS 40 and 42.
Is output. At this time, a through current flows from the PMOS 40, 42 through the NMOS 41. However, due to the high resistance of the NMOS 41 in the ON state, for example, 10 KΩ to 50 KΩ, the through current is 1/20 to 1/20 compared to the conventional CMOS inverter with the ON state resistance of 1 KΩ to 5 KΩ. Not only can it be reduced to about / 100, but the output terminal 31 does not enter the floating state FT.

Furthermore, the input signal when V11 rises to "H" level at time t _4, the signal V14 signal V20 becomes "L" level to the "H" level. Therefore, NMOS41,43 and PMOS42 are off and P
MOS40 is on. Therefore, the high power supply potential VCC is output from the output terminal 31 through the PMOS 40. At this time, a through current does not flow and the output terminal 31 does not enter the floating state FT.

After that, when the input signal V11 falls at time t5, the signal V
21 becomes "L" level, the signal V12 becomes "H" level, and the signal V13 becomes "H" level. Therefore, PMOS40,42
Turns off and NMOS 41, 43 turn on. Therefore, output terminal 3
The low power supply potential VSS is output from 1 through the NMOSs 41 and 43. At this time, a through current flows from the PMOS 40 through the NMOSs 41 and 43, but the resistance value of the PMOS 40 in the ON state is, for example, 10K.
Due to the high resistance of Ω to 50 KΩ, not only the through current can be reduced to about 1/20 to 1/100 as compared with the conventional one, but also the output terminal 31 does not become the floating state FT.

Furthermore, in the present embodiment, the resistance value of the PMOS 42 and the NMOS 43 in the ON state is low resistance, for example, 1 KΩ to 5 KΩ,
Not only the drive capability of output signal V31 is the same as that of the conventional circuit, but also the output signal to prevent shoot-through current as before.
Since it does not use the signal delay at the rise and fall of V2,
There is no delay in rising or falling of the output signal V31.

As described above, in this embodiment, the shoot-through current in the transient state of the output signal V31 is reduced, the consumption current is suppressed, and the transient waveform (transient waveform that occurs on the source side of the PMOS 40, 42 and the NMOS 41, 43 ) Is reduced, and the floating state of the output terminal 31 in the transient state can be prevented. Therefore, using the circuit of this embodiment, for example, an LCD
Drive, the power supply terminals 32,3
Since the transient waveform generated in 3 is also small, it is possible to display a clear image with high contrast.

In the above embodiment, the PMOS 40, 42 is used as the switch means.
, And NMOS 41 and 43 are used, for example, as shown in FIG.
It is also possible to use an analog switch as shown in (2).

Here, the analog switch 50 of FIG.
And the source and drain of the NMOS 52 are connected to each other, and an inverter 53 is connected to each gate of the PMOS 51 and the NMOS 52.
A reverse phase signal is input through the PMOS 51 and the NMOS 52 to turn them on and off at the same time.
Similarly, the analog switch 60 of FIG.
And the source and drain of the PMOS 62 are connected to each other, and the gates of the NMOS 61 and the PMOS 62 are connected via the inverter 63.

When using such analog switches 50 and 60,
Instead of the PMOSs 40 and 42 and the NMOSs 41 and 43 in the figure, two analog switches 50 and 60 operated by a signal V12 and a signal V1
By arranging the analog switch 60 that operates according to 3 and the analog switch 50 that operates according to the signal V14, the same advantages as those of the above-described embodiment are obtained.

Further, the timing circuit 10 of the above embodiment can be modified in various ways.

[Effects of the Invention] As described in detail above, according to the first and second inventions, the on-resistance value is small according to the transition of the input level of the input signal having the first or second input level. A timing circuit for operating a switch circuit composed of the first switch means, the second switch means having a large ON resistance value, and the like is provided. In this timing circuit, when the potential level of the output terminal is shifted to another potential level, the first switch means having a small ON resistance value is turned off before the second switch means having a large ON resistance value, and then, The second switch means having a large on-resistance value is turned off. The timing circuit also causes the first and second switch means to be turned on substantially simultaneously.

Therefore, the potential level of the output terminal can be shifted at a high speed and the shoot-through current generated in the switch circuit can be reduced without bringing the output terminal into a floating state.

Further, in the first and second aspects, the potential level of the input signal having the first or second potential level changes from the first potential level to the second potential level,
The first switch means having a small on-resistance value is turned off, and the second switch means having a large on-resistance value is turned off in response to the transition from the second potential level to the first potential level. Therefore, it is possible to set the timing for turning off the second switch means having a large on-resistance value in accordance with the length of the second potential level of the input signal, and to set the optimum on-resistance value of the switch means according to the setting. Each switch means can be easily operated at various timings.

Therefore, when driving an LCD using this MOS drive circuit, for example, crosstalk is small and transient waveforms generated at the power supply terminals due to shoot-through current can be suppressed, so that clear image display with high contrast becomes possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a MOS drive circuit showing an embodiment of the present invention,
2 is a circuit diagram of a conventional MOS drive circuit, FIG. 3 is a signal waveform diagram of each part of FIG. 2, FIG. 4 is a signal waveform diagram of each part of FIG. 1,
FIGS. 5 (1) and 5 (2) are circuit diagrams showing modified examples of the switch means in FIG. 10 …… Timing circuit, 11 …… Input terminal, 30 …… Switch circuit, 31 …… Output terminal, 32,33 …… Power supply terminal, 40,42…
… PMOS, 41,43 …… NMOS.

Claims (2)

[Claims] 1. A MOS for changing the potential level of an output terminal according to an input signal having a first or second input level.
In the drive circuit, the first switch means including a MOS transistor having a small resistance value in the ON state and the MOS having a large resistance value in the ON state
A second switch means composed of a transistor is connected in parallel between the output terminal and a first power supply terminal for supplying a first potential level, and performs an on / off operation opposite to that of the second switch means. A switch circuit connected to the output terminal and a second power supply terminal for supplying a second potential level, the switch circuit being formed of a MOS transistor, and the output terminal being substantially connected to the second potential. In order to shift from the level to the first potential level, the first and second switch means are turned on substantially at the same time in response to the shift of the input level in the input signal, and the output terminal is substantially turned on. In order to shift the first potential level to the second potential level, the first switch means is turned off in response to the shift of the input signal from the first input level to the second input level. Status The second signal of the input signal after
And a timing circuit for turning off the second switch means in response to the transition from the input level to the first input level. 2. A MOS drive circuit that shifts the potential level of an output terminal according to an input signal having a first or second input level, the first switch means comprising a MOS transistor having a small resistance value in an ON state. And a MOS with a large resistance in the ON state
A second switch means composed of a transistor is connected in parallel between the output terminal and a first power supply terminal for supplying a first potential level, and has a small resistance value in the ON state.
A third switch means composed of a transistor and a fourth switch means composed of a MOS transistor having a large resistance value in the ON state are connected in parallel between the output terminal and a second power supply terminal for supplying a second potential level. A switch circuit connected to the first input level of the input signal to substantially shift the output terminal from the second potential level to the first potential level. In response to the transition to the level, the third switch means is turned off, and then the first and the first input levels are responded to in response to the transition from the second input level of the input signal to the first input level. To turn on the second switch means substantially simultaneously and turn on the fourth switch means to shift the output terminal substantially from the first potential level to the second potential level. , The input After the first switch means is turned off in response to the transition of the signal from the first input level to the second input level, the second input level of the input signal is changed to the first input level. A timing circuit for turning on the third and fourth switch means substantially at the same time and turning on the second switch means in response to the shift to the input level. MOS drive circuit.