JPH0724277B2 - Semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor device in which a MOS field effect transistor is prevented from being broken during withstand voltage measurement.

(B) Conventional technology In the manufacture of semiconductor integrated circuit wafers, various test elements (MOS field effect transistors, resistances, capacitors, etc.) incorporated on the wafer are generally measured after the manufacturing process, and the evaluation results are shown. Based on this, defective wafers or defective lots are selected.

Of these, the measurement pattern of a MOS field effect transistor (hereinafter abbreviated as MOS transistor) is composed of a gate electrode, a source diffusion layer, a drain diffusion layer, and a substrate contact diffusion layer, and four electrode pads formed by extracting them from each. It is configured.

By the way, the measurement of the MOS transistor consists of the measurement of the source / drain breakdown voltage and the other measurement (measurement of the threshold voltage and the saturation current), but in the former measurement, the drain diffusion layer of the MOS transistor and the substrate are There is a problem that the joint portion is easily broken.

A MOS transistor having a miniaturized structure (a so-called LDD structure or DDD structure MOS transistor) is more easily broken.

This is due to an overcurrent (due to the avalanche breakdown phenomenon, which is a drain current of several 10 mA to several 100 mA) that occurs when a voltage exceeding the source-drain breakdown voltage is applied between the source and drain, and the above junction is thermally destroyed. It is estimated that

In the miniaturized MOS transistor, the source / drain diffusion layers are formed shallowly and have a rather low concentration region, so it is considered that they are easily affected by overcurrent.

In this regard, in the related art, the external protection resistor (5K
Ω to 100 KΩ) was previously attached to the deep needle of the probe card corresponding to the drain electrode pad to attenuate the overcurrent and prevent the destruction of the MOS transistor.

(C) Problem to be Solved by the Invention However, in this method, a protective resistor must be attached to the deep needle of the probe card by soldering or the like.

In addition, it is necessary to check whether or not the protective resistor is properly attached before the measurement, and there is a drawback that the measurement process becomes complicated.

The present invention has been made in view of the above conventional problems, and an object of the present invention is to prevent destruction of a MOS transistor at the time of breakdown voltage measurement without using an external protective resistor.

(D) Means for Solving the Problems The present invention provides a source / drain breakdown voltage measurement first pad connected to a drain diffusion layer of a MOS transistor by a high-resistance wiring, And a second pad connected by a wiring.

(E) Action According to the present invention, since a high resistance wiring is provided between the drain diffusion layer of the MOS transistor and the first pad, the first pad is used for the withstand voltage measurement. Since the high resistance wiring has a function of attenuating the overcurrent, it is possible to prevent the MOS transistor from being broken.

Since the drain diffusion layer and the second pad are connected by a low resistance wiring, use the second pad for other measurements (measurement of threshold voltage and saturation current). As a result, the original characteristics of the MOS transistor can be measured without being affected by the resistance.

As described above, according to the present invention, it is possible to prevent the breakdown of the MOS transistor at the time of measuring the breakdown voltage without using an external protective resistor, and to use a single MOS transistor pattern to perform other electrical operations such as threshold voltage The characteristics can also be measured accurately.

(F) Embodiment FIG. 1 shows a chip pattern of a semiconductor device according to an embodiment of the present invention.

In the figure, (1) is a semiconductor substrate, (2) is a gate electrode, (3) is a source diffusion layer, (4) is a drain diffusion layer,
(5) is a diffusion layer for substrate contact, (6A) to (6F) are contact holes, (7A) to (7F) are aluminum wirings,
(8) is a polysilicon wiring, (9) is a first pad for source / drain breakdown voltage measurement taken out from the drain diffusion layer (4) through the polysilicon wiring (8), (10)
Is a second pad taken out from the drain diffusion layer (4) through the aluminum wiring (7C).

If the sheet resistance of the polysilicon film is 50 Ω / port and the wiring width is 1.5 μm and the wiring length is 300 μm,
The resistance value of the polysilicon wiring (8) can be 10 KΩ.

The measuring method of the semiconductor device configured as described above will be described below.

The first pad (9), the second pad (10), the gate electrode (2) (not shown), the source diffusion layer (3), and the substrate contact diffusion layer (5) are taken out from the respective pads provided deeply. Set the needle, and use the first pad (9) for the source / drain breakdown voltage measurement on the drain electrode, and for other measurements (threshold voltage, saturation current measurement, etc.). Makes a measurement using the second pad (10).

As described above, according to this embodiment, the drain diffusion layer (4)
A 10KΩ polysilicon wiring (8) is provided between the second pad (10) and the first pad (9), and an aluminum wiring (7C) is connected between the drain diffusion layer (4) and the second pad (10). Therefore, by following the measurement method described above,
It is possible to prevent the breakdown of the MOS transistor at the time of withstanding voltage measurement, and to measure other electrical characteristics (threshold voltage, saturation current) with high accuracy.

(G) Effect of the Invention As described above, the semiconductor device of the present invention includes the first pad for source / drain breakdown voltage measurement, which is connected to the drain diffusion layer of the MOS transistor by the wiring of high resistance, and the drain diffusion layer. And a second pad connected by a low-resistance wiring, it is possible to prevent the MOS transistor from being destroyed during the measurement of the source / drain breakdown voltage, and other electrical characteristics (threshold voltage, saturation current). It is possible to provide a semiconductor device capable of measuring (1) with high accuracy.

Furthermore, since no external protective resistor is required, the measurement process can be simplified.

[Brief description of drawings]

FIG. 1 is a chip pattern diagram of a semiconductor device according to an embodiment of the present invention.

Claims (3)

[Claims] 1. A first pad for source / drain breakdown voltage measurement, which is connected to a drain diffusion layer of a MOS field effect transistor by a high resistance wiring, and a second pad which is connected to the drain diffusion layer by a low resistance wiring. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the high resistance portion of the high resistance wiring is formed of a polysilicon wiring. 3. The semiconductor device according to claim 1, wherein the low resistance wiring is formed of aluminum wiring or aluminum alloy wiring.