JPH0724309B2 - Semiconductor element - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device in which an operating speed is increased by utilizing a high speed electron propagation effect in a compound semiconductor represented by GaAs.

[Conventional technology]

Conventionally, many attempts have been made to construct a high-speed semiconductor device by utilizing the high-speed propagation effect of electrons in a semiconductor. In particular, by confining the electrons serving as carriers in one dimension, it is possible to realize an element that greatly exceeds the characteristics of conventional elements. For example, confine the movement of electrons in one dimension,
One-dimensional FETs have been proposed that utilize electron mobility enhancement by reducing the effect of scattering. (H.Sakaki: Japan Journal of Applied Physics (Jpn.J.Ap
pl.Phy.) 19,735 (1980), H. Sakaki: 1981 International Symposium on GaAs and related compounds, 1981 (Proc. 1981).
Int.Symp.on GaAs & Related Compound).

A plane structure of the above element is shown in FIG. In the figure, 1011 is a source electrode, 1013 is a drain electrode,
Reference numeral 14 is a thin line channel, and 1012 is a gate electrode. Various cross-sectional structures of the above-mentioned element have been proposed, which will be described later. Also, if a channel structure can be realized in which the channel through which electrons pass is split into two channels and then combined into one channel again, a phase difference of electrons is generated between the two separated channels, and at the combined portion. It has been proposed to obtain a transistor action by using the change in conductance caused by causing interference (S. Datta, MR
Melloch, S.Bandyopadhyay, and MS Lundstrom: Applied Physics Letters (Appl.Phys.Lett.) 48,487
(1986)). The above transistor is called a quantum interference transistor (QIT), and its planar structure is as shown in FIG. 6 (b). Here, 1021 is a source electrode, 10
Reference numeral 23 is a drain electrode, and 1022 is a gate electrode formed only in one of the channels of two paths. 1024 is a channel divided into two in the middle part. The operating principle of such a QIT transistor is completely different from that of a one-dimensional FET. That is, F
The ET controls the number of electrons, while the QIT controls the electron phase. Therefore, the absolute value of the voltage applied to the gate to be controlled is about several hundred mV for the FET, whereas it is about several mV for the QIT.

As mentioned above, there is a difference in operation principle between FET and QIT, but even in QIT, the electrons in the channel are more completely
If it can be confined within a dimension, the interference effect will be more complete and the device characteristics will be improved. Thus, in order to realize this kind of ultra-high-speed device, a potential structure that confines electrons one-dimensionally within several tens of nm, which is the de Broglie wavelength within the channel region, and a thinned channel region with branch points are optional. It is necessary to realize a potential structure that can be formed in the shape of. Furthermore, it is essentially necessary to reduce the influence of the surface interface, which is an important factor that impairs the electrical characteristics, along with the miniaturization.

[Problems to be solved by the invention]

Many structures have been proposed in the past for realizing the above-mentioned device, but as will be described below, any solution satisfying the above requirements has not been found, and the intended device has not been realized. The largest reason is due to a defect based on the sectional structure under the gate electrode indicated by AA 'in FIGS. 6 (a) and 6 (b). Next, the drawbacks of the conventional example will be described in detail.

FIG. 7 shows a sectional structure under the gate electrode of the above-mentioned conventional example.
In FIG. 7, 101 is a GaAs substrate, 102 is a GaAs layer, and 103 is A.
lGaAs layer, 104 is a gate electrode, and 105 is an induced carrier gas. The above structure is based on, for example, a known method,
A GaAs layer 102 and an AlGaAs layer 103 are sequentially formed on a GaAs substrate 101 by a molecular beam epitaxial (MBE) crystal growth method,
Further, it can be formed by depositing the gate electrode 104, processing it into a desired dimension, and then performing mesa etching. AlGa
If the As layer 103 is doped with appropriate impurities, the GaAs layer 1
Carrier gas 105 is formed at the interface with the AlGaAs layer 103 in 02.
Is induced and acts as a channel region. This action is a known fact in so-called HEMT devices. In the potential structure for confining electrons in the above structure, the difference in electron affinity between the GaAs layer 102 and the AlGaAs layer 103 in the vertical direction and GaAs
It is defined by the space charge in layer 102 and laterally, that is, the width W of the channel is defined by the shape of GaAs layer 102 by mesa etching, that is, the difference in electronic state between GaAs layer 102 and the vacuum. However, the above structure has a problem in the method for defining the lateral potential structure by mesa etching. In the above structure, in order to narrow the lateral expansion of the carrier gas region 105 and enhance the one-dimensional confinement effect, it is necessary to make the mask fine in the etching process and to use side etching and other etching techniques. Therefore, it has been very difficult to realize a miniaturized structure of several tens of nm or less.

Further, it is widely known that it is difficult to stabilize the surface or interface of a compound semiconductor, and trap levels are generated on the surface, which causes a drift phenomenon in the current value and deteriorates electrical characteristics. Therefore, even if a fine structure can be realized by making full use of etching technology, it is necessary to stabilize it because the lateral direction of this structure is the surface, but at present, it is effective for surface stabilization. There was a problem that no means was found.

A second example of the prior art is shown in FIG. In FIG. 8A, 201 is a GaAs substrate, 202 and 204 are AlGaAs layers, and 203.
Is a GaAs layer, 205 is a mixed crystal region, 206 is a formed channel region, and 207 is a mask. The above structure is based on, for example, a known method, on the GaAs substrate 201, the AlGaAs layer 202 and the GaAs layer.
After the 203 and the AlGaAs layer 204 are sequentially formed by the MBE crystal growth method, Si or the like is thermally diffused by heat treatment using an appropriate mask 207 to form the AlGaAs mixed crystal region 205. Alternatively, a similar structure can be obtained by implanting ions of Ga, Si, or the like into a region to be the AlGaAs mixed crystal region 205 by using the ion implantation technique and performing heat treatment. Finally, after removing the mask 207, a gate electrode is provided so that the above-described element functions.

In the potential structure in the above example, the vertical direction is AlGaAs.
It is defined by the difference in electron affinity between the layers 202 and 204 and the GaAs layer 203, and the lateral direction is defined by the difference in electron affinity between the mixed crystal region 205 and the GaAs layer 206. In the above structure, since the channel region is entirely surrounded by the hetero structure and the channel region is not exposed to the outside during the manufacturing process, it is difficult to stabilize the surface caused by the mesa etching, which is pointed out in the first example. The problem of is solved. However, the first
As in the above example, in order to reduce the lateral expansion of the channel region 206 in the above structure, it is necessary to miniaturize the mask in the thermal diffusion process or the ion implantation process, and a miniaturized structure of several tens nm or less is realized. There was great difficulty in that.

Further, in the above structure, the dimensions of the channel region 206 are determined by the mixed crystal process based on the diffusion phenomenon by the heat treatment,
That is, as shown in FIG. 8 (b), which shows the impurity distribution in the ion-implanted region, since the boundary portion has a low concentration and has a gentle characteristic, the steepness of the boundary between the channel region and the mixed crystal region is It is difficult to obtain, and there is a problem that it is essentially difficult to realize a miniaturized structure having a lateral spread of several tens nm or less.

A third example of the prior art is shown in FIG. In the figure, Ga
After the AlGaAs layer 302, the GaAs layer 303, and the AlGaAs layer 304 are sequentially formed on the As substrate 301 by the MBE crystal growth method, mesa etching is performed to re-grow the AlGaAs layer 305, and the gate electrode 3
Obtained by depositing 07. AlGaAs layer 305 above
If a suitable amount of impurities is doped in the GaAs layer 303,
Carrier gas is induced at the interface with the lGaAs layer 305 and acts as a channel region 306.

In the potential structure in the above example, the vertical direction is AlGaAs.
It is defined by the difference in electron affinity between the layers 302 and 304 and the GaAs layer 303, and the lateral direction is defined by the difference in electron affinity between the AlGaAs layer 305 and the GaAs layer 303 and the space charge of the GaAs layer 303.

In the above structure, the potential of confinement depends only on the control accuracy of the laminated film thickness, so it is possible in principle to realize a miniaturized structure of several tens of nm or less. The lateral confinement (indicated by W in the figure) is superior to the previous two examples. However, since the above structure uses the edge portion subjected to the mesa etching process, there is a problem that etching and a re-growth process of the AlGaAs layer 305 are required, which requires a high-level manufacturing technique.

In addition, since the edge portion is formed, the end surface of the GaAs layer 303, which will be the channel region, is exposed to the etching atmosphere, the atmosphere, etc. during the process. Therefore, it is necessary to perform the surface stabilization treatment on the end surface portion. However, as noted in the first example,
In compound semiconductors, it is widely known that it is difficult to stabilize the surface or interface, and trap levels occur on the surface, and there is a phenomenon of electrical characteristic deterioration such as a drift phenomenon in the current value. The serious problem is that no effective means for surface stabilization has been found. Furthermore, since the above structure utilizes the channel region induced at the end face, it is theoretically impossible to branch the channel region 306 into two or more channels in order to apply to QIT, for example. There is a problem in that, if an attempt is made to construct a potential structure in which the thinned channel region having the above is formed into an arbitrary shape, the complexity of the structure and the sophistication of the manufacturing technique are further required.

As described above, in the conventional structure, the channel width (W)
The largest point to be solved is that, when viewed at the electronic level, the dimension of could not be formed so narrow as to be regarded as one-dimensional.

The object of the present invention was a problem when miniaturizing the lateral dimension of the potential structure for confining electrons to about 100 nm or less, difficulty in forming a fine structure, difficulty in stabilizing the surface, branching point It is to provide a fine wire channel structure that solves the difficulty of formation.

[Means for solving problems]

The present invention provides a thin-line impurity-doped region in a substrate or a growth layer on the substrate having a large electron affinity,
The impurity-doped region is formed by providing a layer having a larger electron affinity, a layer having a larger electron affinity, and an electrode connected to the impurity-doped region and applying a predetermined potential to the layer. 1-dimensional FET or quantum interference transistor (QIT) having a so-called MIS-like FET structure as a cross-sectional structure, which causes a channel region composed of a carrier storage layer or a carrier inversion layer to function as a channel inducing region and induces a channel region composed of a carrier accumulation layer or a carrier inversion layer on the lower surface of the uppermost layer Is proposed. Furthermore, in order to realize a one-dimensional channel with a narrower channel width, we use a microfabrication technology that uses a focused ion beam, etc. It enables the induction of narrower channels.

[Action]

According to the above means, an extremely fine structure (corresponding to the height of the channel) can be realized in the film thickness direction of the growth film (direction perpendicular to the main surface of the substrate) by the known high-precision film thickness control technique. In the lateral direction, that is, in the width direction of the channel, it can be made extremely fine without being adversely affected by the surface trap, resulting in 1
Dimensional channels can be realized, and if applied to FETs or QITs, high-speed devices that maximize the high-speed electron propagation effect can be realized.

Further, in the past, the width of the induced channel could not be electrically controlled, and therefore only a channel width equal to the width of the channel induced region could be realized. It has an effect that a channel width narrower than a certain width can be realized by electrical control. Therefore, a channel width less than the physical processing limit of the channel inducing region can be realized, so that a one-dimensional channel can be realized more easily.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a view showing a first embodiment of a semiconductor device according to the present invention,
(A) is a plan view showing a one-dimensional FET, (b) is a plan view showing a quantum interference device (QIT), (c) is a cross-sectional view of an essential part, second
FIG. 4 is a sectional view of a main part of a second embodiment according to the present invention, FIG. 3 is a sectional view of a main part of a third embodiment according to the present invention, and FIG. 4 is a view showing a fourth embodiment of the present invention. ) Is a sectional view of an essential part, (b) is a schematic view showing an impurity concentration distribution, and FIG. 5 is a sectional view showing a fifth embodiment of the present invention.

First Embodiment The one-dimensional FET and the QIT are elements having completely different structures and operating principles as described above, but they are common in that the performance is improved if a one-dimensional channel can be formed. Is important for the sectional structure directly under the gate. In other words, by specifying only the structure directly under the gate,
It can be easily applied to both the one-dimensional FET shown in FIG. 1A and the QIT shown in FIG. Therefore, also in the following embodiments, only the sectional structure immediately below each gate will be described.

FIG. 1 (a) is a plan view of a one-dimensional FET, 11 is a source electrode, 13 is a drain electrode, 12 is a gate electrode, 406 is a thin line channel, and QIT shown in FIG. 1 (b) is 21 is a source electrode, 23 is a drain electrode, 22 is a gate electrode, 406
Indicates a thin line channel, but the gate electrode 12
FIG. 1 (c) is a view showing the AA ′ cross section of 22 and 22.
In FIG. 1 (c), 401 is a GaAs substrate and 402 is the above GaAs.
The GaAs layer of the first deposited film grown by the molecular beam epitaxial method (MBE method) on the substrate 401, and 403 is the above GaAs layer.
An AlGaAs layer of a second deposited film grown on the layer 402 by the MBE method, the AlGaAs having a smaller electron affinity than GaAs. Al
The composition ratio of is arbitrary, but is preferably about 0.2 to 0.5. 404
Is a non-doped or p-type third deposited film GaAs layer grown on the second deposited film AlGaAs layer 403 by the MBE method.
Has a higher electron affinity than AlGaAs. 405 is AlG above
Prior to the growth of the aAs layer 403, it is an n region which is selectively doped with an n-type impurity having a concentration of 10 ¹⁶ / cm ³ or more, for example, Si. Reference numeral 406 indicates an induced channel region. If the impurity concentration is less than 10 ¹⁶ / cm ^3, it cannot be used practically in manufacturing and operation.

The electron affinity of the AlGaAs layer 403 is smaller than that of the GaAs layer 402,
Since the GaAs layer 404 is larger than the As layer 403, when an external control electrode connected to the impurity-doped region 405 is arranged and the potential is positively biased, the AlGaAs layer has a small electron affinity.
A channel region 406 is induced as a carrier accumulation layer or a carrier inversion layer in a region adjacent to the impurity-doped region 405 in the GaAs layer 404 across the region 403. The above mechanism is G
Well known as aAsMIS-like FET. In order to achieve the above purpose, 400 is the first bias electrode of the impurity-doped region 405 provided on the back surface of the GaAs substrate 401. 407
Is a fourth electrode for controlling electrons from the source of the second electrode to the drain of the third electrode in the channel 406 formed as described above, and is 12 in the FET of FIG. 1 (a),
This corresponds to 22 in the QIT of FIG. 1 (b). Electrode 4 above
The number of electrons flowing in the channel is controlled by the control signal added to 07, and the number of electrons is controlled in FET and the phase thereof is controlled in QIT to operate as transistors.

In the above structure, the electrode 400 for biasing the impurity-doped region is formed on the back surface facing the gate electrode 407, but the channel inducing region 405 is seen in plan view in FIG.
Since they are located below the channel 406 in (b) and (b), an electrode having an arbitrary size may be provided at an arbitrary position connected to the channel. For example, the planar electrode of the impurity-doped region 405 may be provided on the back surface of the GaAs substrate 401.

A particularly important technique in the manufacturing method for realizing the above structure is how to narrow the width of the impurity-doped region 405. That is, other techniques can be easily realized by known thin film deposition technique, electrode formation technique, and fine processing technique.

In order to dope the portion of the channel inducing region 405 as described above, for example, in addition to a usual method using a mask, as a more preferable manufacturing method, focused ions that are combined so that they can be transported without breaking a vacuum are used. After growing the GaAs layer 402 by using a beam device and a molecular beam epitaxial device, the GaAs layer 402 is transferred to a focused ion beam device without breaking the vacuum, and ion implantation into the channel induction region 405 is performed by the ion beam generated by the focused ion beam device. And further,
There is a method in which the AlGaAs layer 403 and the GaAs layer 404 are regrown by transporting them again to the molecular beam epitaxial device without breaking the vacuum.

By the way, as described above, the fine-width impurity-doped region 405 is used.
Is formed in the GaAs layer 402 having a large electron affinity, the AlGaAs layer 403 having a small electron affinity is formed on the GaAs layer 402, and the GaAs layer 404 having a large electron affinity and a high purity is further formed on the AlGaAs layer 403. , Induction of a channel in the high-purity GaAs layer 404 is known as MIS-like FET,
Furthermore, since the channel is formed in the high-purity GaAs layer 404, the mean free path due to impurity scattering is increased and the electrical characteristics are also greatly improved.

Further, in the present invention, since the channel inducing region 405 is selectively doped, the channel region 40
The lateral spread of 6 is limited by the spread of the potential generated by the space charge in the channel inducing region 405. The structure of the present invention does not require surface stabilization treatment because the surface of the crystal is not exposed to the atmosphere, etching atmosphere, etc. in the formation process and the final structure. This is one of the effects. Further, by modulating the mask pattern or the scanning method of the focused ion beam, a channel region having an arbitrary shape including branching can be formed.

Second Embodiment In FIG. 2 showing the AA ′ cross section of the lower part of the gate electrode in the second embodiment of the present invention, the difference from the first embodiment is as follows.
The GaAs layer 404 is not a single layer but has a two-layer structure of 404A and 404B, and the third deposited film GaAs layer 404A is about 10 nm or less,
A 404B layer having an electron affinity lower than that of the GaAs layer 404A is further formed on the GaAs layer 404A, for example, AlGaAs is used as a fourth deposited layer to form a double heterostructure by the MBE method to form the GaAs layer 404 into a multi-layer structure. As a result, by realizing a structure in which the dimension d of the channel region 406 can be limited to a small value as a so-called quantum well, the channel can be more effectively confined and a channel closer to one dimension can be realized.

Third Embodiment In FIG. 3 showing the AA ′ cross section of the lower part of the gate electrode in the third embodiment of the present invention, 406A, 406B and 406C respectively represent channel regions, and the potential of the channel inducing region 405 is
An electric signal (voltage) for controlling the channel width is applied to the electrode 400 connected to this, and when the positive bias potential is increased, the channel region expands as compared with 406B as shown by 406A, and a positive bias is applied. As the potential is reduced, the channel region becomes narrower, as shown at 406C. Therefore, the bias potential of the channel region 405 has the effect of changing the channel region from the actual size of the channel inducing region to an arbitrary size. In particular, by positively biasing the potential and reducing the absolute value, a channel region narrower than the width of the physical impurity-doped region 405 such as 406C can be realized.
It has become possible to form a channel region of μm or less.
The fact that the channel width can be narrowed by controlling the potential as described above is not limited to the structure shown in FIG. 3, that is, FIG. 1 (c), and a quantum well structure is provided as shown in FIG. Needless to say, it is also effective to combine the structure that positively limits the size and the technique of FIG. 4 in which the impurity distribution is made convex and the size is made finer by using the central portion as described later. Nor.

Fourth Embodiment FIGS. 4 (a) and 4 (b) are views for explaining a fourth embodiment of the present invention, in which 405A and 405B in FIG. 4 (a) are channel inducing regions and 406 is a channel region. is there. The above structure shows a structure in which impurity-doped channel inducing regions 405A and 405B are overlapped at the central portion. The above structure is
For example, it can be obtained by ion implantation using a focused ion beam generator, by scanning the ion beam twice, with a small gap between them. Due to the above structure, the impurity concentration in the overlapping portion of 405A and 405B is 405A and
It is higher than other portions in the 405B region, and the impurity concentration has a convex distribution in the entire channel inducing region as shown in FIG. 4 (b). By appropriately selecting the concentrations of 405A and 405B, it is possible to make only the overlapping portion, that is, the maximum point of the convex distribution, act as the effective channel induction region. 406
Is the channel region generated as described above.

The fine spacing of 405A and 405B can be adjusted to, for example, 0.05 μm or less by the recent focused ion beam generator, so that the above structure can form a channel region of 0.1 μm or less.

Further, it is needless to say that the effect is further increased if the channel region due to the bias potential of the channel inducing region described above is used together with the effect of changing the size of the actual channel inducing region to an arbitrary size.

Fifth Embodiment FIG. 5 shows a fifth embodiment of the present invention, which is an example in which the position of the electrode 400 provided on the back surface of FIG. In FIG. 5, 91 is an undoped GaAs layer inserted for the above structure, 92 is a conductive region for leading out an electrode, and 93 is an ohmic electrode for voltage application. The role of the electrode 400 in FIG.
The ohmic electrode 93 is also provided via the s layer 92, and the effect on the channel regions 406, 501, 502 is exactly the same as that of the first embodiment. To realize the above structure, for example,
Before forming the GaAs layer 402 on the GaAs substrate 401, the undoped GaAs layer 91 is grown, and selective ion implantation by a focused ion beam is performed in the region where the conductive region 92 is to be formed. To form. Then, the conductive region 92 is partially exposed by etching to form an ohmic electrode 93. The undoped GaAs layer 91
It is obvious that the GaAs substrate 401 may be used instead and the conductive region 92 may be formed in the substrate 401, and the same effect as described above can be obtained.

In addition, the structure in which the electrodes are horizontally extended and taken out from the surface like the fourth electrode 407 of the gate without taking out the electrodes from the back surface of the substrate as described above is used in combination with each of the above embodiments. Of course, is also effective.

In the above description, GaAs and AlGaAs layers are used as an example, but the same effect is obtained by using a heterostructure having the same electron affinity as the above combination, such as InP / InGaAs, InGaAs / InAlAs. It is clear that

〔The invention's effect〕

As described above, the semiconductor device according to the present invention includes the first deposited film made of the first semiconductor formed on the semiconductor substrate, and the second semiconductor having a smaller electron affinity than the first semiconductor formed on the first deposited film. A second deposited film, a third deposited film formed on the second deposited film, containing at least a third semiconductor having an electron affinity higher than that of the second semiconductor, and the first deposited film from the back surface side of the semiconductor substrate. A thin linear thin high-concentration impurity-doped region having a shape penetrating through and in contact with the lower surface of the second deposited film, and formed on the back surface of the semiconductor substrate or on the substrate in connection with the high-concentration impurity-doped region. A first electrode is provided in the conductive region, and a third wire is formed on the third deposited film above the channel region formed in the vicinity of the portion facing the high-concentration impurity-doped region and along the thin-line high-concentration impurity-doped region. ,Each The second, third provided at a septum, 4th
A fourth electrode having an electrode and controlling a current flowing between the second electrode and the third electrode through the channel region by applying a voltage to the first electrode is connected to the second electrode and the third electrode. Since a part of the cross-sectional structure is a so-called MIS-like FET structure because it is provided between the electrodes, by doping the channel induction region one-dimensionally,
Since the lateral spread of the channel region is defined by the spread of the potential induced by the channel-induced region,
(1) A channel region of several tens of nm can be formed, (2) The surface of the crystal in the formation process and the final structure is the atmosphere,
It has a structure that it is not exposed to the etching atmosphere and the like, and it does not require surface stabilization treatment, and (3) the mask pattern or the modulation of the scanning method of the focused ion beam allows the formation of a channel region of any shape including branching. There is.

In addition, if the present invention is applied to the channel region, one-dimensional FE
It becomes possible to realize ultra-high-speed devices such as T and quantum interference devices (QIT).

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a semiconductor device according to the present invention, (a) is a plan view showing a one-dimensional FET, (b) is a plan view showing a quantum interference device (QIT), and (c). Is a cross-sectional view of the main part,
FIG. 2 is a sectional view of an essential part of a second embodiment according to the present invention, FIG. 3 is a sectional view of an essential part of a third embodiment according to the present invention, and FIG. 4 is a view showing a fourth embodiment of the present invention. (A) is a sectional view of an essential part,
(B) is a schematic view showing an impurity concentration distribution, FIG. 5 is a sectional view showing a fifth embodiment of the present invention, FIG. 6 is a view showing a conventional example, (a) is a plan view of a one-dimensional FET, (B) is a plan view of a quantum interference device (QIT), FIG. 7 is a cross-sectional view applicable to the conventional example, and FIG. 8 is a view showing a second example applied to the conventional example. Is a cross-sectional view, FIG. 9B is a view showing an impurity distribution, and FIG. 9 is a cross-sectional view showing a third example in the conventional example. 11, 21 ... Second electrode 12, 22, 407 ... Fourth electrode 13, 23 ... Third electrode, 93, 400 ... First electrode 401 ... Semiconductor substrate, 402 ... First deposited film 403 ... … Second deposited film, 404 …… Third deposited layer 405 …… High-concentration impurity-doped region 406 …… Channel region

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 29/812

Claims (6)

[Claims] 1. A first deposited film made of a first semiconductor formed on a semiconductor substrate, and a second deposited film made of a second semiconductor having an electron affinity smaller than that of the first semiconductor formed on the first deposited film. A third deposition film formed on the second deposition film, the third deposition film including at least a third semiconductor having an electron affinity higher than that of the second semiconductor, and the second deposition that penetrates the first deposition film from the back surface side of the semiconductor substrate. A thin line-shaped high-concentration impurity-doped region having a shape that is in contact with the lower surface of the film and has a small width, and is connected to the high-concentration impurity-doped region through the back surface of the semiconductor substrate or a conductive region formed on the substrate. A first electrode is provided, and a thin line-shaped high-concentration impurity-doped region is formed on a third deposited film above a channel region formed in the third deposited film in the vicinity of a portion facing the high-concentration impurity-doped region. Along each The second was provided Te third, a fourth electrode, a semiconductor device having a fourth electrode is provided between the second electrode and the third electrode. 2. The third deposited film comprises a third semiconductor and a fourth semiconductor having an electron affinity lower than that of the third semiconductor, and the fourth deposited film formed by the fourth semiconductor is formed on the third deposited film. 2. The semiconductor device according to claim 1, wherein the second, third, and fourth electrodes are provided on the upper surface of the fourth deposited film at intervals with respect to each other. 3. The high-concentration impurity-doped region has one fine line at each of both ends in a plan view, and an intermediate portion is divided into two fine lines, and one of the divided fine lines is formed. The semiconductor element according to claim 1, characterized in that the fourth electrode is provided only on. 4. The semiconductor element according to claim 1, wherein the high-concentration impurity-doped region has an impurity concentration of 10 ¹⁶ / cm ³ or more. 5. The high-concentration impurity-doped region is the first
The channel 3 region lower surface width having a width different from the upper surface width of the high-concentration impurity-doped region can be formed by adjusting the voltage applied to the electrode. The semiconductor device described in any one. 6. The high-concentration impurity-doped region is characterized in that the impurity concentration distribution in a cross section in the width direction has a convex shape, and a channel region is induced only in a portion corresponding to the central portion of the convex shape. The semiconductor device according to claim 1, or any one of claims 3 to 5.