JPH0724405B2 - Serial communication system between multiple communication devices - Google Patents

Description

BACKGROUND OF THE INVENTION The present invention relates to serial transmission lines interconnected and
The present invention relates to a serial communication system including a plurality of communication devices including a CPU.

The conventional method of constructing a system consisting of multiple CPUs is to connect these CPUs to the bus. The buses include an address bus, a data bus, and a control bus. Even if each bus has an 8-bit configuration, a considerable number of bus lines are required.

There is a method using a serial transmission line as a method of significantly reducing the number of connection lines. This is for transmitting a serial signal on one or several lines. Although a signal serial / parallel conversion circuit or a parallel / serial conversion circuit is required, there is an advantage that the number of lines can be significantly reduced.

HDLC (High Lev
There are various formats, such as el Data Link Control), but these include all addresses, data, and commands in one telegram, and it becomes a considerable length (data length) and communication control is large. Become.

SUMMARY OF THE INVENTION An object of the present invention is to provide a serial communication system having a relatively simple structure suitable for transmitting and receiving a relatively short message.

The serial communication system according to the present invention is connected by a serial transmission line including a serial clock line, a signal output line, a signal input line, a busy signal line and a request signal line, and communicates with each other by at least two.
It consists of two communication devices. At least one communication device outputs a request signal indicating requesting communication to the other communication device to the request signal line, and a busy signal output to output a busy signal to the busy signal line. And means are provided.

The other communication device includes request signal detecting means for detecting a request signal input from the request signal line, and busy signal detecting means for detecting a busy signal given from another communication device through the busy signal line. It recognizes from the busy signal whether or not the device at the other end of the communication is in a communicable state.

A rising edge or a falling edge is given to each communication device prior to the signal to be output from the signal output line in order to distinguish the signal type according to the address, command or data signal type to be transmitted. Transmission signal output means for changing the signal level according to the presence or absence of an edge and its form and outputting these signals to the signal output line, and a level change for detecting the level change appearing in the signal input to the signal input line A detection means is provided, and addresses, commands and data are transmitted and received through the signal input line and the signal output line in response to a request signal or in response to a determination of the form of a busy signal.

In the present invention, the telegram sent to the signal output line or input from the signal input line includes only one of address, command or data, and the telegram length is very short. Therefore, editing the message is very easy.

To identify whether this message contains an address, a command, or data, the address,
Prior to the command or data, the level of the signal is changed according to the address, the command or the data, and the rising edge and / or the falling edge is added, or not added at all. In each communication device, the address based on the rising and falling edge detection of the serial signal,
Distinguish between commands and data. In this way, it is possible to send and receive addresses, commands, and data separately on one line, making use of the feature of the serial communication system that the number of lines can be greatly reduced, and the configuration is not so complicated.

In the present invention, since the signal output line and the signal input line are provided, simultaneous bidirectional communication is possible between the communication devices.

Further, in the present invention, since the serial transmission line includes the busy signal line and the request signal line, it is similar to the parallel communication system including a plurality of CPUs connected to the bus in this respect, and is a technique familiar with the parallel communication system. It is easy for people to handle.

An embodiment in which the present invention is applied to a still video system will be described in detail below, but it goes without saying that the present invention is not limited to this system. In the examples below,
Each controller and regenerator of the still video system
It corresponds to a communication device including a CPU.

Description of Embodiments (1) System Configuration FIG. 1 shows the system configuration of a still video camera.

The still video camera is controlled by three control devices, that is, a system control device 10, a photographing control device 30, and a recording control device 70. Each of these control devices 10, 30, and 70 is a memory (RAM, RO, etc.) that stores a CPU (for example, a microprocessor), its program, and necessary data.
M, etc.) and necessary interface circuits. The CPU of the system controller 10 is the main CPU, and controls the overall operation of the still video camera. The CPU of the photographing control device 30 and the recording control device 70 is a sub C
It is a PU and operates according to commands from the main CPU. The photographing control device 30 controls photographing such as focusing, aperture, shutter speed, and zoom. The recording control device 70 is used for driving the disk motor 3, loading / unloading the magnetic head 2, transferring the magnetic head 2, and the like.
The control for recording the video signal to the floppy 1 is performed. These control devices 10, 30, 70 are connected to each other by a serial transmission line (including five lines as described later), and communicate with each other at a predetermined timing described later.

A regenerator (reproduction adapter) 90 is also connectable, and this regenerator 90 demodulates the video signal read from the video floppy 1 and converts it into a color video signal of NTSC format and outputs it. The regenerator 90 also includes a CPU and memory, and this CPU is a sub-CP for the main CPU.
Positioned as U.

The still video camera is provided with a bucket that can be opened and closed, and the video floppy 1 is inserted into the opened bucket, and when the bucket is closed after that, the video floppy 1 moves to the disk motor 3 It is chucked on the spindle.

The video floppy 1 is provided with a plurality of tracks (for example, 50 tracks) (for example, a track pitch of 100 μm) concentrically, and one field or one frame (one frame) is provided for one or two tracks depending on the photographing process. The FM-modulated color video signal (including the luminance signal, the color difference signal, etc.) is magnetically recorded. The 50 tracks concentrically provided on the magnetic recording surface of the video floppy 1
The track numbers from No. 1 to No. 50 are attached in order from the outer one. The home position HP (origin position or standby position) is outside the No. 1 track, and the end position EP is inside the No. 50 track.

The system controller 10 has a power switch 16, various modes,
Switch input signals for switches 11 to 14, shutter release button 15, etc., detection signal of bucket switch 7 for detecting the open / closed state of the bucket containing the video floppy (and presence of video floppy if necessary), video The detection signal of the dew condensation sensor 8 for measuring the humidity in the vicinity of the installation location of the floppy 1 is input. The modes to be set include a frame / field mode indicating frame recording or field recording, a skip mode in which an empty track that is not recorded in the video floppy is provided, and an edit mode for performing recording on an empty track. . These set modes, track N to record
o., other information is displayed on the liquid crystal display 21. The display 21 is connected to the system controller 10 by a bus. In addition, when the dew condensation is detected or other abnormal conditions occur, the buzzer is
22 is alerted. Condensation detection may be displayed on the display 21.

The shutter release button 15 is a two-step stroke type, and when the first step is pressed, the switch S1
By the second step of further pressing, the switches S2 are turned on. When the switch S1 is turned on, the disc motor 3 is driven. After this, when the switch S2 is turned on, shooting and recording are performed.

The imaging optical system includes a zoom lens system 31, an imaging lens system 32 for forming a subject image, a diaphragm 33, and a beam splitter for deflecting a part of incident light to enter the photometric element 51.
34, an infrared cutoff filter 35, and a shutter 36. The illuminance detection signal of the photometric element 51 is input to the photographing control device 30 via the logarithmic amplifier 52. A process of calculating an aperture value and a shutter speed based on the incident light illuminance detected by the photometric element 51 by the photographing control device 30, control of the aperture 33 based on the determined aperture value, and a shutter 36 based on the shutter speed also determined. Open / close control is performed.
The diaphragm 33 is opened and closed by a diaphragm motor 48 driven by a driver 47. A switch 49 for detecting the limit position of opening and closing of the diaphragm 33 is also provided. Shutter
Unlatch the first and second curtains of 36, and wind them up by the driver
It is performed by a shutter drive device that includes a shutter motor 54 driven by 53. The rotation angle of the motor 54 is detected by the rotary encoder 55 and fed back to the device 30.

The color detection signal of the color sensor 61 is subjected to predetermined processing in the white balance processing circuit 62 and then input to the device 30. This white balance data is used for controlling the amplification gain of the R, G, B signals in the variable gain amplification circuit of the signal processing circuit 71 described later.

In order to measure the distance to the subject, an infrared light emitting diode 63 and a light receiving element 64 for receiving the reflected light are provided,
Based on the output signal of the light receiving element 64, the focusing processing circuit 65 obtains data representing the distance to the subject. Using this data, the auto focus motor 46 is driven via the driver 45 under the control of the device 30, and focusing control is performed.

In addition, a tele or wide
In response to the signals from the switches 38 and 39, the control device 30 drives the zoom motor 42 via the driver 41 to set a predetermined magnification. The rotation angle of the motor 42 is detected by the rotary encoder 43 and fed back to the device 30.

On the focal plane of the image pickup optical system, a solid-state electronic image pickup device 37 for three primary colors including a two-dimensional image pickup cell array such as CCD is arranged. The image data stored in the image pickup device 37 when the shutter 36 is opened is read out as a serial still video signal (R, G, B) in synchronization with the vertical and horizontal synchronizing signals given from the signal processing circuit 71. And input to the signal processing circuit 71.

The signal processing circuit 71 includes an oscillation circuit, and creates and outputs a vertical reference signal VD and a reference clock signal from the output signal of the oscillation circuit. The vertical reference signal VD is the system controller 10,
It is given to the photographing control device 30 and the recording control device 70 and serves as a reference for operation timing in these devices. The reference clock signal is given to the servo control circuit 80. As will be described later, a phase pulse PG representing the reference phase of rotation of the video floppy 1 is given to the signal processing circuit 71, the system controller 10, the recording controller 70 and the regenerator 90. The vertical reference signal VD is adjusted in the signal processing circuit 71 so as to maintain a constant phase relationship with the phase pulse PG by a reset signal provided from the recording control device 70. The signal processing circuit 71 also generates vertical and horizontal synchronizing signals having a fixed phase relationship with the phase pulse PG.

The signal processing circuit 71 further includes a preamplifier circuit for the input still video signals (R, G, B), a variable gain amplifier circuit (white balance adjustment circuit), and a process matrix circuit. A luminance signal Y and two color difference signals RY and BY are created in the process matrix circuit. These color difference signals R-Y and B-Y are then applied to the line sequential circuit 7
Line-sequentially every 1H at 2. The luminance signal Y and the line-sequential color-difference signal are FM-modulated in different frequency bands in FM modulation circuits 73 and 74 via a pre-emphasis circuit (not shown), and combined in a combining circuit 75.

It is also possible to record the additional information signal on the track of the floppy disk 1. The additional information signal means an acoustic signal (representing voice such as narration, music, etc.) and a display signal (representing character information, for example). This additional information signal is input to the signal processing circuit 71 from an input device (not shown) such as a microphone, converted into a predetermined format, and output to the line of the luminance signal Y. The additional information signal S may be superposed on the luminance signal Y, or may be output alone when only this signal S is recorded on a predetermined track of the video floppy 1.

Furthermore, data multiplex recording is possible for video floppy. This multiple recorded data includes initial bits, field / frame data, track address (N
o.) Data, date data and user data. These data are given from the system controller 10, and the signal processing circuit 71 uses DPSK (Differential Phase).
The signal is modulated by the shift keying), synthesized by the synthesizing circuit 76 together with the above FM modulated video signal, and input to the recording / amplifying circuit 77.

A magnetic head 2 for writing a still video signal of an imaged subject on a predetermined track of a video floppy 1
(The two are provided at intervals so as to be capable of frame recording so as to be located in adjacent tracks to each other.) Are movably supported in the radial direction of the video floppy 1 by the transfer drive control device thereof and in the same direction. Transfer controlled. The transfer drive controller includes a step motor 87 and its driver 86. The recording control device 70 gives instructions to the transfer drive control device about the transfer direction and transfer amount of the magnetic head 2. A home position switch 6 for detecting that the magnetic head 2 has reached the home position HP is also provided, and a detection signal of this switch 6 is given to the recording control device 70.

A head loading device is provided to prevent traces on the floppy disk due to the magnetic head 2 coming into contact with the video floppy disk 1 which has been stopped for a long time. This device includes a head load solenoid 85 and its driver 84, and is under the control of the recording control device 70 only during recording or reproduction (video floppy 1).
Magnetic head 2 is displaced (advanced and retracted) so that magnetic head 2 contacts video floppy 1 only when the power is turned on, or away from floppy 1 at other times. .

In order to improve the touching between the magnetic head 2 and the rotating video floppy 1, a regulation plate (not shown) is provided on the opposite side of the magnetic head 2 across the video floppy 1. Also, in the core of Video Floppy 1,
Detects the magnetic flux leakage from the permanent magnet for chucking
A phase detector 5 that outputs a phase detection signal when the floppy 1 reaches a predetermined angular position is close to it. The output detection signal of the phase detector 5 is waveform-shaped by the phase pulse generation circuit (waveform shaping circuit) 82 and output as the phase pulse PG, and as described above, the devices 10, 70, 90, the circuit 71 and the recording gate circuit 78. To enter. One phase pulse PG will be generated for each revolution of the video floppy 1.

The disk motor 3 is driven by its driver 81. The rotation speed of the disk motor 3 is detected by the frequency generator 4, and the detection signal of the frequency output from the frequency generator 4 and proportional to the rotation speed of the motor 3 is input to the servo control circuit 80. The servo control circuit 17 controls the motor 3 to rotate at a constant speed (for example, 3,600 rpm) at a constant speed based on the reference clock signal input from the signal processing circuit 71 and the frequency detection signal input from the detector 4. . The servo control circuit 80 also starts and stops the motor 3 in response to a command from the recording control device 70.

The still video signal and the like amplified by the recording amplifier circuit 77 is input to the recording gate circuit 78. Then, when a recording command is given from the recording control device 70, this gate circuit 78 opens its gate at the timing of the phase pulse PG to be input until the next phase pulse is input. As a result, the video signal or the like is given to the magnetic head 2, and the still video signal or the like is recorded on a predetermined track of the video floppy 1. This recording is made only during one revolution of the video floppy 1. This is the case for field recording. In the case of frame recording, the gate circuit 78 opens its gate for two revolutions of the video floppy 1, and the first rotation of the video floppy 1 causes one head 2 to record a video signal of the first field on one track. But the second
By the second rotation, the other head 2 records the video signal of the second field on the adjacent track.

It is also possible to reproduce the video signal from the video floppy 1 by the magnetic head 2. The FM-modulated video signal and the like read from the magnetic head 2 is similarly amplified by the amplifier circuit 77 via the gate circuit 78 and is given to the envelope detection circuit 83 and the regenerator 90. This reproduction is used for track search processing not only in the reproduction mode but also in the recording mode.

The envelope detection circuit 83 is a read signal of the magnetic head 2,
That is, it is a detection circuit that detects the envelope of the FM-modulated video signal recorded on the track of the video floppy 1 and outputs a voltage signal corresponding to it.
Includes / D (analog / digital) conversion circuit. The voltage signal representing the envelope is converted into a digital quantity by the A / D conversion circuit, converted into an 8-bit digital signal representing, for example, a quantization level of 256, and input to the recording controller 70.

The envelope detection signal indicates whether the track on the video floppy 1 is unrecorded or recorded.
70 is used to determine (track search process). If the level of the detection signal does not reach the predetermined threshold level when the magnetic head 2 is transported across the track, the track is unrecorded, and if it reaches the threshold level, The track has been recorded.

If necessary, the envelope detection signal is also used in the recording check process. The recording check process is a process of recording the photographed still video signal on the predetermined track by the magnetic head 2 as described above, and then checking whether or not this recording is actually performed. If it is above the threshold level, it is judged that recording has been performed.

(2) Communication System FIG. 2 shows a specific example of a serial transmission line that connects the system controller 10, the photographing controller 30, and the recording controller 70 (and the regenerator 90). This serial transmission line consists of 5 lines, and serial clock signal SCK, output signal So, input signal Si, busy (ready) signal ▲ ▼ (READY) and request signal (REQUEST) are transmitted on each line. To be done. Controller 10,30,7
Wired OR each line leading to 0 (and regenerator 90)
Are tied to each other. For example, the system controller 10
The line of the serial clock signal SCK of is connected to the serial clock signal lines of the other control devices 30, 70 (and the regenerator 90) by wired OR. The same applies to the other lines.

The serial clock signal (SCK) is the system controller 10
It is used to synchronize the signals output from and communicated with. The output signal So of the system controller 10 becomes the input signal Si of the other controllers 30, 70 (and the regenerator 90), and conversely the output signal So of the controllers 30, 70 (and the regenerator 90) becomes It becomes the input signal Si. The busy signal ▲ ▼ and the request signal REQUEST are output from the photographing control device 30 and the recording control device 70 (and the reproducing device 90) and given to the system control device 10. An address is assigned to each of the control devices 10, 30, 70 (and the regenerator 90) for designating them in the communication process.

An example of an interface circuit for communication in these control devices 10, 30, 70 (and regenerator 90) is shown in FIG. Prior to the description of this circuit, the communication method and the form of the signal So will be described with reference to FIGS. 4 and 5.

As mentioned above, in a still video camera,
The phase pulse PG is generated every one rotation of the video floppy 1. A still video signal for one field is video floppy 1 between two adjacent phase pulses PG.
Recorded in. Therefore, the basic operation of the still video camera is performed in synchronization with the phase pulse PG as a reference (hence the vertical reference signal VD as will be seen later).

FIG. 4 shows a time chart of basic signals in a still video camera system. The vertical reference signal VD and the vertical synchronizing signal Vsync are generated by the signal processing circuit 71 as described above, but these signals VD and Vsync are phase pulses.
It is controlled so as to be synchronized with the PG while maintaining a predetermined phase relationship. For example, the vertical reference signal VD is 4H (1H
Is a horizontal scanning period), and the vertical synchronization signal Vsync is generated with a delay of 7H. The period of these signals PG, VD, Vsync is equal to 1 V (1/60 sec = 16.6 ms) in the vertical scanning period.

Communication between the control devices 10, 30, 70 (and the regenerator 90) is also performed with the vertical reference signal VD as a reference.

On the other hand, important processing performed at a timing based on the vertical reference signal VD is processing for determining whether the vertical reference signal VD has a predetermined phase relationship with the phase pulse P, and rotation control by the servo control circuit 80. There is a determination process (servo lock determination process) of whether or not the rotation speed of the disk motor 3 has reached a predetermined rotation speed and is maintained at that rotation speed. The phase relation determination processing and the servo lock determination processing are executed by the sub CPU of the recording control device 70, but these processing require extremely high accuracy (that is, the measurement processing of a short time interval is performed. Since it is included), it is necessary for the above sub CPU to concentrate on these processes. Therefore, it is preferable to avoid communication processing with the main CPU of the system controller 10 during the time when the sub CPU is performing these processes. In general, interrupts in communication processing are given high priority, so if a sub CPU interrupts for communication while the sub CPU is performing servo lock determination processing, etc., the sub CPU proceeds to the interrupt processing routine. This is because there is a possibility that high accuracy may not be maintained in the servo lock determination processing and the like.

Therefore, as shown in Fig. 4, it starts from the vertical reference signal VD.
The 1V period is divided into the first half and the second half (for example, both are V / 2 periods), the servo lock determination process and the like are assigned to the first half, and the communication process is limited to the second half. The management of the period of the first half and the second half is the main of the system controller 10.
This is performed by the CPU, and as shown in FIG. 2, the system controller 10 has a timer for managing the period.

It is not necessary to limit the period of the first half to V / 2, and it is sufficient to set the time required for the processing of the first half and the time required for the processing of the second half. For example, since the time required for the servo lock determination processing and the phase relationship determination processing described above is about 4 ms, the first half period may be shorter when only these processings are taken into consideration.

As shown in FIG. 4, this still video
In the camera system, the following processing is performed during the first half of 1V. That is, based on the key scan process of the power lock 16, the mode switches 11 to 14, the shutter release button 15 and the like in the system control device 10, such as the servo lock determination process in the recording control device 70 described above. Controller 30,7
Message edit processing including command creation for 0, data collection processing of measurement data etc. in other control devices 30, 70, etc.
Based on this, message edit processing and other processing are performed. In the latter half of 1V, in addition to communication processing,
The control devices 10, 30, 70, etc. execute commands associated with communication and perform other processing.

Since the communication processing is limited to the latter half of 1V as described above, it is necessary to do this quickly. 1V for message editing
By allocating to the first half of the above, it is not necessary to perform processing such as message editing during the communication processing of the second half, so that sufficient communication is possible even in a short time.

As shown in FIG. 6, editing of a message is performed by storing in a first-in-first-out (FIFO) buffer addresses, commands, and data to be transmitted in the order in which they are transmitted. Figure 6 shows the system controller
10 shows a telegram created when the shutter release button 15 is pressed (when the signal of the switch S1 is input). The main CPU of the system controller 10 starts the key scan process at the time of rising of the vertical reference signal VD.
When it is found that the switch S1 of the shutter release button 15 is turned on by this key scan processing,
The photometric processing for the exposure control and the distance measurement for the focusing control in the photographing control device 30 (distance measurement to the subject)
In addition to instructing the start of processing, the recording controller 70 must be instructed to start the disk motor 3. Therefore, the main CPU responds to the detection of the switch S1 being turned on, as shown in FIG. The address of the device 70 and the command to start the disk motor (both consist of 8 bits) are input in the order of sending to the FIFO buffer.

If the above processing is completed in the first half of 1V, in the latter half of 1V, the main CPU responds to the interrupt from the timer,
The addresses and commands stored in the buffer can be sequentially transmitted to the line of the output signal So according to the communication flow described later, and the communication processing can be performed quickly.

In this way, in response to the command given from the system control device 10, the execution process of the command is performed in the second half of 1V in each of the control devices 30, 70 and the like. For example, when the recording controller 70 receives a disk / motor start command from the system controller 10, the sub CPU of the controller 70 outputs a drive command for the motor 3 to the servo control circuit 80.

It goes without saying that, in the first half of 1V, the other control devices 30, 70, etc. also collect the data to be sent to the system control device 10, and edit the message containing the data into the FIFO buffer.

The output signal So (input signal Si) includes any of address, command and data. That is, the signal So sent in one signal sending process consists of 8 bits and corresponds to any one of the address, command, and data. Therefore, it must be possible to distinguish whether the transmitted signal So is an address, a command, or data.

Referring to FIG. 5, in order to distinguish the address, the command and the data from each other, a predetermined level change is applied or not applied to the signal So prior to the sent address, the command and the date. When signal So includes an address, signal So temporarily falls from H level to L level, then rises to H level, and then falls to L level. Signal So
Signal contains a command, the signal So falls from the H level to the L level. If the signal So contains data, the signal So is H
It is kept at the level.

In order to distinguish such a level change of the signal So from an address, command or data which is the actual content, the address, command or data is serial clock signal SC.
It is sent in synchronization with K.

Whether the content of the signal So is an address or a command,
An interface circuit for distinguishing whether it is data will be described with reference to FIG. Since the circuit shown in FIG. 3 is included in the control device 30 or 70 (or the regenerator 90), the sub CPU 100 is shown, but this circuit is the same as that for the main CPU of the system control device 10. This is true. In this figure, the signal parallel /
Serial (P / S) conversion circuit and serial / parallel (S
/ P) The conversion circuit is omitted.

The serial clock signal SCK is input to the sub CPU 100, counted by the SCK counter (or count program), and the serial clock signal (SC
K) Input to prohibit circuit 101. The SCK prohibiting circuit 101 is, for example, an 8-bit counter, and its output becomes L level while counting the serial clock signal SCK, and otherwise it generates H level output.
The output of the SCK inhibition circuit 101 is input to the AND gate 102.

If the output of the SCK inhibit circuit 101 is H level, the output signal So
(Input signal Si) passes through the AND gate 102 and is input to the flip-flops 103 and 104. Flip-flop 103 has signal So
Is detected and the output Q is set to H level, and the flip-flop 104 detects the falling edge of the signal So and sets its output Q to H level. The outputs Q of these flip-flops 103 and 104 are input to the sub CPU 100. Let these input signals be F1 and F2, respectively.

Therefore, if the signal So is input and there is a change in the level, this level change is caused by the flip-flop 103 or 104
Or detected by both. Next, when the substance of the signal So (address, command, data) is input, the serial clock signal SCK is also input, so that the output of the prohibition circuit 101 becomes L level, the AND gate 102 is closed, and the flip-flops 103 and 104 are closed. The state is retained as it is. The input serial clock signal SCK is counted by the SCK counter.

FIG. 7 shows the identification processing of the signal So by the sub CPU (and the main CPU). When the SCK counter counts 8 (step 201), the levels of the output signals of the flip-flops 103 and 104, that is, the states of the inputs F1 and F2 are checked (step 202). When these inputs F1 and F2 are both at the H level (F1 = 1, F2 = 1), the signal So includes the rising edge and the falling edge.
Is determined to include an address. When the input F1 is L level and F2 is H level (F1 = 0, F2 = 1), the signal So
Contains a falling edge, it is determined to be a command. If both inputs F1 and F2 are at L level (F1 = 0, F2 = 0), it is determined to be data.

Of course, the same function as the interface circuit shown in FIG. 3 can be realized by software of the CPU.

(3) Communication processing Next, referring to FIG. 8, the main CPU of the system controller 10
And the photographing control device 30 and the recording control device 70 (and the reproducing device)
The communication processing procedure with the sub CPU in (90) will be described. The main CPU has the initiative in communication processing.

As described above, when the timer in the system controller 10 starts the time counting operation from the time of the vertical reference signal VD and detects that the latter half of 1V has been reached, the timer gives an interrupt to that effect to the main CPU. The communication process shown in FIG. 8 starts.

The main CPU first checks whether there is a communication request (step 211). There are two types of communication requests. Part 1
One is the sub-C in the FIFO buffer of the main CPU as described above.
This means that the message to be sent to the PU has been edited. The other is that a request REQUEST signal is sent from the sub CPU (an H level signal appears on the request signal line). Sub CPU in the latter case
Means that there is a message (command or data) to be sent from to the main CPU. The request from the sub CPU will be described later. Here, first, the main CP
Described below is the case where a command or data is sent from U to the sub CPU.

The main CPU reads the first address set in the FIFO and sends it as a signal So (step 212). This signal S
As described above, the rising edge and the falling edge are added to o before the address is transmitted.

When the sub CPU also detects that it is in the second half of 1V (sub C
The PU may be provided with a timer, or the timer of the main CPU may give a timer interrupt on a specific line), and the ready signal READY is set to H level (step 231).
When the signal So (Si) including the address is received (step 23)
2) The sub CPU outputs a busy signal ▲ ▼ (sets the ready signal READY to L level) (step 233) and checks whether the address in the received signal matches its own address (step 234). ). If they match, the ready signal READY is set to H level to proceed to the next processing (step 235). If they do not match, the self is not designated and the process returns to the start.

After transmitting the address signal, the main CPU monitors the line of the ready signal and checks whether the line has become the H level (step 213). If the ready signal is not sent within a certain time after the address signal is sent, an error has occurred and the process returns to the start and the same address signal is output again (step 221).

When the ready signal is input, the main CPU reads the command to be sent next from the FIFO buffer, and outputs it by including it in the signal So to which the falling edge is added (step 214).

When the sub CPU receives the signal So including the command (step 236), it generates a busy output (step 23).
7) Execute the given command (step 238).
As described above, the sub CPU starts photometry, starts the motor, and so on. When the command execution is completed, the sub CPU produces a ready output (step 239).

When the H-level ready signal is input, the main CPU sends the next data to be transmitted, if any, as the signal So (steps 215 and 216), and waits for the ready signal to reach the H level again (step 217).

When there is no data to be sent to the sub CPU as in the example shown in FIG. 6, the processes of steps 216 and 217 are skipped and the process returns to the start. Then, the process of reading the next address from the FIFO buffer and transmitting it in the same manner is repeated.

When data is sent from the main CPU to the sub CPU, the sub CPU receives the data (step 240), generates a busy output (step 241), and processes the received data (step 242). . When the data processing is completed, a ready signal is output and the process returns to the start (step 243). Steps 240 to 24 if no data is received
The process of 3 is skipped.

When sending a command or data from the sub CPU to the main CPU, the sub CPU outputs an H level request signal REQUEST. However, as shown in FIG.
Since the request signal line of the regenerator 90 (and the other signal lines are the same) is connected to the same line of the system controller 10 by a wired OR, the main CPU does not know which sub CPU has output the request signal. . Therefore, the main CPU performs communication processing to confirm whether the request signal has been output to all the sub CPUs and what kind of request there is. The outline of the communication processing procedure of the main CPU based on the request signal from the sub CPU is shown in FIG.

The series of processing in FIG. 9 is actually executed by repeating the communication processing shown in FIG. 8 by the number of sub CPUs. The process of FIG. 9 will be described below in relation to the process of FIG. The sub CPUs of the photographing control device 30, the recording control device 70, and the reproducing device 90 are referred to as sub CPU 1, sub CPU 2, and sub CPU 3, respectively.

The main CPU checks if an H level signal appears on the request signal line (corresponding to step 251, step 211 in FIG. 8), and if the request signal is input,
In order to check which sub CPU issued the request, first, a signal So including the address of the sub CPU 1 is output (step 252, corresponding to step 212 in FIG. 8). Sub CPU
1 generates ready output (steps 235, 21 in FIG. 8).
3), the main CPU sends an all-zero command (step 214 in FIG. 8). At the same time, the sub CPU1
When 1 is outputting the request signal, there is a command to be sent to the main CPU, so the command is main
It is sent to the CPU (steps 244 and 245 in FIG. 8). Main CPU
Line between the output signal So and the input signal Si
Since the line is provided, bidirectional simultaneous communication is possible. When the sub CPU1 does not output the request signal, it sends a command to that effect to the main CPU in response to the all-zero command from the main CPU. When the main CPU receives the command from the sub CPU1, it analyzes the contents and stores the result in the memory (step 218 in FIG. 8,
219). In this way, commands are transmitted and received between the sub CPU 1 and the main CPU (step 253), and the main CPU can know whether the sub CPU 1 has issued a request and, if so, the contents thereof. . Sub CPU1
May not make a response to the all-zero command from the main CPU if it has not issued a request. The main CPU determines that the sub CPU1 has not issued a request if there is no response from the sub CPU1 even after a certain time has elapsed after sending the all-zero command.

If sub CPU1 has not issued a request, another sub CP
Because U issued the request, the main CPU is the sub
A signal So including the address of the CPU 2 or the sub CPU 3 is sent to perform the same processing (steps 254 to 257). Since it is possible that two or more sub CPUs issue requests at substantially the same time, the main CPU may proceed to the processing of steps 254 to 257 when it knows that the sub CPU 1 has issued a request.

As described above, the sub CPU that issued the request is identified, and when the content of the request is known, the processing for it is performed. If the sub CPU 1 issues a request, the corresponding processing is performed (steps 258 and 259), and if it is another sub CPU, the processing corresponding to the sub CPU is similarly performed (steps 260 to 263). For example, the sub CPU is the main C
In case of request to send data to PU, sub-CP
U sends data (steps 246 and 247 in Fig. 8), main CP
The process will be performed in which U receives the data (FIG. 8, step 220). When the sub CPU 1 issues a request, the process may proceed from step 253 to step 259 immediately.
In this case, if the request content is related to data transmission, after the command transmission / reception processing shown in FIG. ).

In this embodiment, the communication between the regenerator 90 and the system controller 10 is performed only when the regenerator 90 outputs a request signal. In FIG. 1, the serial transmission line connected to the regenerator 90, the output line of the reproduction still video signal, and the phase pulse PG line are actually bundled to form one cable. Hundreds of playback still video signals
The signal on the serial transmission line is, for example, about 5V, while it is about mV. Therefore, if serial communication is performed while the reproduction still video signal is being transmitted, noise may occur in the reproduction still video signal. When sending a request signal from the regenerator 90 to the system controller 10 to send information, the regenerator
This is the case when there is a key switch input on the 90 side. For example, a forward feed switch, a reverse feed switch, and a track number designation switch. Regenerator only when limited in this way
The serial communication between 90 and the system controller 10 will be performed, and the reproduced video signal will always have noise.
The problem that the quality of the reproduced still image is deteriorated is prevented.

Finally, regarding the overall operation during shooting and recording with a still video camera, especially system controller 10
The communication between the main CPU and the sub CPU of the photographing control device 30 and the recording control device 70 will be mainly described with reference to FIG. In this figure, the load / unload processing of the magnetic head 2, white balance adjustment, etc. are omitted.

When the first switch S1 of the shutter release button 15 is pressed, this is the main CPU of the system controller 10.
Is detected by the sub CPU 1 of the photographing control device 30 and the motor start command is given to the sub CPU 2 of the recording control device 70. As a result, the photographing control device 30 starts the photometry processing and the distance measurement processing. The photometric processing is performed for each 1V in synchronization with the vertical reference signal VD, and if the photometric value is within the shooting range, a message indicating that the photometric value is OK is displayed on the sub CPU1.
Given to the main CPU from. Further, focusing control of the imaging lens system 32 is performed based on the distance measurement data, and when the focusing is performed correctly, the release OK is sent from the sub CPU 1 to the main CPU. Since the recording control device 70 activates the disk motor 3, the rotation speed of the motor 3 increases. The control device 70 performs a servo lock determination process as to whether or not the rotation speed of the motor 3 has reached a predetermined value.

When it is determined that the disk motor 3 is servo-locked, the sub CPU 2 of the recording control device 70 notifies the main CPU of the system control device 10 to that effect. The recording control device 7
The sub CPU 2 of 0 outputs a reset signal to the signal processing circuit 71 and controls so that the vertical reference signal VD has the above-described predetermined phase relationship with the phase pulse PG. Even after this, the recording control device 70 performs the servo lock determination process and the VD control immediately after the vertical reference signal VD is generated (first half of 1V) as described above.
And the phase relationship between PG and PG are determined, and the result is notified to the main CPU.

When the main CPU detects that the second switch S2 of the shutter release button 15 is turned on, shooting is performed based on the servo lock determination result, the phase relationship determination result, and other information notified from the recording control device 70. It judges whether the condition is satisfied, and if it is satisfied, the photographing control device
Give a release command (shooting start command) to 30 sub CPUs 1. In response to this, the sub CPU 1 of the control device 30 determines the aperture value and the shutter speed based on the final photometric value, and drives and controls the aperture 33 so that the determined aperture value is achieved. Then, when the photographing preparation is completed, the control device 30 starts the photographing process. During this time, if the main CPU determines that the shooting conditions are no longer satisfied, the main CPU gives a shooting prohibition command to the shooting control device 30.

The photographing process in the photographing control device 30 is performed by the sub-unit of the control device 30.
The CPU 1 starts by generating a shutter open signal TS having a pulse width corresponding to the shutter speed determined. The shutter 36 is driven so that the front curtain of the shutter 36 runs at the time of rising of the signal TS and the rear curtain runs at the time of falling of the signal TS, and the imaging device 37 is exposed. After that, the winding operation of the shutter is performed.

The shutter open signal TS is also input to the system controller 10 through a line not shown in FIG. 1, and when the main CPU detects the trailing edge of the signal TS, it gives a recording start command to the recording controller 70. In the control device 70, during the period of 1V or 2V starting from the next signal VD, the still video signal read from the imaging device 37 is FM-modulated and then recorded in the video floppy 1. The one shown in FIG. 10 is an example of frame recording, so that the still video signals of the first field and the second field are read and written over the period of 2V.

When this recording process ends, the sub CPU 2 of the control device 70 notifies the main CPU of the completion of recording. After this,
A head feed command is given to the sub CPU2 from the main CPU,
Under the control of the sub CPU 2, the magnetic head 2 is transferred to the next track to be recorded. When the transfer of the magnetic head is completed, the sub CPU 2 notifies the main CPU to that effect. Further, when the photographing control device 30 completes the winding of the shutter, the sub CPU 1 notifies the main CPU to that effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing the system configuration of a still video camera. FIG. 2 is a block diagram showing in more detail a state in which the control devices are connected by a serial transmission line. FIG. 3 is a block diagram showing an interface circuit for communication. FIG. 4 is a time chart showing typical signals and basic operations in the still video camera system. FIG. 5 is a waveform diagram showing a serial clock signal and an output signal. FIG. 6 shows the state of message editing in the FIFO buffer. FIG. 7 is a flow chart showing the processing for determining whether the output signal includes an address, a command, or data. FIG. 8 is a flow chart showing communication processing between the main CPU and the sub CPU. Figure 9 shows the main C when there is a request from the sub CPU
It is a flow chart which shows processing of PU. FIG. 10 is a time chart showing the overall operation at the time of shooting with a still video camera. 1 ... Video floppy, 2 ... Magnetic head, 5 ... Phase detector, 10 ... System controller, 30 ... Imaging controller, 70 ... Recording controller, 71 ... Signal processing circuit, 90 ... … Regenerator, 100 …… Sub CPU, 101 …… SCK inhibit circuit, 102 …… AND gate, 103,104 …… Flip-flop.

Front page continued (72) Inventor Yutaka Maeda 2-26-30 Nishiazabu, Minato-ku, Tokyo Fuji Shashin Film Co., Ltd. (72) Inventor Hiroshi Shimatani 2-26-30 Nishiazabu, Minato-ku, Tokyo Shin Fuji Fujisha Within Film Co., Ltd.

Claims (1)

[Claims] 1. A serial transmission line including a serial clock line, a signal output line, a signal input line, a busy signal line, and a request signal line, and at least two communication devices that communicate with each other. Request signal output means for outputting a request signal indicating that one communication device requests communication to the other communication device to the request signal line; and busy signal output means for outputting a busy signal to the busy signal line. The other communication device includes a request signal detecting means for detecting a request signal input from the request signal line, and a busy signal detecting means for detecting a busy signal given from another communication device through the busy signal line. Is equipped, and the device of the communication partner can communicate with the busy signal. In order to recognize whether or not the signal is in such a state, and to distinguish the signal type according to the address, command or data signal type to be transmitted by each communication device, the signal output from the above signal output line is preceded. The signal level is changed according to the presence or absence of a rising edge or a falling edge to be applied and the form thereof, and a transmission signal output means for outputting these signals to the signal output line, and a signal input to the signal input line. A level change detecting means for detecting a level change that appears, and sends and receives an address, a command and data through the signal input line and the signal output line in response to a request signal or in response to a determination of the form of a busy signal, Serial communication system between multiple communication devices.