JPH0743877B2 - Recording / playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In a still video system such as a still video camera, a servo lock determination of a recording medium rotating motor is performed for each synchronization reference signal (VD), and a predetermined number of times is consecutively determined. The recording / reproducing process is permitted when it is determined that the servo lock has occurred. If it is determined that the lock is unlocked even once, the servo lock determination is restarted from the beginning. As a result, a system resistant to mechanical vibration, electrical noise, etc. is realized.

BACKGROUND OF THE INVENTION The present invention relates to recording a predetermined signal on a rotating magnetic, optical or other recording medium in synchronism with its rotation reference phase, and synchronizing from a rotating recording medium to its rotation reference phase. The present invention relates to a recording / reproducing device that reproduces at least one of signals.

A typical example of this type of recording / reproducing apparatus is a video image in which a still image of a subject is developed by a solid-state electronic imaging device, and the output still video signal is FM-modulated and rotated.
There are still video cameras that magnetically record on floppy disks, still reproducing devices that reproduce still video signals from video floppy disks, and devices that have both recording and reproducing functions.

In such a still video signal recording / reproducing apparatus,
One field of the still video signal is recorded / reproduced by one rotation of the video floppy. A reference angular position for recording / reproducing a still video signal in the video floppy is predetermined, and this reference angular position is detected by the phase detector. Then, a synchronization reference signal (vertical synchronization signal or the like) for recording / reproduction having a fixed phase relationship with the phase pulse (reference phase signal) output from the phase detector is created. The main operation of the recording / reproducing apparatus is performed with this reference signal as a reference.

The phase detector detects the magnetic flux leaked from a permanent magnet provided for chucking the video floppy on the spindle of the disk motor. This detection signal is a signal similar to a sine wave of one cycle, and by shaping the waveform of this detection signal, a phase pulse with the center zero-cross point as a reference is created. If there is a disturbance magnetic flux around the phase detector, the above zero-cross point fluctuates. Further, since the phase pulse has a high frequency component, and its rising and falling are important, it is not possible to provide a noise removing circuit such as a low-pass filter in the transmission path of the phase pulse. Weak against magnetic disturbances.

The synchronization reference signal is created by dividing a reference clock having a constant frequency by a dividing cycle. The frequency divider is reset by the phase pulse in order to generate the synchronization reference signal so as to have a predetermined phase relationship with the phase pulse.
Since this reset is an edge trigger, there is a problem that it is easy to malfunction due to noise.

On the other hand, the disk motor that rotationally drives the video floppy is controlled by the servo control circuit so that it accurately rotates at a constant rotational speed. If the rotation speed fluctuates,
Recording / playback of video signals is not performed correctly.

In a recording / playback device that is often carried when used, such as a still video camera, when it is moved, its acceleration acts on the video floppy when it suddenly moves, and the rotation speed of the disk motor. Fluctuates. That is, the rotation control of the video floppy is the movement of the device,
There is a problem that it is weak against vibrations.

SUMMARY OF THE INVENTION A first object of the present invention is to guarantee a correct recording / reproducing operation even if a sudden movement of the apparatus or movement is applied.

A second object of the present invention is to provide a recording / reproducing device that is strong against magnetic and electrical disturbances.

In order to achieve the first object, a recording / reproducing apparatus according to the first invention is a motor for rotating a recording medium, and a servo control circuit for controlling the motor to rotate at a constant rotation speed in synchronization with a phase reference signal. , Phase lock determination means for determining whether or not the motor is rotating in synchronization with the phase reference signal based on the period of the synchronization reference signal having a longer period than the phase reference signal, and the motor is rotating at the constant rotation speed. It is determined to be in a locked state when the speed lock determination means determines whether or not it is in accordance with the cycle of the synchronization reference signal, the phase lock determination means determines phase lock, and the speed lock determination means determines speed lock. The lock state detecting means determines that the lock state is determined by the lock state detecting means a predetermined number of times consecutively in the cycle of the synchronization reference signal. And a control means for permitting recording / reproduction of a signal to / from the recording medium in response to the servo lock determining means determining the servo lock state. It is characterized by having.

Through the first invention and the second invention described below, the recording / reproducing process means a recording process or a reproducing process.

According to the first aspect of the present invention, the recording / reproducing process is performed only when the phase lock determination and the speed lock determination, which are periodically performed, are both determined to be the locked state a predetermined number of times in succession. If it is determined to be in the unlocked state even once, the recording / reproducing process is prohibited, and the process of determining whether the locked state continues for a predetermined number of times is redone in the phase lock determination and the speed lock determination again. In this way, the recording / reproducing operation is prohibited when the rotational speed of the recording medium fluctuates due to an external force applied to the device, so that the recording / reproducing in a good state is always guaranteed.

In particular, according to the first aspect of the invention, two types of determination processing, that is, phase lock determination and speed lock determination, are performed, and a signal is recorded only when both of these determination processes are in a locked state for a predetermined number of times in succession. Since // reproduction is permitted, recording / reproduction in a good state is guaranteed even when the phase lock determination and the speed lock determination are performed in the cycle of the synchronization reference signal.

In order to achieve the second object, the second aspect of the present invention generates and rotates the synchronization reference signal so as to maintain a predetermined phase relationship with the rotation reference phase signal generated at the rotation reference phase of the rotating recording medium. A recording / reproducing apparatus for performing at least one of recording a predetermined signal on a recording medium in synchronization with its rotation reference phase and reproducing from a rotating recording medium in synchronization with its rotation reference phase. The phase reference determination means for determining whether the rotation reference phase signal generated at the rotation reference phase and the synchronization reference signal have a predetermined phase relationship, and the control means performs the phase relationship determination processing by the phase relationship determination means. It is characterized in that at least the recording process is permitted when the item passes.

Therefore, when the phase relationship between the reference phase signal and the synchronization reference signal is changed due to magnetic or electrical disturbance, the recording process is not performed. Recording that includes errors is not performed, and only normal recording will always be executed.

An embodiment in which the present invention is applied to a still video camera will be described in detail below. The present invention is applied to a still video signal reproducing device, a device having both magnetic recording and reproducing functions, and other magnetic signals. It goes without saying that the present invention can also be applied to a recording / reproducing device, a recording / reproducing device for an optical or magneto-optical recording medium, and the like.

Description of Embodiments (1) System Configuration FIG. 1 shows the system configuration of a still video camera.

The still video camera is controlled by three control devices, that is, a system control device 10, a photographing control device 30, and a recording control device 70. Each of these control devices 10, 30, and 70 is a memory (RAM, RO, etc.) that stores a CPU (for example, a microprocessor), its program and necessary data.
M, etc.) and necessary interface circuits. The CPU of the system controller 10 is the main CPU, and controls the overall operation of the still video camera. The CPU of the photographing control device 30 and the recording control device 70 is a sub C
It is a PU and operates according to commands from the main CPU. The photographing control device 30 controls photographing such as focusing, aperture, shutter speed, and zoom. The recording control device 70 is used for driving the disk motor 3, loading / unloading the magnetic head 2, transferring the magnetic head 2, and the like.
The control for recording the video signal to the floppy 1 is performed. These control devices 10, 30, 70 are connected to each other by a serial transmission line (including five lines as described later), and communicate with each other at a predetermined timing described later.

A regenerator (reproduction adapter) 90 is also connectable, and this regenerator 90 demodulates the video signal read from the video floppy 1 and converts it into a color video signal of NTSC format and outputs it. The regenerator 90 also includes a CPU and memory, and this CPU is a sub-CP for the main CPU.
Positioned as U.

The still video camera is provided with a bucket that can be opened and closed, and the video floppy 1 is inserted into the opened bucket, and when the bucket is closed after that, the video floppy 1 moves to the disk motor 3 It is chucked on the spindle.

The video floppy 1 is provided with a plurality of tracks (for example, 50 tracks) (for example, a track pitch of 100 μm) concentrically, and one field or one frame (one frame) is provided for one or two tracks depending on the photographing process. The FM-modulated color video signal (including the luminance signal, the color difference signal, etc.) is magnetically recorded. The 50 tracks concentrically provided on the magnetic recording surface of the video floppy 1
The track numbers from No. 1 to No. 50 are attached in order from the outer one. The home position HP (origin position or standby position) is outside the No. 1 track, and the end position EP is inside the No. 50 track.

The system controller 10 has a power switch 16, various modes,
Switch input signals for switches 11 to 14, shutter release button 15, etc., detection signal of bucket switch 7 for detecting the open / closed state of the bucket containing the video floppy (and presence of video floppy if necessary), video The detection signal of the dew condensation sensor 8 for measuring the humidity in the vicinity of the installation location of the floppy 1 is input. The modes to be set include a frame / field mode indicating frame recording or field recording, a skip mode in which an empty track that is not recorded in the video floppy is provided, and an edit mode for performing recording on an empty track. . These set modes, track N to record
o., other information is displayed on the liquid crystal display 21. The display 21 is connected to the system controller 10 by a bus.

In addition, the buzzer 22 alarms when dew condensation is detected or other abnormal conditions occur. Condensation detection may be displayed on the display 21.

The shutter release button 15 is a two-step stroke type, and when the first step is pressed, the switch S1
By the second step of further pressing, the switches S2 are turned on. When the switch S1 is turned on, the disc motor 3 is driven. After this, when the switch S2 is turned on, shooting and recording are performed.

The imaging optical system includes a zoom lens system 31, an imaging lens system 32 for forming a subject image, a diaphragm 33, and a beam splitter for deflecting a part of incident light to enter the photometric element 51.
34, an infrared cutoff filter 35, and a shutter 36. The illuminance detection signal of the photometric element 51 is input to the photographing control device 30 via the logarithmic amplifier 52. A process of calculating an aperture value and a shutter speed based on the incident light illuminance detected by the photometric element 51 by the photographing control device 30, control of the aperture 33 based on the determined aperture value, and a shutter 36 based on the shutter speed also determined. Open / close control is performed.
The diaphragm 33 is opened and closed by a diaphragm motor 48 driven by a driver 47. A switch 49 for detecting the limit position of opening and closing of the diaphragm 33 is also provided. Shutter
Unlatch the first and second curtains of 36, and wind them up by the driver
It is performed by a shutter drive device that includes a shutter motor 54 driven by 53. The rotation angle of the motor 54 is detected by the rotary encoder 55 and fed back to the device 30.

The color detection signal of the color sensor 61 is subjected to predetermined processing in the white balance processing circuit 62 and then input to the device 30. This white balance data is used for controlling the amplification gain of the R, G, B signals in the variable gain amplification circuit of the signal processing circuit 71 described later.

In order to measure the distance to the subject, an infrared light emitting diode 63 and a light receiving element 64 for receiving the reflected light are provided,
Based on the output signal of the light receiving element 64, the focusing processing circuit 65 obtains data representing the distance to the subject. Using this data, the auto focus motor 46 is driven via the driver 45 under the control of the device 30, and focusing control is performed.

In addition, a tele or wide
In response to the signals from the switches 38 and 39, the control device 30 drives the zoom motor 42 via the driver 41 to set a predetermined magnification. The rotation angle of the motor 42 is detected by the rotary encoder 43 and fed back to the device 30.

On the focal plane of the image pickup optical system, a solid-state electronic image pickup device 37 for three primary colors including a two-dimensional image pickup cell array such as CCD is arranged. The image data stored in the image pickup device 37 when the shutter 36 is opened is read out as a serial still video signal (R, G, B) in synchronization with the vertical and horizontal synchronizing signals given from the signal processing circuit 71. And input to the signal processing circuit 71.

The signal processing circuit 71 includes an oscillating circuit as described later in detail,
A vertical reference signal VD and a reference clock signal are created from the output signal of this oscillation circuit and output. The vertical reference signal VD is supplied to the system controller 10, the photographing controller 30, and the recording controller 7.
It is set to 0 and serves as a reference for operation timing in these devices. The reference clock signal is given to the servo control circuit 80. As will be described later, a phase pulse PG representing the reference phase of rotation of the video floppy 1 is given to the signal processing circuit 71, the system controller 10, the recording controller 70 and the regenerator 90. In the signal processing 71, the vertical reference signal VD is adjusted so as to maintain a constant phase relationship with the phase pulse PG by a reset signal provided from the recording control device 70.
The signal processing circuit 71 also generates vertical and horizontal synchronizing signals having a fixed phase relationship with the phase pulse PG.

The signal processing circuit 71 further includes a preamplifier circuit for the input still video signals (R, G, B), a variable gain amplifier circuit (white balance adjustment circuit), and a process matrix circuit. A luminance signal Y and two color difference signals RY and BY are created in the process matrix circuit. These color difference signals R-Y and B-Y are then applied to the line sequential circuit 7
Line-sequentially every 1H at 2. The luminance signal Y and the line-sequential color-difference signal are FM-modulated in different frequency bands in FM modulation circuits 73 and 74 via a pre-emphasis circuit (not shown), and combined in a combining circuit 75.

It is also possible to record the additional information signal on the track of the floppy disk 1. The additional information signal means an acoustic signal (representing voice such as narration, music, etc.) and a display signal (representing character information, for example). This additional information signal is input to the signal processing circuit 71 from an input device (not shown) such as a microphone, converted into a predetermined format, and output to the line of the luminance signal Y. The additional information signal S may be superposed on the luminance signal Y, or may be output alone when only this signal S is recorded on a predetermined track of the video floppy 1.

Furthermore, data multiplex recording is also possible for video floppy. This multiple recorded data includes initial bits, field / frame data, track address (N
o.) Data, date data and user data. These data are given from the system controller 10, and the signal processing circuit 71 uses DPSK (Differential Phase).
The signal is modulated by the shift keying), synthesized by the synthesizing circuit 76 together with the above FM modulated video signal, and input to the recording / amplifying circuit 77.

A magnetic head 2 for writing a still video signal of an imaged subject on a predetermined track of a video floppy 1
(The two are provided at intervals so as to be capable of frame recording so as to be located in adjacent tracks to each other.) Are movably supported in the radial direction of the video floppy 1 by the transfer drive control device thereof and in the same direction. Transfer controlled. The transfer drive controller includes a step motor 87 and its driver 86. The recording control device 70 gives instructions to the transfer drive control device about the transfer direction and transfer amount of the magnetic head 2. A home position switch 6 for detecting that the magnetic head 2 has reached the home position HP is also provided, and a detection signal of this switch 6 is given to the recording control device 70.

A head loading device is provided in order to prevent the floppy from being imprinted due to the magnetic head 2 coming into contact with the stopped video floppy 1 for a long time. This device includes a head load solenoid 85 and its driver 84, and is under the control of the recording control device 70 only during recording or reproduction (video floppy 1).
So that the magnetic head 2 comes into contact with the video floppy 1 only when the power is turned on, and apart from the floppy 1 at other times.
The magnetic head 2 is displaced (moved back and forth).

In order to improve the touching between the magnetic head 2 and the rotating video floppy 1, a regulation plate (not shown) is provided on the opposite side of the magnetic head 2 across the video floppy 1. Also, in the core of Video Floppy 1,
Detects the magnetic flux leakage from the permanent magnet for chucking
A phase detector 5 that outputs a phase detection signal when the floppy 1 reaches a predetermined angular position is close to it. The output detection signal of the phase detector 5 is given to the phase pulse generation circuit (which is composed of the waveform shaping circuit, the zero-cross detection circuit, etc. as described above) 82, and after the predetermined processing is applied thereto, the phase pulse PG Is output as
0, 70, 90, and input to the circuit 71 and the recording gate circuit 78. One phase pulse PG will be generated for each revolution of the video floppy 1.

The disk motor 3 is driven by its driver 81. The rotation speed of the disk motor 3 is detected by the frequency generator 4, and the detection signal of the frequency output from the frequency generator 4 and proportional to the rotation speed of the motor 3 is input to the servo control circuit 80. The servo control circuit 80 controls the motor 3 to rotate at a constant speed (for example, 3,600 rpm) at a constant speed based on the reference clock signal input from the signal processing circuit 71 and the frequency detection signal input from the detector 4. . The servo control circuit 80 also starts and stops the motor 3 in response to a command from the recording control device 70.

The still video signal and the like amplified by the recording amplifier circuit 77 is input to the recording gate circuit 78. Then, when a recording command is given from the recording control device 70, this gate circuit 78 opens its gate at the timing of the phase pulse PG to be input until the next phase pulse is input. As a result, the video signal or the like is given to the magnetic head 2, and the still video signal or the like is recorded on a predetermined track of the video floppy 1. This recording is made only during one revolution of the video floppy 1. This is the case for field recording. In the case of frame recording, the gate circuit 78 opens its gate for two revolutions of the video floppy 1, and the first rotation of the video floppy 1 causes one head 2 to record a video signal of the first field on one track. But the second
By the second rotation, the other head 2 records the video signal of the second field on the adjacent track.

It is also possible to reproduce the video signal from the video floppy 1 by the magnetic head 2. The FM-modulated video signal and the like read from the magnetic head 2 is similarly amplified by the amplifier circuit 77 via the gate circuit 78 and is given to the envelope detection circuit 83 and the regenerator 90. This reproduction is used for track search processing not only in the reproduction mode but also in the recording mode.

The envelope detection circuit 83 is a read signal of the magnetic head 2,
That is, it is a detection circuit that detects the envelope of the FM-modulated video signal recorded on the track of the video floppy 1 and outputs a voltage signal corresponding to it.
Includes / D (analog / digital) conversion circuit. The voltage signal representing the envelope is converted into a digital quantity by an A / D conversion circuit, converted into a bit digital signal representing, for example, a quantization level of 256, and input to the recording controller 70.

The envelope detection signal indicates whether the track on the video floppy 1 is unrecorded or recorded.
70 is used to determine (track search process). If the level of the detection signal does not reach the predetermined threshold level when the magnetic head 2 is transported across the track, the track is unrecorded, and if it reaches the threshold level, The track has been recorded.

If necessary, the envelope detection signal is also used in the recording check process. The recording check process is a process of recording the photographed still video signal on the predetermined track by the magnetic head 2 as described above, and then checking whether or not this recording is actually performed. If it is above the threshold level, it is judged that recording has been performed.

(2) Communication System FIG. 2 shows a specific example of a serial transmission line that connects the system controller 10, the photographing controller 30, and the recording controller 70 (and the regenerator 90). This serial transmission line is composed of five lines, and a serial clock signal SCK, output signal S _o , input signal S _i , busy (ready) signal ▲ ▼ (READY) and request signal (REQUEST) are provided on each line. Each is transmitted. Controller 10,30,7
Wired OR each line leading to 0 (and regenerator 90)
Are tied to each other. For example, the system controller 10
The line of the serial clock signal SCK of is connected to the serial clock signal lines of the other control devices 30, 70 (and the regenerator 90) by wired OR. The same applies to the other lines.

The serial clock signal (SCK) is the system controller 10
It is used to synchronize the signals output from and communicated with. The output signal S _o of the system controller 10 becomes the input signal S _i of the other controllers 30, 70 (and the regenerator 90), and conversely the output signal S _o of the controllers 30, 70 (and the regenerator 90) is controlled. It becomes the input signal S _{i of the} device 10. The busy signal ▲ ▼ and the request signal REQUEST are output from the photographing control device 30 and the recording control device 70 (and the reproducing device 90) and given to the system control device 10. An address is assigned to each of the control devices 10, 30, 70 (and the regenerator 90) for designating them in the communication process.

An example of an interface circuit for communication in these control devices 10, 30, 70 (and regenerator 90) is shown in FIG. Prior to the description of this circuit, the communication method and the form of the signal S _o will be described with reference to FIGS. 4 and 5.

As mentioned above, in a still video camera,
The phase pulse PG is generated every one rotation of the video floppy 1. A still video signal for one field is video floppy 1 between two adjacent phase pulses PG.
Recorded in. Therefore, the basic operation of the still video camera is performed in synchronization with the phase pulse PG as a reference (hence the vertical reference signal VD as will be seen later).

FIG. 4 shows a time chart of basic signals in a still video camera system. The vertical reference signal VD and the vertical synchronizing signal Vsync are generated by the signal processing circuit 71 as described above, but these signals VD and Vsync are phase pulses.
It is controlled so as to be synchronized with the PG while maintaining a predetermined phase relationship. For example, the vertical reference signal VD is 4H (1H
Is a horizontal scanning period), and the vertical synchronization signal Vsync is generated with a delay of 7H. The period of these signals PG, VD, Vsync is equal to 1 V (1/60 sec = 16.6 ms) in the vertical scanning period.

Communication between the control devices 10, 30, 70 (and the regenerator 90) is also performed with the vertical reference signal VD as a reference.

On the other hand, important processing that is performed at a timing based on the vertical reference signal VD is processing for determining whether the vertical reference signal VD has a predetermined phase relationship with the phase pulse PG (phase relationship determination processing), and servo control. There is a determination process (servo lock determination process) of whether or not the rotation speed of the disk motor 3 whose rotation is controlled by the circuit 80 has reached a predetermined rotation speed and is maintained at that rotation speed. These phase relationship determination processing and servo lock determination processing are performed by the recording control device 70.
It is executed by the sub CPU of, but these processes require extremely high precision (ie,
Since the measurement processing of a short time interval is included as will be described later in detail), the sub CPU needs to concentrate on these processings. Therefore, it is preferable to avoid communication processing with the main CPU of the system controller 10 during the time when the sub CPU is performing these processes. Generally, a high priority is given to an interrupt in communication processing, so if an interrupt for communication is entered and the sub CPU proceeds to the interrupt processing routine while the sub CPU is performing servo lock determination processing, etc. This is because there is a possibility that high accuracy may not be maintained in the servo lock determination processing and the like.

Therefore, as shown in Fig. 4, it starts from the vertical reference signal VD.
The period of 1V is divided into the first half and the second half (for example, both are V / 2 periods), the phase relation determination processing, the servo lock determination processing, etc. are assigned to the first half, and the communication processing is limited to the second half. There is. The management of the periods of the first half and the latter half is performed by the main CPU of the system controller 10, and the system controller 10 is provided with a timer for managing the period as shown in FIG.

It is not necessary to limit the period of the first half to V / 2, and it is sufficient to set the time required for the processing of the first half and the time required for the processing of the second half. For example, since the time required for the servo lock determination process and the phase relation determination process is about 4 ms, as will be shown later,
If only these processes are considered, the first half period may be shorter.

As shown in FIG. 4, in the still video camera system, the following processing is performed in the first half period of 1V. That is, the phase control determination processing, the servo lock determination processing, etc. in the recording control apparatus 70 described above, the key scan processing of the power switch 16, various mode switches 11 to 14, the shutter release button 15, etc. in the system control apparatus 10, A message edit process including command creation for the control devices 30 and 70 based on the key scan process, a data collection process of measurement data and the like in the other control devices 30 and 70, a message edit process based on the data collection process, and other processes are performed. During the latter half of 1V, in addition to the communication processing, the control devices 10, 3070, etc. execute commands associated with the communication and other processing.

Since the communication processing is limited to the latter half of 1V as described above, it is necessary to do this quickly. 1V for message editing
By allocating to the first half of the above, it is not necessary to perform processing such as message editing during the communication processing of the second half, so that sufficient communication is possible even in a short period.

As shown in FIG. 6, editing of a message is performed by storing in a first-in-first-out (FIFO) buffer addresses, commands, and data to be transmitted in the order in which they are transmitted. Figure 6 shows the system controller
10 shows a telegram created when the shutter release button 15 is pressed (when the signal of the switch S1 is input). The main CPU of the system controller 10 starts the key scan process at the time of rising of the vertical reference signal VD.
When it is found that the switch S1 of the shutter release button 15 is turned on by this key scan processing,
The photometric processing for the exposure control and the distance measurement for the focusing control in the photographing control device 30 (distance measurement to the subject)
In addition to instructing the start of processing, the recording controller 70 must be instructed to start the disk motor 3. Therefore, the main CPU responds to the detection of the switch S1 being turned on, as shown in FIG. The address of the device 70 and the command to start the disk motor (both consist of 8 bits) are input in the order of sending to the FIFO buffer.

If the above processing is completed in the first half of 1V, in the latter half of 1V, the main CPU responds to the interrupt from the timer,
The addresses and commands stored in the buffer can be sequentially transmitted on the lines of the output signal S _o according to the communication flow described later, and the communication processing can be performed quickly.

In this way, in response to the command given from the system control device 10, the execution process of the command is performed in the second half of 1V in each of the control devices 30, 70 and the like. For example, when the recording controller 70 receives a disk / motor start command from the system controller 10, the sub CPU of the controller 70 outputs a drive command for the motor 3 to the servo control circuit 80.

It goes without saying that, in the first half of 1V, the other control devices 30, 70, etc. also collect the data to be sent to the system control device 10, and edit the message containing the data into the FIFO buffer.

The output signal S _o (input signal S _i ) includes any of address, command and data. That is, the signal S _o sent in one signal sending process consists of 8 bits and corresponds to any one of address, command, and data. Therefore,
It must be possible to distinguish whether the signal S _o sent out is an address, a command or a data.

Referring to Figure 5, the address, command, in order to distinguish data mutually and address sent, the command, a predetermined level change in prior signal S _o to the data is given or not given. When signal S _o includes an address, signal S _o once falls from H level to L level, then H level rises, and then falls to L level. Signal S _o
Signal contains a command, signal S _o falls from H level to L level. If the signal S _o contains data, the signal S _o is H
It is kept at the level.

In order to distinguish such a level change of the signal S _{o from} an address, command or data which is the actual content, the address, command or data is serial clock signal SC.
It is sent in synchronization with K.

Whether the content of signal S _o is an address or a command,
An interface circuit for distinguishing whether it is data will be described with reference to FIG. Since the circuit shown in FIG. 3 is included in the control device 30 or 70 (or the regenerator 90), the sub CPU 100 is shown, but this circuit is the same as that for the main CPU of the system control device 10. This is true. In this figure, the signal parallel /
Serial (P / S) conversion circuit and serial / parallel (S
/ P) The conversion circuit is omitted.

The serial clock signal SCK is input to the sub CPU 100, counted by the SCK counter (or count program), and the serial clock signal (SC
K) Input to prohibit circuit 101. The SCK prohibiting circuit 101 is, for example, an 8-bit counter, and its output becomes L level while counting the serial clock signal SCK, and otherwise it generates H level output.
The output of the SCK inhibition circuit 101 is input to the AND gate 102.

If the output of the SCK inhibit circuit 101 is H level, the output signal S
_{The o} (input signal S _i ) passes through the AND gate 102 and is input to the flip-flops 103 and 104. Flip-flop 103 is a signal
S by detecting the rising edge of _o is intended to its output Q to H level, the flip-flop 104 detects the falling edge of the signal S _o to the output Q to the H level. The outputs Q of these flip-flops 103 and 104 are input to the sub CPU 100. Let these input signals be F1 and F2, respectively.

Therefore, if the signal S _o is input and there is a change in the level, this level change is reflected in the flip-flop 103 or 104.
Or detected by both. Next, when the substance of the signal S _o (address, command, data) is input, the serial clock signal SCK is also input, so the output of the prohibition circuit 101 becomes L level, the AND gate 102 is closed, and the flip-flops 103, 104. The state of is retained as it is. The input serial clock signal SCK is counted by the SCK counter.

FIG. 7 shows the process of identifying the signal S _o by the sub CPU (and the main CPU). When the SCK counter 8 counts (step 201), the levels of the output signals of the flip-flops 103 and 104, that is, the states of the inputs F1 and F2 are checked (step 202). When these inputs F1 and F2 are both at the H level (F1 = 1, F2 = 1), the signal S _o includes the rising edge and the falling edge, so the signal S _o is It is determined that the address is included. Input F1 is L level, F
When 2 is at H level (F1 = 0, F2 = 1), since the signal S _o includes the falling edge, it is determined to be a command. If both inputs F1 and F2 are at L level (F
1 = 0, F2 = 0), and it is determined that the data.

Of course, the same function as the interface circuit shown in FIG. 3 can be realized by software of the CPU.

(3) Phase Relation Judgment Processing and Servo Lock Judgment Processing FIG. 8 shows the circuit analysis necessary for explaining the phase relation judgment processing and the servo lock judgment processing in the entire system shown in FIG. It is a thing. The same parts as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Since the above two determination processes are executed by the sub CPU included in the recording control device 70 as described above,
In the figure, the sub CPU 100 is shown in place of the recording control device 70.

The speed / phase control of the disk motor 3 is realized by the feedback control in the servo control circuit 80 as described above. The frequency detection signal P _FG output from the frequency generator 4 is input to the sub CPU 100, one input terminal of the phase comparison circuit 122, and the speed detection circuit 123. Signal processing circuit 71
The reference clock signal transmitted from the oscillating circuit 111 is input to the frequency divider 121, is divided by an appropriate ratio, and is output as the phase reference signal _Pref (for example, frequency 960 Hz). Input to the other input terminal. The phase comparison circuit 122 gives a signal representing the phase difference between the two input terminals P _FG and P _ref to the arithmetic circuit 124. On the other hand, the speed detection circuit 123 creates a signal representing the rotation speed from the input signal P _FG and gives it to the arithmetic circuit 124. The arithmetic circuit 124 creates signals for speed / phase control from these inputs,
Since it is given to the driver 81, servo control is performed so that the rotation speed of the disk motor 3 is maintained at a constant value.

In the signal processing circuit 71, the reference clock signal generated by the oscillator circuit 111 is input to the frequency divider 112, and the vertical reference signal VD is created by dividing the frequency by an appropriate ratio. In order to set the vertical reference signal VD in a constant phase relationship with the phase pulse PG, the phase pulse PG is given as a signal for resetting the frequency divider 112 when the gate of the gate circuit 113 is opened. As will be described later, the gate circuit 113 is opened by the sub CPU 100 (gate enable) when the servo lock state is determined.

The sub CPU 100 has a frequency detection signal P _{FG '} phase reference signal P
_{The ref '} phase pulse PG and the vertical reference signal VD are input, and the sub CPU 100 uses these input signals to perform servo lock determination processing and phase relation determination processing. 4 above
An example of the types of signals is shown in FIG. Here, the phase pulse PG is shown in an inverted state from that shown in FIG.

Next, the servo lock determination process will be described with reference to FIGS. 9 and 10. Servo lock determination processing includes phase lock determination and speed lock determination. The servo lock determination process is performed for each input (interrupt input) of the vertical reference signal VD while the disk motor 3 is rotationally driven. That is, the falling edge r3 of the signal VD (9th
Servo lock determination is started based on the figure). The sub CPU 100 has a servo lock counter for counting the number of times the servo lock is continuously determined, and a servo set when the count value of this counter reaches a predetermined value N (value of 2 or more). A lock flag is provided.

When the disk motor 3 is started, the servo lock determination process is started, and first the servo lock counter and the servo lock flag are cleared (step 211). When there is an interrupt input by the vertical reference signal VD (step 212), phase lock determination is performed (step 213). With reference to FIG. 9, the phase lock determination is falling edge (r3) rising edge of the phase reference signal P _ref immediately after the signal VD (r4)
The falling edge of the immediately following frequency detection pulse P _FG (r
5) The time between and is measured and whether this time is equal to the predetermined time or is within the predetermined time range.

When it is determined that the phase is not locked (NO in step 214), the servo lock counter is cleared (step 217), and the servo unlock process is executed.
That is, the servo lock flag is cleared (step 218) and the process returns to step 212 to wait for the next signal VD interrupt.

When it is determined that the phase is locked (step 214
YES), then speed lock determination is performed (step 2).
15). The speed lock judgment is performed by measuring the time from the falling edge (r6) of the pulse next to the above-mentioned falling edge (r5) of the pulse signal P _{FG to} the falling edge (r7) of the next pulse. This is done by checking whether the time is equal to a predetermined time or is within a predetermined time range.

If it is determined that the speed is not locked (NO in step 216), the servo lock counter and the servo lock flag are cleared (steps 217, 21).
8) Return to step 212.

When it is determined that the speed is locked (step
If YES in step 216), it is determined whether or not the count value of the servo lock counter has reached N (step 219). If not, this counter is incremented by +1 (step 220), and the servo lock counter is reset again. It is checked whether the count value has reached N (step 22).
1). If the count value of this counter has not reached N, the process returns to step 212 to wait for the interruption of the vertical reference signal VD.

In this way, the servo lock counter is incremented when it is determined that the phase is locked and the speed is locked. This counter is cleared if it is determined even once that the phase is not locked or the speed is not locked. Therefore, the count value of the servo lock counter represents the number of times that the servo lock is continuously determined.

If the count value of the servo lock counter reaches N for the first time (YES in step 221), that is, if the phase lock and speed lock determinations have been performed N times consecutively, it is determined that the servo lock state has been reached, and the servo lock processing is performed. Is
That is, the servo lock flag is set (step 222). After this, the process returns to step 212.

Once the count value of the servo lock counter reaches N,
As long as it is determined that the phase is locked and the speed is locked, YES is obtained in step 219, so that the count value of this counter is held as N and the carbo lock flag is kept set. However, even after the count value of the servo lock counter reaches N, if it is determined that the phase is not locked or the speed is not locked, the servo lock counter is cleared and the servo lock flag is also cleared. (Steps 217, 218). If the rotation of the disk motor fluctuates due to external force applied to the still video camera, it may be determined that the servo lock is not established. In such a case, the above process is repeated for each signal VD, and the servo lock counter becomes 1
The servo lock state is not judged unless the count is started from N and N is reached.

Although the procedure of the phase relation determination processing is not particularly shown, referring to FIG. 9, this processing is performed from the rising edge (r1) of the phase pulse PG to the rising edge (r1) of the vertical reference signal VD.
It is performed by measuring the time up to 2) and determining whether the measured time is equal to a predetermined time or within a predetermined range. This phase relation determination processing is performed after the servo lock flag is set.

The time for the servo lock determination process and the phase relation determination process (determination time shown in FIG. 9) is about 4 ms, and as described above, these processes are performed in the first half of the 1V period of VD synchronization. Further, since processing that requires high accuracy, that is, measurement of the time from the rising (falling) edge to the rising (falling) edge of the pulse signal is included, the serial communication is performed in the first half of 1V as described above. No other processing is performed.

FIG. 11 shows a flow in the recording processing of the servo lock judgment and the phase relation judgment processing by the sub CPU 100. This process is also performed by pressing the shutter release button 15 in the first step to turn on the switch S1 and after the disk motor 3 is started, the vertical reference signal VD Is performed for each input of.

First, recording is prohibited (step 231). This is because even if the system controller 10 notifies that the switch S2 has been input by pressing the shutter release button 15 in the second stage, the gate of the recording gate circuit 78 is ignored by the recording controller 70. Does not open, informs the system controller 10 that recording is prohibited and ignores the input by the switch S2, displays the recording prohibition on the display 21, and ignores the input by the switch S2 With buzzer
Shutter release button 15 to warn by breaking 22
If the camera has a lock mechanism, the button 15 is locked so that it cannot be pressed until the second stage.
It may be realized by notifying the recording prohibition to the shutter and not operating the shutter.

Next, the servo lock determination process shown in FIG. 10 is performed (step 232), and this process is continuously executed until the servo lock flag is set. When the servo lock flag is set (YES in step 233), the sub CPU 100 opens the gate 113 only for the 1V period, and the next phase pulse PG
The frequency divider 112 is reset by and the generated vertical reference signal VD is set so as to have a constant phase relationship with the phase pulse PG (with a time difference of 4H shown in FIG. 4) (step
234). Then, it is checked by the above-mentioned phase relation processing whether or not the above-mentioned fixed relation is established (step 235). Step 232 if there is no fixed relationship
Then, the same operation is repeated from the servo lock judgment processing.

If the vertical reference signal VD and the phase pulse PG have the above-described fixed relationship (this is called phase lock) (step 236), since the servo lock has already been achieved, it becomes possible to record and record. Allow recording (step 23)
7). That is, the above-mentioned recording prohibition is lifted. For example, the system controller 10 is notified that recording is permitted.

Then, as long as the disk motor 3 is rotationally driven (step 238), the servo lock determination process and the phase relationship determination process are repeated for each interruption of the vertical reference signal VD (steps 239 to 242). When the servo lock state is lost or the phase lock state is lost, the process returns to step 231, and the recording prohibition process is performed again.

As described above, since the recording is performed only in the servo lock state and the phase lock state, the still video signal shot at the correct recording speed is recorded at the correct position of the video floppy 1.

[Brief description of drawings]

FIG. 1 is a block diagram showing the system configuration of a still video camera. FIG. 2 is a block diagram showing in more detail the state in which the control device continues on the serial transmission line. FIG. 3 is a block diagram showing an interface circuit for communication. FIG. 4 is a time chart showing typical signals and basic operations in the still video camera system. FIG. 5 is a waveform diagram showing a serial clock signal and an output signal. FIG. 6 shows the state of message editing in the FIFO buffer. FIG. 7 is a flow chart showing the processing for determining whether the output signal includes an address, a command, or data. FIG. 8 is a block diagram specifically showing a circuit portion necessary for the servo lock determination and the phase relation determination processing, extracted from the system configuration diagram of FIG. FIG. 9 is a time chart for explaining the servo lock determination and phase relation determination processing. FIG. 10 is a flow chart showing the details of the phase lock / speed lock determination processing of the disk motor. FIG. 11 is a flow chart showing the flow of recording processing of servo lock determination and phase relation determination processing. 71 ... Signal processing circuit, 80 ... Servo control circuit, 82 ... Phase pulse generation circuit, 100 ... Sub CPU, 112 ... Frequency divider.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshio Nakane 2-26-30 Nishiazabu, Minato-ku, Tokyo Inside Fuji Shashin Film Co., Ltd. (72) Hiroshi Shimatani 2-26-30 Nishiazabu, Minato-ku, Tokyo Fuji Shashin Film Co., Ltd. (56) Reference JP-A-63-74165 (JP, A) JP-A-61-104465 (JP, A) JP-A-62-273670 (JP, A) Actual development Sho-55- 15696 (JP, U)

Claims (2)

[Claims] 1. A motor for rotating a recording medium, a servo control circuit for controlling the motor to rotate at a constant number of revolutions in synchronization with a phase reference signal, and the motor rotates in synchronization with the phase reference signal. Phase lock determining means for determining whether or not the motor is rotating at the constant rotation speed by the period of the synchronous reference signal having a longer period than the phase reference signal, and speed for determining whether or not the motor is rotating at the constant rotation speed Lock determination means, phase lock determination means determines phase lock,
And a lock state detecting means for determining a lock state when the speed lock determining means determines a speed lock, and a lock state for a predetermined number of times consecutively in the cycle of the synchronization reference signal. A servo lock determining means for determining a servo lock state in response to the request, and a control means for permitting recording / reproducing of a signal on the recording medium in response to the servo lock determining means determining the servo lock state; Recording / reproducing apparatus equipped with. 2. The synchronization reference signal is generated so as to maintain a predetermined phase relationship with a rotation reference phase signal generated at the rotation reference phase of the rotating recording medium, and is synchronized with the rotation reference phase of the rotating recording medium. In a recording / reproducing apparatus that performs at least one of recording a predetermined signal and reproducing from a rotating recording medium in synchronization with the rotation reference phase, a rotation reference phase signal generated at the rotation reference phase. A phase relationship determining means for determining whether or not there is a predetermined phase relationship with the synchronization reference signal, and at least the recording processing is permitted when the control means passes the phase relationship determining processing by the phase relationship determining means. The recording / reproducing apparatus according to claim (1).