JPH0727012B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a circuit configuration for testing a semiconductor integrated circuit.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit. In the figure, 1 is a main circuit of a packaged semiconductor integrated circuit, which has an input pad 2 and an output pad 3. Four
Is a main power supply voltage supply terminal for supplying a power supply voltage to the main circuit 1 from outside the semiconductor integrated circuit.

Next, the operation of performing the burn-in test of the main circuit 1 will be described. The semiconductor integrated circuit is placed under a predetermined temperature condition in a thermostatic chamber, and a test signal is supplied to the input pad 2 from a signal generator (not shown) outside the semiconductor integrated circuit. A signal is output from the output pad 3 according to the test signal. A burn-in test is performed by measuring this output signal and determining whether it is within the standard value.

[Problems to be Solved by the Invention]

The conventional semiconductor integrated circuit is configured as described above, and when performing a burn-in test, a constant temperature bath having a test signal generator is used. In this case, there is a problem that the burn-in test of many semiconductor integrated circuits is limited within the volume of the constant temperature oven. In addition, different input signal patterns must be created for each product type, and there is a problem that the input signal patterns that can be generated by the test signal generation circuit are limited. In addition, one packaged semiconductor integrated circuit occupies a large volume, and the package shape of the semiconductor integrated circuit is different for each product type, and it is necessary to provide a burn-in test dedicated substrate for each product type in the constant temperature bath. When the burn-in test is performed and other varieties are not tested, there is also a problem that the efficiency of use of the constant temperature bath is poor.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor integrated circuit having a circuit configuration capable of performing a test in a wafer state.

[Means for Solving the Problems]

A semiconductor integrated circuit according to the present invention has an input unit, an output unit, and a power supply voltage input unit, operates when a power supply voltage is applied to the power supply voltage input unit, and responds to a signal to the input unit. A semiconductor integrated circuit having a main circuit for outputting a signal from the output section, wherein an input pad connected to the input section, an output pad connected to the output section, and a power supply voltage input section of the main circuit. A connected first power supply voltage supply terminal, a second power supply voltage supply terminal connected to the power supply voltage input section of the main circuit, a second power supply voltage supply terminal and a power supply voltage input section of the main circuit And a second switching means which is provided between the signal path of the second power supply voltage supply terminal and the second switching means and which conducts in response to the power supply voltage to the second power supply voltage supply terminal. In response to the power supply voltage to the power supply voltage supply terminal, The second power source voltage supply terminal is provided on the signal path between the signal generating means for applying a predetermined test signal to the input section of the main circuit, and the signal generating means and the input section of the main circuit. And a second switching means which becomes conductive in response to the power supply voltage to the.

[Operation] The first switching means in the present invention responds to the power supply voltage to the second power supply voltage supply terminal and becomes conductive to supply the power supply voltage to the main circuit. In response to the power supply voltage to the second power supply voltage supply terminal, the signal generating means generates a signal, the second switching means becomes conductive, and the signal from the signal generating means is input to the input part of the main circuit. It The main circuit outputs a signal corresponding to this signal from the output section to the output pad.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a main circuit in a wafer state. The signal generation circuit 5 gives a test signal to the three-state buffer 6 during the burn-in test. The three-state buffer 6 inputs a test signal to the input section 7 of the main circuit 1 during the burn-in test. The input section 7 is connected to the input pad 2 as in the conventional case. The output section 3a of the main circuit 1 is connected to the output pad 3. The signal generation circuit 5 is connected to the test power supply voltage supply terminal 8 and is connected to the test power supply voltage supply terminal 8.
Generates a test signal in response to the power supply voltage from. The control terminal of the three-state buffer 6 is connected to the test power supply voltage supply terminal 8 and is also grounded via the pull-down resistor R. When the power supply voltage is not applied to the test power supply voltage supply terminal 8, the pull-down resistor R forces the control terminal of the three-state buffer 6 to low and keeps the three-state buffer 6 in a floating state. Although not shown, the power supply terminal of the three-state buffer 6 is directly connected to the power supply terminal 4.

Reference numeral 9 denotes a switch composed of an N-channel MOS transistor and connected between the main power supply voltage supply terminal 4 and the test power supply voltage supply terminal 8. The switch 9 conducts when a power supply voltage is applied only to the test power supply voltage supply terminal 8, and supplies the power supply voltage not only to the signal generating circuit 5 and the three-state buffer 6 but also to the main circuit 1. Switch 9
On the contrary, when the power supply voltage is applied only to the main power supply voltage supply terminal 4, it becomes non-conducting state, the power supply voltage is supplied only to the main circuit 1, and the power supply voltage is not supplied to the signal generating circuit 5 and the three-state buffer 6. .

Next, the operation of performing the burn-in test of the main circuit 1 will be described. In this case, the main circuit 1 in the wafer state is kept at a predetermined temperature in the constant temperature bath. During the burn-in test, the voltage is supplied only to the test power supply voltage supply terminal 8. Then,
The switch 9 becomes conductive, the power supply voltage is supplied to the main circuit 1 from the test power supply voltage supply terminal 8, and the main circuit 1 operates.
Further, the signal generating circuit 5 is supplied from the test power supply voltage supply terminal 8.
The power supply voltage is also supplied to the control terminal of the three-state buffer 6. Therefore, the signal generating circuit 5 generates a test signal, and the three-state buffer 6 becomes conductive, so that the test signal is input to the input section 7 of the main circuit 1. As described above, the main circuit 1 is in the operating state,
The main circuit 1 receives the test signal from the signal generating circuit 5 and outputs a signal according to this test signal. This output signal is measured to determine whether it is within specifications, and a burn-in test of the main circuit 1 is performed.

During normal operation of the semiconductor integrated circuit after packaging, the power supply voltage is supplied only from the external connection pin to the main power supply voltage supply terminal 4. (In this case, the test power supply voltage supply terminal 8 does not need to be connected to the external connection pin.) Then, the switch 9 becomes non-conductive, and the power supply voltage is supplied to the control terminals of the signal generating circuit 5 and the three-state buffer 6. Not done. As a result, the signal generating circuit 5 does not generate a test signal, and the three-state buffer 6 is brought into a floating state by the pull-down resistor R. Therefore, no signal is input to the input section 7 of the main circuit 1 from the three-state buffer 6, and the main circuit 1 normally operates according to the signal to the input pad 2.

In the above-mentioned embodiment, the case of the burn-in test of the main circuit 1 in the wafer state has been described, but it can be applied to the case of performing the burn-in test after packaging, and the same effect as that of the above-mentioned embodiment can be obtained. In this case, the main power supply voltage supply terminal 4 and the test power supply voltage supply terminal 8 may be taken out to the external connection pins and the power supply voltage may be supplied to these terminals.

Further, although the case of the burn-in test has been described in the above embodiment, it is widely applied to the case of performing the test of the semiconductor integrated circuit using the signal generating circuit, and is not limited to the burn-in test.

Further, in the above embodiment, the switch 9 is an N channel MOS.
Although the case where the switch is configured by the transistor has been described, any switch may be used as long as the switch is conductive only when the power supply voltage for test 8 is supplied with the power supply voltage.

〔The invention's effect〕

As described above, according to the present invention, it is provided between the signal paths of the second power supply voltage supply terminal and the power supply voltage input section of the main circuit, and responds to the power supply voltage to the second power supply voltage supply terminal. It is connected to the first switching means that conducts and the second power supply voltage supply terminal, and responds to the power supply voltage to the second power supply voltage supply terminal, and outputs a predetermined test signal to the input section of the main circuit. A second signal generating means, which is provided between the signal generating means and the signal path between the signal generating means and the input section of the main circuit, and which becomes conductive in response to the power supply voltage to the second power supply voltage supply terminal.
Since the switching means is provided, it is not necessary to provide a signal generator outside the semiconductor integrated circuit when testing the semiconductor integrated circuit, and the wiring of the signal line from outside the semiconductor integrated circuit is not necessary and the wafer state There is an effect that the main circuit can be tested with.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit. In the figure, 1 is a main circuit, 2 is an input pad, 3 is an output pad, 3a is an output section, 4 is a main power supply voltage supply terminal, 5 is a signal generation circuit, 6 is a three-state buffer, 7 is an input section,
Reference numeral 8 is a test power supply voltage supply terminal, and 9 is a switch. In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display area H01L 27/04 // G01R 31/26 H

Claims (1)

[Claims] 1. An input unit, an output unit, and a power supply voltage input unit, which operate when a power supply voltage is applied to the power supply voltage input unit and output a signal corresponding to a signal to the input unit. A semiconductor integrated circuit having a main circuit for outputting from an input section, the input pad connected to the input section, the output pad connected to the output section, and the first connected to the power supply voltage input section of the main circuit. No. 1 power supply voltage supply terminal, a second power supply voltage supply terminal connected to the power supply voltage input section of the main circuit, and a signal path between the second power supply voltage supply terminal and the power supply voltage input section of the main circuit First switching means provided between the first power supply voltage supply terminal and the second switching means for conducting in response to the power supply voltage to the second power supply voltage supply terminal; and the second power supply voltage supply terminal connected to the second power supply voltage supply terminal. Responsive to the power supply voltage to the predetermined A signal generating means for supplying a test signal to the input section of the main circuit, and a power supply voltage to the second power supply voltage supply terminal, which is provided between the signal generating means and the signal path between the input section of the main circuit. A semiconductor integrated circuit comprising: a second switching means which responds to turn on.